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Taken from list archive at http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2001-July/004064.html

Initial definitions
-------------------

The following symbol definitions rely on you knowing the translation that
__virt_to_phys() does for your machine.  This macro converts the passed
virtual address to a physical address.  Normally, it is simply:

		phys = virt - PAGE_OFFSET + PHYS_OFFSET


Decompressor Symbols
--------------------

ZTEXTADDR
	Start address of decompressor.  There's no point in talking about
	virtual or physical addresses here, since the MMU will be off at
	the time when you call the decompressor code.  You normally call
	the kernel at this address to start it booting.  This doesn't have
	to be located in RAM, it can be in flash or other read-only or
	read-write addressable medium.

ZBSSADDR
	Start address of zero-initialised work area for the decompressor.
	This must be pointing at RAM.  The decompressor will zero initialise
	this for you.  Again, the MMU will be off.

ZRELADDR
	This is the address where the decompressed kernel will be written,
	and eventually executed.  The following constraint must be valid:

		__virt_to_phys(TEXTADDR) == ZRELADDR

	The initial part of the kernel is carefully coded to be position
	independent.

INITRD_PHYS
	Physical address to place the initial RAM disk.  Only relevant if
	you are using the bootpImage stuff (which only works on the old
	struct param_struct).

INITRD_VIRT
	Virtual address of the initial RAM disk.  The following  constraint
	must be valid:

		__virt_to_phys(INITRD_VIRT) == INITRD_PHYS

PARAMS_PHYS
	Physical address of the struct param_struct or tag list, giving the
	kernel various parameters about its execution environment.


Kernel Symbols
--------------

PHYS_OFFSET
	Physical start address of the first bank of RAM.

PAGE_OFFSET
	Virtual start address of the first bank of RAM.  During the kernel
	boot phase, virtual address PAGE_OFFSET will be mapped to physical
	address PHYS_OFFSET, along with any other mappings you supply.
	This should be the same value as TASK_SIZE.

TASK_SIZE
	The maximum size of a user process in bytes.  Since user space
	always starts at zero, this is the maximum address that a user
	process can access+1.  The user space stack grows down from this
	address.

	Any virtual address below TASK_SIZE is deemed to be user process
	area, and therefore managed dynamically on a process by process
	basis by the kernel.  I'll call this the user segment.

	Anything above TASK_SIZE is common to all processes.  I'll call
	this the kernel segment.

	(In other words, you can't put IO mappings below TASK_SIZE, and
	hence PAGE_OFFSET).

TEXTADDR
	Virtual start address of kernel, normally PAGE_OFFSET + 0x8000.
	This is where the kernel image ends up.  With the latest kernels,
	it must be located at 32768 bytes into a 128MB region.  Previous
	kernels placed a restriction of 256MB here.

DATAADDR
	Virtual address for the kernel data segment.  Must not be defined
	when using the decompressor.

VMALLOC_START
VMALLOC_END
	Virtual addresses bounding the vmalloc() area.  There must not be
	any static mappings in this area; vmalloc will overwrite them.
	The addresses must also be in the kernel segment (see above).
	Normally, the vmalloc() area starts VMALLOC_OFFSET bytes above the
	last virtual RAM address (found using variable high_memory).

VMALLOC_OFFSET
	Offset normally incorporated into VMALLOC_START to provide a hole
	between virtual RAM and the vmalloc area.  We do this to allow
	out of bounds memory accesses (eg, something writing off the end
	of the mapped memory map) to be caught.  Normally set to 8MB.

Architecture Specific Macros
----------------------------

BOOT_MEM(pram,pio,vio)
	`pram' specifies the physical start address of RAM.  Must always
	be present, and should be the same as PHYS_OFFSET.

	`pio' is the physical address of an 8MB region containing IO for
	use with the debugging macros in arch/arm/kernel/debug-armv.S.

	`vio' is the virtual address of the 8MB debugging region.

	It is expected that the debugging region will be re-initialised
	by the architecture specific code later in the code (via the
	MAPIO function).

BOOT_PARAMS
	Same as, and see PARAMS_PHYS.

FIXUP(func)
	Machine specific fixups, run before memory subsystems have been
	initialised.

MAPIO(func)
	Machine specific function to map IO areas (including the debug
	region above).

INITIRQ(func)
	Machine specific function to initialise interrupts.
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// SPDX-License-Identifier: GPL-2.0
//
// spi-mt7621.c -- MediaTek MT7621 SPI controller driver
//
// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
//
// Some parts are based on spi-orion.c:
//   Author: Shadi Ammouri <shadi@marvell.com>
//   Copyright (C) 2007-2008 Marvell Ltd.

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/reset.h>
#include <linux/spi/spi.h>

#define DRIVER_NAME		"spi-mt7621"

/* in usec */
#define RALINK_SPI_WAIT_MAX_LOOP 2000

/* SPISTAT register bit field */
#define SPISTAT_BUSY		BIT(0)

#define MT7621_SPI_TRANS	0x00
#define SPITRANS_BUSY		BIT(16)

#define MT7621_SPI_OPCODE	0x04
#define MT7621_SPI_DATA0	0x08
#define MT7621_SPI_DATA4	0x18
#define SPI_CTL_TX_RX_CNT_MASK	0xff
#define SPI_CTL_START		BIT(8)

#define MT7621_SPI_MASTER	0x28
#define MASTER_MORE_BUFMODE	BIT(2)
#define MASTER_FULL_DUPLEX	BIT(10)
#define MASTER_RS_CLK_SEL	GENMASK(27, 16)
#define MASTER_RS_CLK_SEL_SHIFT	16
#define MASTER_RS_SLAVE_SEL	GENMASK(31, 29)

#define MT7621_SPI_MOREBUF	0x2c
#define MT7621_SPI_POLAR	0x38
#define MT7621_SPI_SPACE	0x3c

#define MT7621_CPHA		BIT(5)
#define MT7621_CPOL		BIT(4)
#define MT7621_LSB_FIRST	BIT(3)

struct mt7621_spi {
	struct spi_controller	*master;
	void __iomem		*base;
	unsigned int		sys_freq;
	unsigned int		speed;
	struct clk		*clk;
	int			pending_write;
};

static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
{
	return spi_controller_get_devdata(spi->master);
}

static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
{
	return ioread32(rs->base + reg);
}

static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
{
	iowrite32(val, rs->base + reg);
}

static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
{
	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	int cs = spi->chip_select;
	u32 polar = 0;
	u32 master;

	/*
	 * Select SPI device 7, enable "more buffer mode" and disable
	 * full-duplex (only half-duplex really works on this chip
	 * reliably)
	 */
	master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
	master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
	master &= ~MASTER_FULL_DUPLEX;
	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);

	rs->pending_write = 0;

	if (enable)
		polar = BIT(cs);
	mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
}

static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
{
	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	u32 rate;
	u32 reg;

	dev_dbg(&spi->dev, "speed:%u\n", speed);

	rate = DIV_ROUND_UP(rs->sys_freq, speed);
	dev_dbg(&spi->dev, "rate-1:%u\n", rate);

	if (rate > 4097)
		return -EINVAL;

	if (rate < 2)
		rate = 2;

	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
	reg &= ~MASTER_RS_CLK_SEL;
	reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
	rs->speed = speed;

	reg &= ~MT7621_LSB_FIRST;
	if (spi->mode & SPI_LSB_FIRST)
		reg |= MT7621_LSB_FIRST;

	/*
	 * This SPI controller seems to be tested on SPI flash only and some
	 * bits are swizzled under other SPI modes probably due to incorrect
	 * wiring inside the silicon. Only mode 0 works correctly.
	 */
	reg &= ~(MT7621_CPHA | MT7621_CPOL);

	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);

	return 0;
}

static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
{
	int i;

	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
		u32 status;

		status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
		if ((status & SPITRANS_BUSY) == 0)
			return 0;
		cpu_relax();
		udelay(1);
	}

	return -ETIMEDOUT;
}

static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
					int rx_len, u8 *buf)
{
	int tx_len;

	/*
	 * Combine with any pending write, and perform one or more half-duplex
	 * transactions reading 'len' bytes. Data to be written is already in
	 * MT7621_SPI_DATA.
	 */
	tx_len = rs->pending_write;
	rs->pending_write = 0;

	while (rx_len || tx_len) {
		int i;
		u32 val = (min(tx_len, 4) * 8) << 24;
		int rx = min(rx_len, 32);

		if (tx_len > 4)
			val |= (tx_len - 4) * 8;
		val |= (rx * 8) << 12;
		mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);

		tx_len = 0;

		val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
		val |= SPI_CTL_START;
		mt7621_spi_write(rs, MT7621_SPI_TRANS, val);

		mt7621_spi_wait_till_ready(rs);

		for (i = 0; i < rx; i++) {
			if ((i % 4) == 0)
				val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
			*buf++ = val & 0xff;
			val >>= 8;
		}

		rx_len -= i;
	}
}

static inline void mt7621_spi_flush(struct mt7621_spi *rs)
{
	mt7621_spi_read_half_duplex(rs, 0, NULL);
}

static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
					 int tx_len, const u8 *buf)
{
	int len = rs->pending_write;
	int val = 0;

	if (len & 3) {
		val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
		if (len < 4) {
			val <<= (4 - len) * 8;
			val = swab32(val);
		}
	}

	while (tx_len > 0) {
		if (len >= 36) {
			rs->pending_write = len;
			mt7621_spi_flush(rs);
			len = 0;
		}

		val |= *buf++ << (8 * (len & 3));
		len++;
		if ((len & 3) == 0) {
			if (len == 4)
				/* The byte-order of the opcode is weird! */
				val = swab32(val);
			mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
			val = 0;
		}
		tx_len -= 1;
	}

	if (len & 3) {
		if (len < 4) {
			val = swab32(val);
			val >>= (4 - len) * 8;
		}
		mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
	}

	rs->pending_write = len;
}

static int mt7621_spi_transfer_one_message(struct spi_controller *master,
					   struct spi_message *m)
{
	struct mt7621_spi *rs = spi_controller_get_devdata(master);
	struct spi_device *spi = m->spi;
	unsigned int speed = spi->max_speed_hz;
	struct spi_transfer *t = NULL;
	int status = 0;

	mt7621_spi_wait_till_ready(rs);

	list_for_each_entry(t, &m->transfers, transfer_list)
		if (t->speed_hz < speed)
			speed = t->speed_hz;

	if (mt7621_spi_prepare(spi, speed)) {
		status = -EIO;
		goto msg_done;
	}

	/* Assert CS */
	mt7621_spi_set_cs(spi, 1);

	m->actual_length = 0;
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if ((t->rx_buf) && (t->tx_buf)) {
			/*
			 * This controller will shift some extra data out
			 * of spi_opcode if (mosi_bit_cnt > 0) &&
			 * (cmd_bit_cnt == 0). So the claimed fu