linux - Contrib clone of linux

Age	Commit message (Expand)	Author
2012-05-31	kconfig: update compression algorithm info	Randy Dunlap
2011-01-20	kconfig: rename CONFIG_EMBEDDED to CONFIG_EXPERT	David Rientjes
2011-01-13	decompressors: add boot-time XZ support	Lasse Collin
2010-08-23	Kconfig: delete duplicate word	Stephan Sperber
2010-01-11	Add LZO compression support for initramfs and old-style initrd	Albin Tonnerre
2009-03-31	bzip2/lzma: quiet Kconfig warning for INITRAMFS_COMPRESSION_NONE	H. Peter Anvin
2009-03-28	bzip2/lzma: don't ask for compression mode for the default initramfs	H. Peter Anvin
2009-03-28	bzip2/lzma: consistently capitalize LZMA in Kconfig	H. Peter Anvin
2009-03-28	bzip2/lzma: clarify the meaning of the CONFIG_RD_ options	H. Peter Anvin
2009-03-28	bzip2/lzma: move CONFIG_RD_* options under CONFIG_EMBEDDED	H. Peter Anvin
2009-02-19	bzip2/lzma: make internal initramfs compression configurable	Alain Knaff
2009-01-07	bzip2/lzma: move initrd/ramfs options out of BLK_DEV	H. Peter Anvin
2007-05-02	usr/Kconfig: fix typo	Alexander E. Patrakov
2005-08-10	kconfig: move initramfs options to General Setup	Sam Ravnborg

/* * pata_it821x.c - IT821x PATA for new ATA layer * (C) 2005 Red Hat Inc * Alan Cox <alan@lxorguk.ukuu.org.uk> * (C) 2007 Bartlomiej Zolnierkiewicz * * based upon * * it821x.c * * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004 * * Copyright (C) 2004 Red Hat * * May be copied or modified under the terms of the GNU General Public License * Based in part on the ITE vendor provided SCSI driver. * * Documentation available from IT8212F_V04.pdf * http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=5,91 * Some other documents are NDA. * * The ITE8212 isn't exactly a standard IDE controller. It has two * modes. In pass through mode then it is an IDE controller. In its smart * mode its actually quite a capable hardware raid controller disguised * as an IDE controller. Smart mode only understands DMA read/write and * identify, none of the fancier commands apply. The IT8211 is identical * in other respects but lacks the raid mode. * * Errata: * o Rev 0x10 also requires master/slave hold the same DMA timings and * cannot do ATAPI MWDMA. * o The identify data for raid volumes lacks CHS info (technically ok) * but also fails to set the LBA28 and other bits. We fix these in * the IDE probe quirk code. * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode * raid then the controller firmware dies * o Smart mode without RAID doesn't clear all the necessary identify * bits to reduce the command set to the one used * * This has a few impacts on the driver * - In pass through mode we do all the work you would expect * - In smart mode the clocking set up is done by the controller generally * but we must watch the other limits and filter. * - There are a few extra vendor commands that actually talk to the * controller but only work PIO with no IRQ. * * Vendor areas of the identify block in smart mode are used for the * timing and policy set up. Each HDD in raid mode also has a serial * block on the disk. The hardware extra commands are get/set chip status, * rebuild, get rebuild status. * * In Linux the driver supports pass through mode as if the device was * just another IDE controller. If the smart mode is running then * volumes are managed by the controller firmware and each IDE "disk" * is a raid volume. Even more cute - the controller can do automated * hotplug and rebuild. * * The pass through controller itself is a little demented. It has a * flaw that it has a single set of PIO/MWDMA timings per channel so * non UDMA devices restrict each others performance. It also has a * single clock source per channel so mixed UDMA100/133 performance * isn't perfect and we have to pick a clock. Thankfully none of this * matters in smart mode. ATAPI DMA is not currently supported. * * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. * * TODO * - ATAPI and other speed filtering * - RAID configuration ioctls */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/blkdev.h> #include <linux/delay.h> #include <linux/slab.h> #include <scsi/scsi_host.h> #include <linux/libata.h> #define DRV_NAME "pata_it821x" #define DRV_VERSION "0.4.2" struct it821x_dev { unsigned int smart:1, /* Are we in smart raid mode */ timing10:1; /* Rev 0x10 */ u8 clock_mode; /* 0, ATA_50 or ATA_66 */ u8 want[2][2]; /* Mode/Pri log for master slave */ /* We need these for switching the clock when DMA goes on/off The high byte is the 66Mhz timing */ u16 pio[2]; /* Cached PIO values */ u16 mwdma[2]; /* Cached MWDMA values */ u16 udma[2]; /* Cached UDMA values (per drive) */ u16 last_device; /* Master or slave loaded ? */ }; #define ATA_66 0 #define ATA_50 1 #define ATA_ANY 2 #define UDMA_OFF 0 #define MWDMA_OFF 0 /* * We allow users to force the card into non raid mode without * flashing the alternative BIOS. This is also necessary right now * for embedded platforms that cannot run a PC BIOS but are using this * device. */ static int it8212_noraid; /** * it821x_program - program the PIO/MWDMA registers * @ap: ATA port * @adev: Device to program * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8) * * Program the PIO/MWDMA timing for this channel according to the * current clock. These share the same register so are managed by * the DMA start/stop sequence as with the old driver. */ static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); struct it821x_dev *itdev = ap->private_data; int channel = ap->port_no; u8 conf; /* Program PIO/MWDMA timing bits */ if (itdev->clock_mode == ATA_66) conf = timing >> 8; else conf = timing & 0xFF; pci_write_config_byte(pdev, 0x54 + 4 * channel, conf); } /** * it821x_program_udma - program the UDMA registers * @ap: ATA port * @adev: ATA device to update * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz * * Program the UDMA timing for this drive according to the * current clock. Handles the dual clocks and also knows about * the errata on the 0x10 revision. The UDMA errata is partly handled * here and partly in start_dma. */ static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing) { struct it821x_dev *itdev = ap->private_data; struct pci_dev *pdev = to_pci_dev(ap->host->dev); int channel = ap->port_no; int unit = adev->devno; u8 conf; /* Program UDMA timing bits */ if (itdev->clock_mode == ATA_66) conf = timing >> 8; else conf = timing & 0xFF; if (itdev->timing10 == 0) pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf); else { /* Early revision must be programmed for both together */ pci_write_config_byte(pdev, 0x56 + 4 * channel, conf); pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf); } } /** * it821x_clock_strategy * @ap: ATA interface * @adev: ATA device being updated * * Select between the 50 and 66Mhz base clocks to get the best * results for this interface. */ static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); struct it821x_dev *itdev = ap->private_data; u8 unit = adev->devno; struct ata_device *pair = ata_dev_pair(adev); int clock, altclock; u8 v; int sel = 0; /* Look for the most wanted clocking */ if (itdev->want[0][0] > itdev->want[1][0]) { clock = itdev->want[0][1]; altclock = itdev->want[1][1]; } else { <