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path: root/net/bridge/br_device.c
AgeCommit message (Expand)Author
2012-05-09bridge: Convert compare_ether_addr to ether_addr_equalJoe Perches
2012-04-15net: add generic PF_BRIDGE:RTM_ FDB hooksJohn Fastabend
2012-02-23br_device: unify return value of .ndo_set_mac_address if address is invalidDanny Kukawka
2012-02-15net: use eth_hw_addr_random() and reset addr_assign_typeDanny Kukawka
2011-12-08bridge: add local MAC address to forwarding table (v2)stephen hemminger
2011-11-16net: remove NETIF_F_NO_CSUM feature bitMichał Mirosław
2011-11-16net: introduce and use netdev_features_t for device features setsMichał Mirosław
2011-10-07Merge branch 'master' of github.com:davem330/netDavid S. Miller
2011-10-06bridge: allow forwarding some link local framesstephen hemminger
2011-10-06bridge: leave carrier on for empty bridgestephen hemminger
2011-08-17net: remove use of ndo_set_multicast_list in driversJiri Pirko
2011-07-05bridge: Always flood broadcast packetsHerbert Xu
2011-06-19netpoll: copy dev name of slaves to struct netpollWANG Cong
2011-04-28bridge: convert br_features_recompute() to ndo_fix_featuresMichał Mirosław
2011-04-04bridge: allow creating bridge devices with netlinkstephen hemminger
2011-03-14bridge: control carrier based on ports onlinestephen hemminger
2011-02-13bridge: implement [add/del]_slave opsJiri Pirko
2010-12-09net: Abstract away all dst_entry metrics accesses.David S. Miller
2010-10-21bridge: Add support for TX vlan offload.Jesse Gross
2010-08-02Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/ne...David S. Miller
2010-07-30bridge: Fix skb leak when multicast parsing fails on TXHerbert Xu
2010-07-28bridge: add rcu_read_lock on transmitstephen hemminger
2010-07-19bridge: Partially disable netpoll supportHerbert Xu
2010-07-07net: fix 64 bit counters on 32 bit archesEric Dumazet
2010-06-23bridge: 64bit rx/tx countersEric Dumazet
2010-06-15bridge: Fix netpoll supportHerbert Xu
2010-06-15bridge: Remove redundant npinfo NULL settingHerbert Xu
2010-06-10net-next: remove useless union keywordChangli Gao
2010-05-15bridge: change console message interfacestephen hemminger
2010-05-15bridge: netpoll cleanupstephen hemminger
2010-05-10Merge branch 'master' of /repos/git/net-next-2.6Patrick McHardy
2010-05-06bridge: make bridge support netpollWANG Cong
2010-04-27bridge: use is_multicast_ether_addrstephen hemminger
2010-04-15netfilter: bridge-netfilter: simplify IP DNATBart De Schuymer
2010-03-16bridge: per-cpu packet statistics (v3)stephen hemminger
2010-03-16bridge br_multicast: Don't refer to BR_INPUT_SKB_CB(skb)->mrouters_only witho...YOSHIFUJI Hideaki / 吉藤英明
2010-02-28bridge: Add multicast data-path hooksHerbert Xu
2010-02-28bridge: Add multicast start/stop hooksHerbert Xu
2010-02-28bridge: Use BR_INPUT_SKB_CB on xmit pathHerbert Xu
2009-10-07bridge: Allow enable/disable UFO on bridge device via ethtoolSridhar Samudrala
2009-09-01netdev: convert pseudo-devices to netdev_tx_tStephen Hemminger
2009-07-05net: use NETDEV_TX_OK instead of 0 in ndo_start_xmit() functionsPatrick McHardy
2008-11-20netdev: add more functions to netdevice opsStephen Hemminger
2008-11-19bridge: convert to net_device_opsStephen Hemminger
2008-10-23net: Fix disjunct computation of netdev featuresHerbert Xu
2008-09-08netns bridge: allow bridges in netns!Alexey Dobriyan
2008-08-15bridge: show offload settingsStephen Hemminger
2008-07-30bridge: send correct MTU value in PMTU (revised)Simon Wunderlich
2008-06-17bridge: make bridge address settings stickyStephen Hemminger
2008-06-11net: remove CVS keywordsAdrian Bunk
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/*
 * aQuantia Corporation Network Driver
 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 */

/* File hw_atl_llh.h: Declarations of bitfield and register access functions for
 * Atlantic registers.
 */

#ifndef HW_ATL_LLH_H
#define HW_ATL_LLH_H

#include <linux/types.h>

struct aq_hw_s;

/* global */

/* set global microprocessor semaphore */
void reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw,	u32 glb_cpu_sem,
			 u32 semaphore);

/* get global microprocessor semaphore */
u32 reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore);

/* set global register reset disable */
void glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis);

/* set soft reset */
void glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res);

/* get soft reset */
u32 glb_soft_res_get(struct aq_hw_s *aq_hw);

/* stats */

u32 rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw);

/* get rx dma good octet counter lsw */
u32 stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);

/* get rx dma good packet counter lsw */
u32 stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);

/* get tx dma good octet counter lsw */
u32 stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);

/* get tx dma good packet counter lsw */
u32 stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);

/* get rx dma good octet counter msw */
u32 stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);

/* get rx dma good packet counter msw */
u32 stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);

/* get tx dma good octet counter msw */
u32 stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);

/* get tx dma good packet counter msw */
u32 stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);

/* get msm rx errors counter register */
u32 reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw);

/* get msm rx unicast frames counter register */
u32 reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);

/* get msm rx multicast frames counter register */
u32 reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);

/* get msm rx broadcast frames counter register */
u32 reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);

/* get msm rx broadcast octets counter register 1 */
u32 reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);

/* get msm rx unicast octets counter register 0 */
u32 reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);

/* get rx dma statistics counter 7 */
u32 reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw);

/* get msm tx errors counter register */
u32 reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw);

/* get msm tx unicast frames counter register */
u32 reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);

/* get msm tx multicast frames counter register */
u32 reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);

/* get msm tx broadcast frames counter register */
u32 reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);

/* get msm tx multicast octets counter register 1 */
u32 reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw);

/* get msm tx broadcast octets counter register 1 */
u32 reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);

/* get msm tx unicast octets counter register 0 */
u32 reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);

/* get global mif identification */
u32 reg_glb_mif_id_get(struct aq_hw_s *aq_hw);

/* interrupt */

/* set interrupt auto mask lsw */
void itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, u32 irq_auto_masklsw);

/* set interrupt mapping enable rx */
void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx);

/* set interrupt mapping enable tx */
void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx);

/* set interrupt mapping rx */
void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx);

/* set interrupt mapping tx */
void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx);

/* set interrupt mask clear lsw */
void itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_clearlsw);

/* set interrupt mask set lsw */
void itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw);

/* set interrupt register reset disable */
void itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis);

/* set interrupt status clear lsw */
void itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
				 u32 irq_status_clearlsw);

/* get interrupt status lsw */
u32 itr_irq_statuslsw_get(struct aq_hw_s *aq_hw);

/* get reset interrupt */
u32 itr_res_irq_get(struct aq_hw_s *aq_hw);

/* set reset interrupt */
void itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq);

/* rdm */

/* set cpu id */
void rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);

/* set rx dca enable */
void rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en);

/* set rx dca mode */
void rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode);

/* set rx descriptor data buffer size */
void rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
				    u32 rx_desc_data_buff_size,
				    u32 descriptor);

/* set rx descriptor dca enable */
void rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
			    u32 dca);

/* set rx descriptor enable */
void rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
			u32 descriptor);

/* set rx descriptor header splitting */
void rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
				    u32 rx_desc_head_splitting,
				    u32 descriptor);

/* get rx descriptor head pointer */
u32 rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);

/* set rx descriptor length */
void rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
			 u32 descriptor);

/* set rx descriptor write-back interrupt enable */
void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
				  u32 rx_desc_wr_wb_irq_en);

/* set rx header dca enable */
void rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
			    u32 dca);

/* set rx payload dca enable */
void rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, u32 dca);

/* set rx descriptor header buffer size */
void rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
				    u32 rx_desc_head_buff_size,
				    u32 descriptor);

/* set rx descriptor reset */
void rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
			 u32 descriptor);

/* Set RDM Interrupt Moderation Enable */
void rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 rdm_intr_moder_en);

/* reg */

/* set general interrupt mapping register */
void reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, u32 regidx);

/* get general interrupt status register */
u32 reg_gen_irq_status_get(struct aq_hw_s *aq_hw);

/* set interrupt global control register */
void reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl);

/* set interrupt throttle register */
void reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle);

/* set rx dma descriptor base address lsw */
void reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
					u32 rx_dma_desc_base_addrlsw,
					u32 descriptor);

/* set rx dma descriptor base address msw */
void reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
					u32 rx_dma_desc_base_addrmsw,
					u32 descriptor);

/* get rx dma descriptor status register */
u32 reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor);

/* set rx dma descriptor tail pointer register */
void reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
				  u32 rx_dma_desc_tail_ptr,
				  u32 descriptor);

/* set rx filter multicast filter mask register */
void reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
				 u32 rx_flr_mcst_flr_msk);<