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path: root/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c
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2020-07-28bus: fsl-mc: Add ACPI support for fsl-mcMakarand Pawagi
Add ACPI support in the fsl-mc driver. Driver parses MC DSDT table to extract memory and other resources. Interrupt (GIC ITS) information is extracted from the MADT table by drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c. IORT table is parsed to configure DMA. Signed-off-by: Makarand Pawagi <makarand.pawagi@nxp.com> Signed-off-by: Diana Craciun <diana.craciun@oss.nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Link: https://lore.kernel.org/r/20200619082013.13661-13-lorenzo.pieralisi@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-07-28bus/fsl-mc: Refactor the MSI domain creation in the DPRC driverDiana Craciun
The DPRC driver is not taking into account the msi-map property and assumes that the icid is the same as the stream ID. Although this assumption is correct, generalize the code to include a translation between icid and streamID. Furthermore do not just copy the MSI domain from parent (for child containers), but use the information provided by the msi-map property. If the msi-map property is missing from the device tree retain the old behaviour for backward compatibility ie the child DPRC objects inherit the MSI domain from the parent. Signed-off-by: Diana Craciun <diana.craciun@oss.nxp.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200619082013.13661-12-lorenzo.pieralisi@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-07-16irqchip/gic-v3-its: Move minimum LPI requirements to individual bussesMarc Zyngier
At the moment, the core ITS driver imposes the allocation to be in chunks of 32. As we want to relax this on a per bus basis, let's move the the the allocation constraints to each bus. No functionnal change. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-02-26Merge 4.16-rc3 into staging-nextGreg Kroah-Hartman
We want the IIO/Staging fixes in here, and to resolve a merge problem with the move of the fsl-mc code. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-02-22staging: fsl-mc: Move irqchip code out of stagingBogdan Purcareata
Now that the fsl-mc bus core infrastructure is out of staging, the remaining irqchip glue code used (irq-gic-v3-its-fsl-mc-msi.c) goes to drivers/irqchip. Create new Kconfig option for irqchip code that depends on FSL_MC_BUS and ARM_GIC_V3_ITS. This ensures irqchip code only gets built on ARM64 platforms. We can now remove #ifdef GENERIC_MSI_DOMAIN_OPS as it was only needed for x86. Signed-off-by: Stuart Yoder <stuyoder@gmail.com> [rebased, add dpaa2_eth and dpio #include updates] Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [rebased, split irqchip to separate patch] Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> [add Kconfig dependency on ARM_GIC_V3_ITS] Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>