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2016-05-27remove lots of IS_ERR_VALUE abusesArnd Bergmann
Most users of IS_ERR_VALUE() in the kernel are wrong, as they pass an 'int' into a function that takes an 'unsigned long' argument. This happens to work because the type is sign-extended on 64-bit architectures before it gets converted into an unsigned type. However, anything that passes an 'unsigned short' or 'unsigned int' argument into IS_ERR_VALUE() is guaranteed to be broken, as are 8-bit integers and types that are wider than 'unsigned long'. Andrzej Hajda has already fixed a lot of the worst abusers that were causing actual bugs, but it would be nice to prevent any users that are not passing 'unsigned long' arguments. This patch changes all users of IS_ERR_VALUE() that I could find on 32-bit ARM randconfig builds and x86 allmodconfig. For the moment, this doesn't change the definition of IS_ERR_VALUE() because there are probably still architecture specific users elsewhere. Almost all the warnings I got are for files that are better off using 'if (err)' or 'if (err < 0)'. The only legitimate user I could find that we get a warning for is the (32-bit only) freescale fman driver, so I did not remove the IS_ERR_VALUE() there but changed the type to 'unsigned long'. For 9pfs, I just worked around one user whose calling conventions are so obscure that I did not dare change the behavior. I was using this definition for testing: #define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \ unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO)) which ends up making all 16-bit or wider types work correctly with the most plausible interpretation of what IS_ERR_VALUE() was supposed to return according to its users, but also causes a compile-time warning for any users that do not pass an 'unsigned long' argument. I suggested this approach earlier this year, but back then we ended up deciding to just fix the users that are obviously broken. After the initial warning that caused me to get involved in the discussion (fs/gfs2/dir.c) showed up again in the mainline kernel, Linus asked me to send the whole thing again. [ Updated the 9p parts as per Al Viro - Linus ] Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Andrew Morton <akpm@linux-foundation.org> Link: https://lkml.org/lkml/2016/1/7/363 Link: https://lkml.org/lkml/2016/5/27/486 Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-05-19Merge tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds
Pull dmaengine updates from Vinod Koul: "This time round the update brings in following changes: - new tegra driver for ADMA device - support for Xilinx AXI Direct Memory Access Engine and Xilinx AXI Central Direct Memory Access Engine and few updates to this driver - new cyclic capability to sun6i and few updates - slave-sg support in bcm2835 - updates to many drivers like designware, hsu, mv_xor, pxa, edma, qcom_hidma & bam" * tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (84 commits) dmaengine: ioatdma: disable relaxed ordering for ioatdma dmaengine: of_dma: approximate an average distribution dmaengine: core: Use IS_ENABLED() instead of checking for built-in or module dmaengine: edma: Re-evaluate errors when ccerr is triggered w/o error event dmaengine: qcom_hidma: add support for object hierarchy dmaengine: qcom_hidma: add debugfs hooks dmaengine: qcom_hidma: implement lower level hardware interface dmaengine: vdma: Add clock support Documentation: DT: vdma: Add clock support for dmas dmaengine: vdma: Add config structure to differentiate dmas MAINTAINERS: Update Tegra DMA maintainers dmaengine: tegra-adma: Add support for Tegra210 ADMA Documentation: DT: Add binding documentation for NVIDIA ADMA dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine Documentation: DT: vdma: update binding doc for AXI CDMA dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine Documentation: DT: vdma: update binding doc for AXI DMA dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dma dmaengine: slave means at least one of DMA_SLAVE, DMA_CYCLIC dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible SoC ...
2016-05-17Merge branch 'topic/xilinx' into for-linusVinod Koul
2016-05-17Merge branch 'topic/tegra' into for-linusVinod Koul
2016-05-17Merge branch 'topic/sun6i' into for-linusVinod Koul
2016-05-17Merge branch 'topic/qcom' into for-linusVinod Koul
2016-05-17Merge branch 'topic/pxa' into for-linusVinod Koul
2016-05-17Merge branch 'topic/pl08x' into for-linusVinod Koul
2016-05-17Merge branch 'topic/mv_xor' into for-linusVinod Koul
2016-05-17Merge branch 'topic/mpc512x' into for-linusVinod Koul
2016-05-17Merge branch 'topic/hsu' into for-linusVinod Koul
2016-05-17Merge branch 'topic/dw' into for-linusVinod Koul
2016-05-17Merge branch 'topic/bcm' into for-linusVinod Koul
2016-05-17Merge branch 'topic/core' into for-linusVinod Koul
2016-05-14dmaengine: ioatdma: disable relaxed ordering for ioatdmaDave Jiang
ioatdma by default is in snoop mode. Relaxed ordering according to spec does not do anything in snoop mode. However, it causes hang or significant performance degrade when tested with NTB. Disabling in the driver due to some BIOS do not configure it correctly. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-14dmaengine: of_dma: approximate an average distributionNiklas Söderlund
Currently the following DT description would result in dmac0 always being tried first and dmac1 second if dmac0 was unavailable. This results in heavier use of dmac0 then of dmac1. This patch adds an approximate average distribution over the two nodes lessening the load of anyone of them. i2c6: i2c@e60b0000 { ... dmas = <&dmac0 0x77>, <&dmac0 0x78>, <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; ... }; Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-14dmaengine: core: Use IS_ENABLED() instead of checking for built-in or moduleJavier Martinez Canillas
The IS_ENABLED() macro checks if a Kconfig symbol has been enabled either built-in or as a module, use that macro instead of open coding the same. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-14dmaengine: edma: Re-evaluate errors when ccerr is triggered w/o error eventPeter Ujfalusi
When the ccerr handler is called but the error registers indicate no error events we need to command eDMA to re-evaluate the errors. Otherwise we can receive flood of error interrupts. Reported-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-14dmaengine: qcom_hidma: add support for object hierarchySinan Kaya
In order to create a relationship model between the channels and the management object, we are adding support for object hierarchy to the drivers. This patch simplifies the userspace application development. We will not have to traverse different firmware paths based on device tree or ACPI based kernels. No matter what flavor of kernel is used, objects will be represented as platform devices. The new layout is as follows: hidmam_10: hidma-mgmt@0x5A000000 { compatible = "qcom,hidma-mgmt-1.0"; ... hidma_10: hidma@0x5a010000 { compatible = "qcom,hidma-1.0"; ... } } The hidma_mgmt_init detects each instance of the hidma-mgmt-1.0 objects in device tree and calls into the channel driver to create platform devices for each child of the management object. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-14dmaengine: qcom_hidma: add debugfs hooksSinan Kaya
Add debugfs hooks for debugging the execution behavior of the DMA channel. The debugfs hooks get initialized by the probe function and uninitialized by the remove function. A stats file is created in debugfs. The stats file will show the information about each HIDMA channel as well as each asynchronous job queued and completed at a given time. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-14dmaengine: qcom_hidma: implement lower level hardware interfaceSinan Kaya
This patch implements the hardware hooks for the HIDMA channel driver. The main functions of interest are: - hidma_ll_init - hidma_ll_request - hidma_ll_queue_request - hidma_ll_hw_start OS layer calls the hidma_ll_init function during probe to set up the hardware. At this moment, the number of supported descriptors are also given. On each request, a descriptor is allocated from the free pool and filled in with the transfer parameters. Multiple requests can be queued into the hardware via the OS interface. When client is ready for requests to be executed, start method is called. Completions are delivered via callbacks via tasklet. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-13dmaengine: vdma: Add clock supportKedareswara rao Appana
Added basic clock support for axi dma's. The clocks are requested at probe and released at remove. Reviewed-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-13dmaengine: vdma: Add config structure to differentiate dmasKedareswara rao Appana
This patch adds config structure in the driver to differentiate AXI DMA's and to add more features(clock support etc..) to these DMA's. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-13dmaengine: tegra-adma: Add support for Tegra210 ADMAJon Hunter
Add support for the Tegra210 Audio DMA controller that is used for transferring data between system memory and the Audio sub-system. The driver only supports cyclic transfers because this is being solely used for audio. This driver is based upon the work by Dara Ramesh <dramesh@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access EngineKedareswara rao Appana
This patch adds support for the AXI Central Direct Memory Access (AXI CDMA) core to the existing vdma driver, AXI CDMA is a soft Xilinx IP core that provides high-bandwidth Direct Memory Access(DMA) between a memory-mapped source address and a memory-mapped destination address. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access EngineKedareswara rao Appana
This patch adds support for the AXI Direct Memory Access (AXI DMA) core in the existing vdma driver, AXI DMA Core is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream type target peripherals. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dmaKedareswara rao Appana
This patch renames the xilinx_vdma_ prefix to xilinx_dma for the API's and masks that will be shared b/w three DMA IP cores. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12dmaengine: slave means at least one of DMA_SLAVE, DMA_CYCLICAndy Shevchenko
When check for capabilities recognize slave support by either DMA_SLAVE or DMA_CYCLIC bit set. If we don't do that the user can't get a normally worked DMA support for engines that doesn't have one of the mentioned bits set. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-03dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible SoCGregory CLEMENT
Armada 3700 SoC uses the mv_xor driver but don't select anymore the PLAT_ORION symbol. This commit extends the dependency of the mv_xor driver to the more modern SoCs only compatible with ARCH_MVEBU, which allows using it with the Armada 3700 SoC. In the same time it also add the COMPILE_TEST dependency allowing a wider test coverage. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-03dmaengine: mv_xor: add support for Armada 3700 SoCMarcin Wojtas
Armada 3700 SoC comprise a single XOR engine compliant with the ones used in older Marvell SoC's like Armada XP or 38x. The only thing that needs modification is the Mbus configuration, which has to be done on two levels: global and in device. The first one is inherited from the bootloader. The latter can be opened in a default way, leaving arbitration to the bus controller. Hence filled mbus_dram_target_info structure is not needed. Patch "dmaengine: mv_xor: optimize performance by using a subset of the XOR channels" introduced limitation for using XOR engines and channels vs number of available CPU's. Those constraints do not however fit Armada 3700 architecture with two possible CPU's and single, dual-channel engine. Hence in this commit an adjustment for setting maximum available channels is added. This patch enables XOR access to DRAM by opening default window to 4GB space with specific attribute. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-03dmaengine: mv_xor: use SoC type instead of directly the operation modeGregory CLEMENT
Currently the main difference between legacy XOR engine and newer one, is the way the engine modes are setup (either in the descriptor or through the controller registers). In order to be able to take into account new generation of the XOR engine for the ARM64 SoC, we need to identify them by type, and then depending to the type the engine setup will be selected. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-03dmaengine: mv_xor: make the code 64 bits compliantGregory CLEMENT
Fix two warnings which appear when building for 64 bits target: drivers/dma/mv_xor.c: In function ‘mv_xor_prep_dma_xor’: drivers/dma/mv_xor.c:480:3: warning: format ‘%u’ expects argument of type ‘unsigned int’, but argument 6 has type ‘size_t {aka long unsigned int}’ [-Wformat=] "%s src_cnt: %d len: %u dest %pad flags: %ld\n", ^ drivers/dma/mv_xor.c: In function ‘mv_xor_probe’: drivers/dma/mv_xor.c:1223:17: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] op_in_desc = (int)of_id->data; ^ Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-03dmaengine: vdma: Use dma_pool_zallocJulia Lawall
Dma_pool_zalloc combines dma_pool_alloc and memset 0. The semantic patch that makes this transformation is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression d,e; statement S; @@ d = - dma_pool_alloc + dma_pool_zalloc (...); if (!d) S - memset(d, 0, sizeof(*d)); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-03dmaengine: fsldma: Use dma_pool_zallocJulia Lawall
Dma_pool_zalloc combines dma_pool_alloc and memset 0. The semantic patch that makes this transformation is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression d,e; statement S; @@ d = - dma_pool_alloc + dma_pool_zalloc (...); if (!d) S - memset(d, 0, sizeof(*d)); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-03dmaengine: ioatdma: Use dma_pool_zallocJulia Lawall
Dma_pool_zalloc combines dma_pool_alloc and memset 0. The semantic patch that makes this transformation is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression d,e; statement S; @@ d = - dma_pool_alloc + dma_pool_zalloc (...); if (!d) S - memset(d, 0, sizeof(*d)); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-03dmaengine: mmp_pdma: Use dma_pool_zallocJulia Lawall
Dma_pool_zalloc combines dma_pool_alloc and memset 0. The semantic patch that makes this transformation is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression d,e; statement S; @@ d = - dma_pool_alloc + dma_pool_zalloc (...); if (!d) S - memset(d, 0, sizeof(*d)); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-02dmaengine: sun6i: Add cyclic capabilityJean-Francois Moine
DMA cyclic transfers are required by audio streaming. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-02dmaengine: sun6i: Remove useless checkJean-Francois Moine
The transfer direction is now checked in set_config. There is no need to check it twice. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-02dmaengine: sun6i: Set default maxburst size and bus widthJean-Francois Moine
Some DMA clients, as audio, don't set the maxburst size and bus width on the memory side when starting DMA transfers. This patch prevents such transfers to be aborted by providing system default values to the lacking ones. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-02dmaengine: dw: pass platform data via struct dw_dma_chipAndy Shevchenko
We pass struct dw_dma_chip to dw_dma_probe() anyway, thus we may use it to pass a platform data as well. While here, constify the source of the platform data. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-02dmaengine: dw: keep entire platform data in struct dw_dmaAndy Shevchenko
Keep the entire platform data in the struct dw_dma. It makes the driver a bit cleaner. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-02dmaengine: dw: revisit data_width propertyAndy Shevchenko
There several changes are done here: - Convert the property to be in bytes Besides that this is a common practice for such property, the use of a value in bytes much more convenient than handling the encoded one. - Rename data_width to data-width in the device tree bindings The change leaves the support for the old format as well just in case someone will use a newer kernel with an old device tree blob. - While here, replace dwc_fast_ffs() by __ffs() Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-02dmaengine: dw: platform: check nr_masters to be non-zeroAndy Shevchenko
The value of nr_masters equal to 0 is invalid since this DMA controller has to have at least one master. Check this before we proceed with the rest of properties. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-02dmaengine: tegra-apb: proper default init of channel slave_idShardar Shariff Md
Initialize default channel slave_id(req_sel) to invalid id (i.e max supported slave id + 1) to avoid overwriting of slave_id during tegra_dma_slave_config() with client data if slave_id is not initialized through DT Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-02dmaengine: bcm2835: fix typo/added newline in legacy-mode warning messageMartin Sperl
Fix typo in warning message that there is no "interrupt-names" property defined in the device-tree and legacy-mode is used. Also added newline to end of message. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-26dmaengine: pxa_dma: remove duplicate const qualifierEric Engestrom
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-26dmaengine: sun6i: Simplify lli settingJean-Francois Moine
Checking the DMA config before setting the lli list avoids to do tests inside the setting loop. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-26dmaengine: sun6i: Fix impossible settings of burst and bus widthJean-Francois Moine
In the commit 1f9cd915b64bb95f ("dmaengine: sun6i: Fix memcpy operation"), the signed values returned by convert_burst() and convert_buswidth() were stored in an unsigned value. Then, these values were considered as errors when non null. As a result, DMA transfers were rejected when the burst or buswidth had values different from 1, as 8 for the burst or 4 for the bus width. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-26dmaengine: sun6i: Fix the access of the IRQ registerJean-Francois Moine
The IRQ register number is computed, but this number was not used and the register was the one indexed by the channel index instead. Then, only the first DMA channel was working. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-26dmaengine: pxa: handle bus errorsRobert Jarzmik
In the current state, upon bus error the driver will spin endlessly, relaunching the last tx, which will fail again and again : - a bus error happens - pxad_chan_handler() is called - as PXA_DCSR_STOPSTATE is true, the last non-terminated transaction is lauched, which is the one triggering the bus error, as it didn't terminate - moreover, the STOP interrupt fires a new, as the STOPIRQEN is still active Break this logic by stopping the automatic relaunch of a dma channel upon a bus error, even if there are still pending issued requests on it. As dma_cookie_status() seems unable to return DMA_ERROR in its current form, ie. there seems no way to mark a DMA_ERROR on a per-async-tx basis, it is chosen in this patch to remember on the channel which transaction failed, and report it in pxad_tx_status(). It's a bit misleading because if T1, T2, T3 and T4 were queued, and T1 was completed while T2 causes a bus error, the status of T3 and T4 will be reported as DMA_IN_PROGRESS, while the channel is actually stopped. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>