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drivers
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clk
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samsung
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clk-exynos3250.c
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Author
2020-09-17
clk: samsung: Use cached clk_hws instead of __clk_lookup() calls
Sylwester Nawrocki
2019-06-19
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
Thomas Gleixner
2019-05-15
clk: Remove io.h from clk-provider.h
Stephen Boyd
2018-09-06
clk: samsung: Remove excessive include
Marek Szyprowski
2018-02-23
clk: samsung: Add compile time PLL rate validators
Andrzej Hajda
2018-02-23
clk: samsung: exynos3250: Fix PLL rates
Andrzej Hajda
2016-06-02
clk: samsung: Suppress unbinding to prevent theoretical attacks
Krzysztof Kozlowski
2016-06-02
clk: samsung: exynos3250: Move PLL rates data to init section
Krzysztof Kozlowski
2016-06-02
clk: samsung: exynos3250: Constify all clock initializers
Krzysztof Kozlowski
2016-06-02
clk: samsung: exynos3250: Move platform driver and of_device_id to init section
Krzysztof Kozlowski
2016-03-31
clk: samsung: exynos3250: Add MMC2 clock
Chanwoo Choi
2016-03-31
clk: samsung: exynos3250: Add UART2 clock
Pankaj Dubey
2015-07-28
Merge branch 'v4.3-topic/clk-samsung' of git://git.kernel.org/pub/scm/linux/k...
Michael Turquette
2015-07-24
clk: exynos3250: Add cpu clock configuration data and instaniate cpu clock
Chanwoo Choi
2015-07-20
clk: samsung: Properly include clk.h and clkdev.h
Stephen Boyd
2015-03-30
clk: samsung: exynos3250: Add driver for CMU_ISP clock domain
Tomasz Figa
2014-12-23
clk: samsung: exynos3250: Use samsung_cmu_register_one() to simplify code
Chanwoo Choi
2014-09-22
clk: samsung: exynos3250: Register DMC clk provider
Krzysztof Kozlowski
2014-09-22
clk: samsung: exynos3250: fix width field of mout_mmc0/1
Pankaj Dubey
2014-09-22
clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
Pankaj Dubey
2014-09-22
clk: samsung: exynos3250: fix mout_cam_blk parent list
Pankaj Dubey
2014-07-26
clk: samsung: exynos3250: Enable ARMCLK down feature
Krzysztof Kozlowski
2014-06-30
clk: samsung: Register clk provider only after registering its all clocks
Sylwester Nawrocki
2014-05-14
clk: samsung: exynos3250: Add clocks using common clock framework
Tomasz Figa