Age | Commit message (Expand) | Author |
---|---|---|
2019-04-02 | clk: renesas: rcar-gen3: Rename DRIF clocks | Takeshi Kihara |
2019-04-02 | clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC | Takeshi Kihara |
2019-04-02 | clk: renesas: rcar-gen3: Correct parent clock of HS-USB | Kazuya Mizuguchi |
2019-04-02 | clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI | Kazuya Mizuguchi |
2019-04-02 | clk: renesas: r8a77990: Add Z2 clock | Takeshi Kihara |
2018-12-04 | clk: renesas: r8a77990: Correct parent clock of DU | Takeshi Kihara |
2018-09-25 | clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment | Geert Uytterhoeven |
2018-08-31 | clk: renesas: r8a77990: Add missing I2C7 clock | Geert Uytterhoeven |
2018-08-27 | clk: renesas: r8a77990: Correct RCLK handling | Geert Uytterhoeven |
2018-05-09 | clk: renesas: cpg-mssr: Add support for R-Car E3 | Yoshihiro Shimoda |