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path: root/arch/arm/mach-tegra/fuse.h
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2014-07-17soc/tegra: Add efuse driver for TegraPeter De Schrijver
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: move fuse exports to soc/tegra/fuse.hPeter De Schrijver
All fuse related functionality will move to a driver in the following patches. To prepare for this, export all the required functionality in a global header file and move all users of fuse.h to soc/tegra/fuse.h. While we're at it, remove tegra_bct_strapping, as its only user was removed in Commit a7cbe92cef27 ("ARM: tegra: remove tegra EMC scaling driver"). Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: Use a function to get the chip IDThierry Reding
Instead of using a simple variable access to get at the Tegra chip ID, use a function so that we can run additional code. This can be used to determine where the chip ID is being accessed without being available. That in turn will be handy for resolving boot sequence dependencies in order to convert more code to regular initcalls rather than a sequence fixed by Tegra SoC setup code. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-18ARM: tegra: add Tegra124 SoC supportJoseph Lo
Add Tegra124 SoC support that base on CortexA15MP Core. And enable the SMP function that can re-use the same procedure with Tegra114. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-22ARM: tegra: add an assembly marco to check Tegra SoC IDJoseph Lo
There are some Tegra SoC ID checking code around the low level assembly code. Adding a marco to replace them. For the single image to support all the Tegra series, we may also need the marco in other common code. So we make it become a marco for the usage. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-19ARM: tegra: add speedo-based process id for Tegra114Danny Huang
Add speedo-based process identification for Tegra114. Based on the work by: Alex Frid <afrid@nvidia.com> Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren: added include of bug.h] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: fuse: Add chip ID Tegra114 0x35Hiroshi Doyu
Add tegra_chip_id TEGRA114 0x35 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-15ARM: tegra: Tegra30 speedo-based process identificationDanny Huang
This patch adds speedo-based process identification support for Tegra30. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra3/Tegra30/ in log print, s/T30/Tegra30/ in commit description] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-15ARM: tegra: Add speedo-based process identificationDanny Huang
Detect CPU and core process ID by checking speedo corner tables. This can provide a more accurate process ID. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra2/Tegra20/ in log print] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-15ARM: tegra: flexible spare fuse read functionDanny Huang
Change the spare fuse base from a definition to a variable. It provides flexibilty to read spare fuse on different chip. Signed-off-by: Danny Huang <dahuang@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-02-26ARM: tegra: export Tegra chipidPeter De Schrijver
The powergating and reset handling code needs to differentiate between Tegra variants. Therefore we export the chipid here. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-02-26ARM: tegra: cleanup use of chipid registerPeter De Schrijver
The chipid register contains information about the Tegra variant and revision. We want differentiate between Tegra variants for powergating and secondary core bringup. This patch cleans up the reading and decoding of this register. In subsequent patches the variant will exported as a global variable. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-02-06ARM: tegra: fuse: add bct strapping readingOlof Johansson
This is used by the memory setup code to pick the right memory timing table, if needed. Signed-off-by: Olof Johansson <olof@lixom.net>
2012-02-06ARM: tegra: fuse: add functions to access chip revisionOlof Johansson
Add function to get chip revision, and print it out at boot time. Restructure the fuse access to just use cached variables instead of always reading the fuses, and export those variables directly instead of using accessor functions. Add a SKU ID table of currently known values. Based on code originally by Colin Cross <ccross@android.com>. Changes since v1: * Add A01 minor rev support * Don't decode for A03p on anything but T2x Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com>
2010-10-21[ARM] tegra: Add support for reading fusesColin Cross
The Tegra SOC contains fuses to identify the CPU type and bin, and a unique id. The CPU info is required to determine the correct voltages for each cpu and core frequency. Signed-off-by: Colin Cross <ccross@android.com>