diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/powerpc/power9/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/powerpc/power9/other.json | 934 |
1 files changed, 467 insertions, 467 deletions
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/other.json b/tools/perf/pmu-events/arch/powerpc/power9/other.json index 62b864269623..3f69422c21f9 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/other.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/other.json @@ -1,2335 +1,2335 @@ [ - {, + { "EventCode": "0x3084", "EventName": "PM_ISU1_ISS_HOLD_ALL", "BriefDescription": "All ISU rejects" }, - {, + { "EventCode": "0xF880", "EventName": "PM_SNOOP_TLBIE", "BriefDescription": "TLBIE snoop" }, - {, + { "EventCode": "0x4088", "EventName": "PM_IC_DEMAND_REQ", "BriefDescription": "Demand Instruction fetch request" }, - {, + { "EventCode": "0x20A4", "EventName": "PM_TM_TRESUME", "BriefDescription": "TM resume instruction completed" }, - {, + { "EventCode": "0x40008", "EventName": "PM_SRQ_EMPTY_CYC", "BriefDescription": "Cycles in which the SRQ has at least one (out of four) empty slice" }, - {, + { "EventCode": "0x20064", "EventName": "PM_IERAT_RELOAD_4K", "BriefDescription": "IERAT reloaded (after a miss) for 4K pages" }, - {, + { "EventCode": "0x260B4", "EventName": "PM_L3_P2_LCO_RTY", "BriefDescription": "L3 initiated LCO received retry on port 2 (can try 4 times)" }, - {, + { "EventCode": "0x20006", "EventName": "PM_DISP_HELD_ISSQ_FULL", "BriefDescription": "Dispatch held due to Issue q full. Includes issue queue and branch queue" }, - {, + { "EventCode": "0x201E4", "EventName": "PM_MRK_DATA_FROM_L3MISS", "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load" }, - {, + { "EventCode": "0x4E044", "EventName": "PM_DPTEG_FROM_L31_ECO_MOD", "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, - {, + { "EventCode": "0x40B8", "EventName": "PM_BR_MPRED_TAKEN_CR", "BriefDescription": "A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction)." }, - {, + { "EventCode": "0xF8AC", "EventName": "PM_DC_DEALLOC_NO_CONF", "BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)" }, - {, + { "EventCode": "0xD090", "EventName": "PM_LS0_DC_COLLISIONS", "BriefDescription": "Read-write data cache collisions" }, - {, + { "EventCode": "0x40BC", "EventName": "PM_THRD_PRIO_0_1_CYC", "BriefDescription": "Cycles thread running at priority level 0 or 1" }, - {, + { "EventCode": "0x4C054", "EventName": "PM_DERAT_MISS_16G_1G", "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) or 1G (radix mode)" }, - {, + { "EventCode": "0x2084", "EventName": "PM_FLUSH_HB_RESTORE_CYC", "BriefDescription": "Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery" }, - {, + { "EventCode": "0x4F054", "EventName": "PM_RADIX_PWC_MISS", "BriefDescription": "A radix translation attempt missed in the TLB and all levels of page walk cache." }, - {, + { "EventCode": "0x26882", "EventName": "PM_L2_DC_INV", "BriefDescription": "D-cache invalidates sent over the reload bus to the core" }, - {, + { "EventCode": "0x24048", "EventName": "PM_INST_FROM_LMEM", "BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)" }, - {, + { "EventCode": "0xD8B4", "EventName": "PM_LSU0_LRQ_S0_VALID_CYC", "BriefDescription": "Slot 0 of LRQ valid" }, - {, + { "EventCode": "0x2E052", "EventName": "PM_TM_PASSED", "BriefDescription": "Number of TM transactions that passed" }, - {, + { "EventCode": "0xF088", "EventName": "PM_LSU0_STORE_REJECT", "BriefDescription": "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met" }, - {, + { "EventCode": "0x360B2", "EventName": "PM_L3_GRP_GUESS_WRONG_LOW", "BriefDescription": "Prefetch scope predictor selected GS or NNS, but was wrong because scope was LNS" }, - {, + { "EventCode": "0x168A6", "EventName": "PM_TM_CAM_OVERFLOW", "BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to memory" }, - {, + { "EventCode": "0xE8B0", "EventName": "PM_TEND_PEND_CYC", "BriefDescription": "TEND latency per thread" }, - {, + { "EventCode": "0x4884", "EventName": "PM_IBUF_FULL_CYC", "BriefDescription": "Cycles No room in ibuff" }, - {, + { "EventCode": "0xD08C", "EventName": "PM_LSU2_LDMX_FIN", "BriefDescription": "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56])." }, - {, + { "EventCode": "0x300F8", "EventName": "PM_TB_BIT_TRANS", "BriefDescription": "timebase event" }, - {, + { "EventCode": "0x3C040", "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST", "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load" }, - {, + { "EventCode": "0xE0BC", "EventName": "PM_LS0_PTE_TABLEWALK_CYC", "BriefDescription": "Cycles when a tablewalk is pending on this thread on table 0" }, - {, + { "EventCode": "0x3884", "EventName": "PM_ISU3_ISS_HOLD_ALL", "BriefDescription": "All ISU rejects" }, - {, + { "EventCode": "0x468A0", "EventName": "PM_L3_PF_OFF_CHIP_MEM", "BriefDescription": "L3 PF from Off chip memory" }, - {, + { "EventCode": "0x268AA", "EventName": "PM_L3_P1_LCO_DATA", "BriefDescription": "LCO sent with data port 1" }, - {, + { "EventCode": "0xE894", "EventName": "PM_LSU1_TM_L1_HIT", "BriefDescription": "Load tm hit in L1" }, - {, + { "EventCode": "0x5888", "EventName": "PM_IC_INVALIDATE", "BriefDescription": "Ic line invalidated" }, - {, + { "EventCode": "0x2890", "EventName": "PM_DISP_CLB_HELD_TLBIE", "BriefDescription": "Dispatch Hold: Due to TLBIE" }, - {, + { "EventCode": "0x1001C", "EventName": "PM_CMPLU_STALL_THRD", "BriefDescription": "Completion Stalled because the thread was blocked" }, - {, + { "EventCode": "0x368A6", "EventName": "PM_SNP_TM_HIT_T", "BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modified)" }, - {, + { "EventCode": "0x3001A", "EventName": "PM_DATA_TABLEWALK_CYC", "BriefDescription": "Data Tablewalk Cycles. Could be 1 or 2 active tablewalks. Includes data prefetches." }, - {, + { "EventCode": "0xD894", "EventName": "PM_LS3_DC_COLLISIONS", "BriefDescription": "Read-write data cache collisions" }, - {, + { "EventCode": "0x35158", "EventName": "PM_MRK_DATA_FROM_L31_ECO_MOD_CYC", "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load" }, - {, + { "EventCode": "0xF0B4", "EventName": "PM_DC_PREF_CONS_ALLOC", "BriefDescription": "Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase" }, - {, + { "EventCode": "0xF894", "EventName": "PM_LSU3_L1_CAM_CANCEL", "BriefDescription": "ls3 l1 tm cam cancel" }, - {, + { "EventCode": "0x2888", "EventName": "PM_FLUSH_DISP_TLBIE", "BriefDescription": "Dispatch Flush: TLBIE" }, - {, + { "EventCode": "0x4E11E", "EventName": "PM_MRK_DATA_FROM_DMEM_CYC", "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load" }, - {, + { "EventCode": "0x14156", "EventName": "PM_MRK_DATA_FROM_L2_CYC", "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load" }, - {, + { "EventCode": "0x468A6", "EventName": "PM_RD_CLEARING_SC", "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated" }, - {, + { "EventCode": "0xD0B0", "EventName": "PM_HWSYNC", "BriefDescription": "A hwsync instruction was decoded and transferred" }, - {, + { "EventCode": "0x168B0", "EventName": "PM_L3_P1_NODE_PUMP", "BriefDescription": "L3 PF sent with nodal scope port 1, counts even retried requests" }, - {, + { "EventCode": "0xD0BC", "EventName": "PM_LSU0_1_LRQF_FULL_CYC", "BriefDescription": "Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ" }, - {, + { "EventCode": "0x2D148", "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST", "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load" }, - {, + { "EventCode": "0x468AE", "EventName": "PM_L3_P3_CO_RTY", "BriefDescription": "L3 CO received retry port 3 (memory only), every retry counted" }, - {, + { "EventCode": "0x460A8", "EventName": "PM_SN_HIT", "BriefDescription": "Any port snooper hit L3. Up to 4 can happen in a cycle but we only count 1" }, - {, + { "EventCode": "0x360AA", "EventName": "PM_L3_P0_CO_MEM", "BriefDescription": "L3 CO to memory port 0 with or without data" }, - {, + { "EventCode": "0xF0A4", "EventName": "PM_DC_PREF_HW_ALLOC", "BriefDescription": "Prefetch stream allocated by the hardware prefetch mechanism" }, - {, + { "EventCode": "0xF0BC", "EventName": "PM_LS2_UNALIGNED_ST", "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" }, - {, + { "EventCode": "0xD0AC", "EventName": "PM_SRQ_SYNC_CYC", "BriefDescription": "A sync is in the S2Q (edge detect to count)" }, - {, + { "EventCode": "0x401E6", "EventName": "PM_MRK_INST_FROM_L3MISS", "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet" }, - {, + { "EventCode": "0x58A8", "EventName": "PM_DECODE_HOLD_ICT_FULL", "BriefDescription": "Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread" }, - {, + { "EventCode": "0x26082", "EventName": "PM_L2_IC_INV", "BriefDescription": "I-cache Invalidates sent over the realod bus to the core" }, - {, + { "EventCode": "0xC8AC", "EventName": "PM_LSU_FLUSH_RELAUNCH_MISS", "BriefDescription": "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent" }, - {, + { "EventCode": "0x260A4", "EventName": "PM_L3_LD_HIT", "BriefDescription": "L3 Hits for demand LDs" }, - {, + { "EventCode": "0xF0A0", "EventName": "PM_DATA_STORE", "BriefDescription": "All ops that drain from s2q to L2 containing data" }, - {, + { "EventCode": "0x1D148", "EventName": "PM_MRK_DATA_FROM_RMEM", "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load" }, - {, + { "EventCode": "0x16088", "EventName": "PM_L2_LOC_GUESS_CORRECT", "BriefDescription": "L2 guess local (LNS) and guess was correct (ie data local)" }, - {, + { "EventCode": "0x160A4", "EventName": "PM_L3_HIT", "BriefDescription": "L3 Hits (L2 miss hitting L3, including data/instrn/xlate)" }, - {, + { "EventCode": "0xE09C", "EventName": "PM_LSU0_TM_L1_MISS", "BriefDescription": "Load tm L1 miss" }, - {, + { "EventCode": "0x168B4", "EventName": "PM_L3_P1_LCO_RTY", "BriefDescription": "L3 initiated LCO received retry on port 1 (can try 4 times)" }, - {, + { "EventCode": "0x268AC", "EventName": "PM_L3_RD_USAGE", "BriefDescription": "Rotating sample of 16 RD actives" }, - {, + { "EventCode": "0x1415C", "EventName": "PM_MRK_DATA_FROM_L3_MEPF_CYC", "BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load" }, - {, + { "EventCode": "0xE880", "EventName": "PM_L1_SW_PREF", "BriefDescription": "Software L1 Prefetches, including SW Transient Prefetches" }, - {, + { "EventCode": "0x288C", "EventName": "PM_DISP_CLB_HELD_BAL", "BriefDescription": "Dispatch/CLB Hold: Balance Flush" }, - {, + { "EventCode": "0x101EA", "EventName": "PM_MRK_L1_RELOAD_VALID", "BriefDescription": "Marked demand reload" }, - {, + { "EventCode": "0x1D156", "EventName": "PM_MRK_LD_MISS_L1_CYC", "BriefDescription": "Marked ld latency" }, - {, + { "EventCode": "0x4C01A", "EventName": "PM_CMPLU_STALL_DMISS_L3MISS", "BriefDescription": "Completion stall due to cache miss resolving missed the L3" }, - {, + { "EventCode": "0x2006C", "EventName": "PM_RUN_CYC_SMT4_MODE", "BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT4 mode" }, - {, + { "EventCode": "0x1D14E", "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC", "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load" }, - {, + { "EventCode": "0xF888", "EventName": "PM_LSU1_STORE_REJECT", "BriefDescription": "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met" }, - {, + { "EventCode": "0xC098", "EventName": "PM_LS2_UNALIGNED_LD", "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" }, - {, + { "EventCode": "0x20058", "EventName": "PM_DARQ1_10_12_ENTRIES", "BriefDescription": "Cycles in which 10 or more DARQ1 entries (out of 12) are in use" }, - {, + { "EventCode": "0x360A6", "EventName": "PM_SNP_TM_HIT_M", "BriefDescription": "TM snoop that is a store hits line in L3 in M or Mu state (exclusive modified)" }, - {, + { "EventCode": "0x5898", "EventName": "PM_LINK_STACK_INVALID_PTR", "BriefDescription": "It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable." }, - {, + { "EventCode": "0x46088", "EventName": "PM_L2_CHIP_PUMP", "BriefDescription": "RC requests that were local (aka chip) pump attempts" }, - {, + { "EventCode": "0x28A0", "EventName": "PM_TM_TSUSPEND", "BriefDescription": "TM suspend instruction completed" }, - {, + { "EventCode": "0x20054", "EventName": "PM_L1_PREF", "BriefDescription": "A data line was written to the L1 due to a hardware or software prefetch" }, - {, + { "EventCode": "0x2608E", "EventName": "PM_TM_LD_CONF", "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)" }, - {, + { "EventCode": "0x1D144", "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT", "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load" }, - {, + { "EventCode": "0x400FA", "EventName": "PM_RUN_INST_CMPL", "BriefDescription": "Run_Instructions" }, - {, + { "EventCode": "0x15154", "EventName": "PM_SYNC_MRK_L3MISS", "BriefDescription": "Marked L3 misses that can throw a synchronous interrupt" }, - {, + { "EventCode": "0xE0B4", "EventName": "PM_LS0_TM_DISALLOW", "BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it" }, - {, + { "EventCode": "0x26884", "EventName": "PM_DSIDE_MRU_TOUCH", "BriefDescription": "D-side L2 MRU touch commands sent to the L2" }, - {, + { "EventCode": "0x30134", "EventName": "PM_MRK_ST_CMPL_INT", "BriefDescription": "marked store finished with intervention" }, - {, + { "EventCode": "0xC0B8", "EventName": "PM_LSU_FLUSH_SAO", "BriefDescription": "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush" }, - {, + { "EventCode": "0x50A8", "EventName": "PM_EAT_FORCE_MISPRED", "BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued" }, - {, + { "EventCode": "0xC094", "EventName": "PM_LS0_UNALIGNED_LD", "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" }, - {, + { "EventCode": "0xF8BC", "EventName": "PM_LS3_UNALIGNED_ST", "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" }, - {, + { "EventCode": "0x460AE", "EventName": "PM_L3_P2_CO_RTY", "BriefDescription": "L3 CO received retry port 2 (memory only), every retry counted" }, - {, + { "EventCode": "0x58B0", "EventName": "PM_BTAC_GOOD_RESULT", "BriefDescription": "BTAC predicts a taken branch and the BHT agrees, and the target address is correct" }, - {, + { "EventCode": "0x1C04C", "EventName": "PM_DATA_FROM_LL4", "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load" }, - {, + { "EventCode": "0x3608E", "EventName": "PM_TM_ST_CONF", "BriefDescription": "TM Store (fav or non-fav) ran into conflict (failed)" }, - {, + { "EventCode": "0xF8A0", "EventName": "PM_NON_DATA_STORE", "BriefDescription": "All ops that drain from s2q to L2 and contain no data" }, - {, + { "EventCode": "0x3F146", "EventName": "PM_MRK_DPTEG_FROM_L21_SHR", "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, - {, + { "EventCode": "0x40A0", "EventName": "PM_BR_UNCOND", "BriefDescription": "Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve." }, - {, + { "EventCode": "0xF8A8", "EventName": "PM_DC_PREF_FUZZY_CONF", "BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)" }, - {, + { "EventCode": "0xF8A4", "EventName": "PM_DC_PREF_SW_ALLOC", "BriefDescription": "Prefetch stream allocated by software prefetching" }, - {, + { "EventCode": "0xE0A0", "EventName": "PM_LSU2_TM_L1_MISS", "BriefDescription": "Load tm L1 miss" }, - {, + { "EventCode": "0xC880", "EventName": "PM_LS1_LD_VECTOR_FIN", "BriefDescription": "LS1 finished load vector op" }, - {, + { "EventCode": "0x2894", "EventName": "PM_TM_OUTER_TEND", "BriefDescription": "Completion time outer tend" }, - {, + { "EventCode": "0xF098", "EventName": "PM_XLATE_HPT_MODE", "BriefDescription": "LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode)" }, - {, + { "EventCode": "0x2C04E", "EventName": "PM_LD_MISS_L1_FIN", "BriefDescription": "Number of load instructions that finished with an L1 miss. Note that even if a load spans multiple slices this event will increment only once per load op." }, - {, + { "EventCode": "0x30162", "EventName": "PM_MRK_LSU_DERAT_MISS", "BriefDescription": "Marked derat reload (miss) for any page size" }, - {, + { "EventCode": "0x160A0", "EventName": "PM_L3_PF_MISS_L3", "BriefDescription": "L3 PF missed in L3" }, - {, + { "EventCode": "0x1C04A", "EventName": "PM_DATA_FROM_RL2L3_SHR", "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load" }, - {, + { "EventCode": "0x268B0", "EventName": "PM_L3_P1_GRP_PUMP", "BriefDescription": "L3 PF sent with grp scope port 1, counts even retried requests" }, - {, + { "EventCode": "0x30016", "EventName": "PM_CMPLU_STALL_SRQ_FULL", "BriefDescription": "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full" }, - {, + { "EventCode": "0x40B4", "EventName": "PM_BR_PRED_TA", "BriefDescription": "Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE" }, - {, + { "EventCode": "0x40AC", "EventName": "PM_BR_MPRED_CCACHE", "BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction" }, - {, + { "EventCode": "0x3688A", "EventName": "PM_L2_RTY_LD", "BriefDescription": "RC retries on PB for any load from core (excludes DCBFs)" }, - {, + { "EventCode": "0xE08C", "EventName": "PM_LSU0_ERAT_HIT", "BriefDescription": "Primary ERAT hit. There is no secondary ERAT" }, - {, + { "EventCode": "0xE088", "EventName": "PM_LS2_ERAT_MISS_PREF", "BriefDescription": "LS0 Erat miss due to prefetch" }, - {, + { "EventCode": "0xF0A8", "EventName": "PM_DC_PREF_CONF", "BriefDescription": "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams" }, - {, + { "EventCode": "0x16888", "EventName": "PM_L2_LOC_GUESS_WRONG", "BriefDescription": "L2 guess local (LNS) and guess was not correct (ie data not on chip)" }, - {, + { "EventCode": "0xC888", "EventName": "PM_LSU_DTLB_MISS_64K", "BriefDescription": "Data TLB Miss page size 64K" }, - {, + { "EventCode": "0xE0A4", "EventName": "PM_TMA_REQ_L2", "BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding" }, - {, + { "EventCode": "0xC088", "EventName": "PM_LSU_DTLB_MISS_4K", "BriefDescription": "Data TLB Miss page size 4K" }, - {, + { "EventCode": "0x3C042", "EventName": "PM_DATA_FROM_L3_DISP_CONFLICT", "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load" }, - {, + { "EventCode": "0x168AA", "EventName": "PM_L3_P1_LCO_NO_DATA", "BriefDescription": "Dataless L3 LCO sent port 1" }, - {, + { "EventCode": "0x3D140", "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC", "BriefDescription": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load" }, - {, + { "EventCode": "0xC89C", "EventName": "PM_LS1_LAUNCH_HELD_PREF", "BriefDescription": "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle" }, - {, + { "EventCode": "0x4894", "EventName": "PM_IC_RELOAD_PRIVATE", "BriefDescription": "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat" }, - {, + { "EventCode": "0x1688E", "EventName": "PM_TM_LD_CAUSED_FAIL", "BriefDescription": "Non-TM Load caused any thread to fail" }, - {, + { "EventCode": "0x26084", "EventName": "PM_L2_RCLD_DISP_FAIL_OTHER", "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflicts with an L2 machines (e.g. Read-Claim/Snoop machine not available)" }, - {, + { "EventCode": "0x101E4", "EventName": "PM_MRK_L1_ICACHE_MISS", "BriefDescription": "sampled Instruction suffered an icache Miss" }, - {, + { "EventCode": "0x20A0", "EventName": "PM_TM_NESTED_TBEGIN", "BriefDescription": "Completion Tm nested tbegin" }, - {, + { "EventCode": "0x368AA", "EventName": "PM_L3_P1_CO_MEM", "BriefDescription": "L3 CO to memory port 1 with or without data" }, - {, + { "EventCode": "0xC8A4", "EventName": "PM_LSU3_FALSE_LHS", "BriefDescription": "False LHS match detected" }, - {, + { "EventCode": "0xF0B0", "EventName": "PM_L3_LD_PREF", "BriefDescription": "L3 load prefetch, sourced from a hardware or software stream, was sent to the nest" }, - {, + { "EventCode": "0x4D012", "EventName": "PM_PMC3_SAVED", "BriefDescription": "PMC3 Rewind Value saved" }, - {, + { "EventCode": "0xE888", "EventName": "PM_LS3_ERAT_MISS_PREF", "BriefDescription": "LS1 Erat miss due to prefetch" }, - {, + { "EventCode": "0x368B4", "EventName": "PM_L3_RD0_BUSY", "BriefDescription": "Lifetime, sample of RD machine 0 valid" }, - {, + { "EventCode": "0x46080", "EventName": "PM_L2_DISP_ALL_L2MISS", "BriefDescription": "All successful D-side-Ld/St or I-side-instruction-fetch dispatches for this thread that were an L2 miss" }, - {, + { "EventCode": "0xF8B8", "EventName": "PM_LS1_UNALIGNED_ST", "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" }, - {, + { "EventCode": "0x408C", "EventName": "PM_L1_DEMAND_WRITE", "BriefDescription": "Instruction Demand sectors written into IL1" }, - {, + { "EventCode": "0x368A8", "EventName": "PM_SN_INVL", "BriefDescription": "Any port snooper detects a store to a line in the Sx state and invalidates the line. Up to 4 can happen in a cycle but we only count 1" }, - {, + { "EventCode": "0x160B2", "EventName": "PM_L3_LOC_GUESS_CORRECT", "BriefDescription": "Prefetch scope predictor selected LNS and was correct" }, - {, + { "EventCode": "0x48B4", "EventName": "PM_DECODE_FUSION_CONST_GEN", "BriefDescription": "32-bit constant generation" }, - {, + { "EventCode": "0x4D146", "EventName": "PM_MRK_DATA_FROM_L21_MOD", "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load" }, - {, + { "EventCode": "0xE080", "EventName": "PM_S2Q_FULL", "BriefDescription": "Cycles during which the S2Q is full" }, - {, + { "EventCode": "0x268B4", "EventName": "PM_L3_P3_LCO_RTY", "BriefDescription": "L3 initiated LCO received retry on port 3 (can try 4 times)" }, - {, + { "EventCode": "0xD8B8", "EventName": "PM_LSU0_LMQ_S0_VALID", "BriefDescription": "Slot 0 of LMQ valid" }, - {, + { "EventCode": "0x2098", "EventName": "PM_TM_NESTED_TEND", "BriefDescription": "Completion time nested tend" }, - {, + { "EventCode": "0x368A0", "EventName": "PM_L3_PF_OFF_CHIP_CACHE", "BriefDescription": "L3 PF from Off chip cache" }, - {, + { "EventCode": "0x20056", "EventName": "PM_TAKEN_BR_MPRED_CMPL", "BriefDescription": "Total number of taken branches that were incorrectly predicted as not-taken. This event counts branches completed and does not include speculative instructions" }, - {, + { "EventCode": "0x4688A", "EventName": "PM_L2_SYS_PUMP", "BriefDescription": "RC requests that were system pump attempts" }, - {, + { "EventCode": "0xE090", "EventName": "PM_LSU2_ERAT_HIT", "BriefDescription": "Primary ERAT hit. There is no secondary ERAT" }, - {, + { "EventCode": "0x4001C", "EventName": "PM_INST_IMC_MATCH_CMPL", "BriefDescription": "IMC Match Count" }, - {, + { "EventCode": "0x40A8", "EventName": "PM_BR_PRED_LSTACK", "BriefDescription": "Conditional Branch Completed that used the Link Stack for Target Prediction" }, - {, + { "EventCode": "0x268A2", "EventName": "PM_L3_CI_MISS", "BriefDescription": "L3 castins miss (total count)" }, - {, + { "EventCode": "0x289C", "EventName": "PM_TM_NON_FAV_TBEGIN", "BriefDescription": "Dispatch time non favored tbegin" }, - {, + { "EventCode": "0xF08C", "EventName": "PM_LSU2_STORE_REJECT", "BriefDescription": "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met" }, - {, + { "EventCode": "0x360A0", "EventName": "PM_L3_PF_ON_CHIP_CACHE", "BriefDescription": "L3 PF from On chip cache" }, - {, + { "EventCode": "0x35152", "EventName": "PM_MRK_DATA_FROM_L2MISS_CYC", "BriefDescription": "Duration in cycles to reload from a location other than the local core's L2 due to a marked load" }, - {, + { "EventCode": "0x160AC", "EventName": "PM_L3_SN_USAGE", "BriefDescription": "Rotating sample of 16 snoop valids" }, - {, + { "EventCode": "0x1608C", "EventName": "PM_RC0_BUSY", "BriefDescription": "RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point)" }, - {, + { "EventCode": "0x36082", "EventName": "PM_L2_LD_DISP", "BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread" }, - {, + { "EventCode": "0xF8B0", "EventName": "PM_L3_SW_PREF", "BriefDescription": "L3 load prefetch, sourced from a software prefetch stream, was sent to the nest" }, - {, + { "EventCode": "0xF884", "EventName": "PM_TABLEWALK_CYC_PREF", "BriefDescription": "tablewalk qualified for pte prefetches" }, - {, + { "EventCode": "0x4D144", "EventName": "PM_MRK_DATA_FROM_L31_ECO_MOD", "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load" }, - {, + { "EventCode": "0x16884", "EventName": "PM_L2_RCLD_DISP_FAIL_ADDR", "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflicts with an L2 machines already working on this line (e.g. ld-hit-stq or Read-claim/Castout/Snoop machines)" }, - {, + { "EventCode": "0x460A0", "EventName": "PM_L3_PF_ON_CHIP_MEM", "BriefDescription": "L3 PF from On chip memory" }, - {, + { "EventCode": "0xF084", "EventName": "PM_PTE_PREFETCH", "BriefDescription": "PTE prefetches" }, - {, + { "EventCode": "0x2D026", "EventName": "PM_RADIX_PWC_L1_PDE_FROM_L2", "BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache" }, - {, + { "EventCode": "0x48B0", "EventName": "PM_BR_MPRED_PCACHE", "BriefDescription": "Conditional Branch Completed that was Mispredicted due to pattern cache prediction" }, - {, + { "EventCode": "0x2C126", "EventName": "PM_MRK_DATA_FROM_L2", "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load" }, - {, + { "EventCode": "0xE0AC", "EventName": "PM_TM_FAIL_TLBIE", "BriefDescription": "Transaction failed because there was a TLBIE hit in the bloom filter" }, - {, + { "EventCode": "0x260AA", "EventName": "PM_L3_P0_LCO_DATA", "BriefDescription": "LCO sent with data port 0" }, - {, + { "EventCode": "0x4888", "EventName": "PM_IC_PREF_REQ", "BriefDescription": "Instruction prefetch requests" }, - {, + { "EventCode": "0xC898", "EventName": "PM_LS3_UNALIGNED_LD", "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty" }, - {, + { "EventCode": "0x488C", "EventName": "PM_IC_PREF_WRITE", "BriefDescription": "Instruction prefetch written into IL1" }, - {, + { |