summaryrefslogtreecommitdiffstats
path: root/sound
diff options
context:
space:
mode:
Diffstat (limited to 'sound')
-rw-r--r--sound/pci/lx6464es/lx_core.c84
1 files changed, 0 insertions, 84 deletions
diff --git a/sound/pci/lx6464es/lx_core.c b/sound/pci/lx6464es/lx_core.c
index 626ecad4dae7..df4044d4f43d 100644
--- a/sound/pci/lx6464es/lx_core.c
+++ b/sound/pci/lx6464es/lx_core.c
@@ -141,63 +141,6 @@ void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data)
iowrite32(data, address);
}
-u32 lx_plx_mbox_read(struct lx6464es *chip, int mbox_nr)
-{
- int index;
-
- switch (mbox_nr) {
- case 1:
- index = ePLX_MBOX1; break;
- case 2:
- index = ePLX_MBOX2; break;
- case 3:
- index = ePLX_MBOX3; break;
- case 4:
- index = ePLX_MBOX4; break;
- case 5:
- index = ePLX_MBOX5; break;
- case 6:
- index = ePLX_MBOX6; break;
- case 7:
- index = ePLX_MBOX7; break;
- case 0: /* reserved for HF flags */
- snd_BUG();
- default:
- return 0xdeadbeef;
- }
-
- return lx_plx_reg_read(chip, index);
-}
-
-int lx_plx_mbox_write(struct lx6464es *chip, int mbox_nr, u32 value)
-{
- int index = -1;
-
- switch (mbox_nr) {
- case 1:
- index = ePLX_MBOX1; break;
- case 3:
- index = ePLX_MBOX3; break;
- case 4:
- index = ePLX_MBOX4; break;
- case 5:
- index = ePLX_MBOX5; break;
- case 6:
- index = ePLX_MBOX6; break;
- case 7:
- index = ePLX_MBOX7; break;
- case 0: /* reserved for HF flags */
- case 2: /* reserved for Pipe States
- * the DSP keeps an image of it */
- snd_BUG();
- return -EBADRQC;
- }
-
- lx_plx_reg_write(chip, index, value);
- return 0;
-}
-
-
/* rmh */
#ifdef CONFIG_SND_DEBUG
@@ -491,33 +434,6 @@ int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data)
#define CSES_BROADCAST 0x0002
#define CSES_UPDATE_LDSV 0x0004
-int lx_dsp_es_check_pipeline(struct lx6464es *chip)
-{
- int i;
-
- for (i = 0; i != CSES_TIMEOUT; ++i) {
- /*
- * le bit CSES_UPDATE_LDSV est à 1 dés que le macprog
- * est pret. il re-passe à 0 lorsque le premier read a
- * été fait. pour l'instant on retire le test car ce bit
- * passe a 1 environ 200 à 400 ms aprés que le registre
- * confES à été écrit (kick du xilinx ES).
- *
- * On ne teste que le bit CE.
- * */
-
- u32 cses = lx_dsp_reg_read(chip, eReg_CSES);
-
- if ((cses & CSES_CE) == 0)
- return 0;
-
- udelay(1);
- }
-
- return -ETIMEDOUT;
-}
-
-
#define PIPE_INFO_TO_CMD(capture, pipe) \
((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)