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+/****************************************************************************/
+
+/*
+ * esssolo1.c -- ESS Technology Solo1 (ES1946) audio driver.
+ *
+ * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Module command line parameters:
+ * none so far
+ *
+ * Supported devices:
+ * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
+ * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
+ * /dev/midi simple MIDI UART interface, no ioctl
+ *
+ * Revision history
+ * 10.11.1998 0.1 Initial release (without any hardware)
+ * 22.03.1999 0.2 cinfo.blocks should be reset after GETxPTR ioctl.
+ * reported by Johan Maes <joma@telindus.be>
+ * return EAGAIN instead of EBUSY when O_NONBLOCK
+ * read/write cannot be executed
+ * 07.04.1999 0.3 implemented the following ioctl's: SOUND_PCM_READ_RATE,
+ * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
+ * Alpha fixes reported by Peter Jones <pjones@redhat.com>
+ * 15.06.1999 0.4 Fix bad allocation bug.
+ * Thanks to Deti Fliegl <fliegl@in.tum.de>
+ * 28.06.1999 0.5 Add pci_set_master
+ * 12.08.1999 0.6 Fix MIDI UART crashing the driver
+ * Changed mixer semantics from OSS documented
+ * behaviour to OSS "code behaviour".
+ * Recording might actually work now.
+ * The real DDMA controller address register is at PCI config
+ * 0x60, while the register at 0x18 is used as a placeholder
+ * register for BIOS address allocation. This register
+ * is supposed to be copied into 0x60, according
+ * to the Solo1 datasheet. When I do that, I can access
+ * the DDMA registers except the mask bit, which
+ * is stuck at 1. When I copy the contents of 0x18 +0x10
+ * to the DDMA base register, everything seems to work.
+ * The fun part is that the Windows Solo1 driver doesn't
+ * seem to do these tricks.
+ * Bugs remaining: plops and clicks when starting/stopping playback
+ * 31.08.1999 0.7 add spin_lock_init
+ * replaced current->state = x with set_current_state(x)
+ * 03.09.1999 0.8 change read semantics for MIDI to match
+ * OSS more closely; remove possible wakeup race
+ * 07.10.1999 0.9 Fix initialization; complain if sequencer writes time out
+ * Revised resource grabbing for the FM synthesizer
+ * 28.10.1999 0.10 More waitqueue races fixed
+ * 09.12.1999 0.11 Work around stupid Alpha port issue (virt_to_bus(kmalloc(GFP_DMA)) > 16M)
+ * Disabling recording on Alpha
+ * 12.01.2000 0.12 Prevent some ioctl's from returning bad count values on underrun/overrun;
+ * Tim Janik's BSE (Bedevilled Sound Engine) found this
+ * Integrated (aka redid 8-)) APM support patch by Zach Brown
+ * 07.02.2000 0.13 Use pci_alloc_consistent and pci_register_driver
+ * 19.02.2000 0.14 Use pci_dma_supported to determine if recording should be disabled
+ * 13.03.2000 0.15 Reintroduce initialization of a couple of PCI config space registers
+ * 21.11.2000 0.16 Initialize dma buffers in poll, otherwise poll may return a bogus mask
+ * 12.12.2000 0.17 More dma buffer initializations, patch from
+ * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
+ * 31.01.2001 0.18 Register/Unregister gameport, original patch from
+ * Nathaniel Daw <daw@cs.cmu.edu>
+ * Fix SETTRIGGER non OSS API conformity
+ * 10.03.2001 provide abs function, prevent picking up a bogus kernel macro
+ * for abs. Bug report by Andrew Morton <andrewm@uow.edu.au>
+ * 15.05.2001 pci_enable_device moved, return values in probe cleaned
+ * up. Marcus Meissner <mm@caldera.de>
+ * 22.05.2001 0.19 more cleanups, changed PM to PCI 2.4 style, got rid
+ * of global list of devices, using pci device data.
+ * Marcus Meissner <mm@caldera.de>
+ * 03.01.2003 0.20 open_mode fixes from Georg Acher <acher@in.tum.de>
+ */
+
+/*****************************************************************************/
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/sound.h>
+#include <linux/slab.h>
+#include <linux/soundcard.h>
+#include <linux/pci.h>
+#include <linux/bitops.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <linux/spinlock.h>
+#include <linux/smp_lock.h>
+#include <linux/gameport.h>
+#include <linux/wait.h>
+
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/uaccess.h>
+
+#include "dm.h"
+
+/* --------------------------------------------------------------------- */
+
+#undef OSS_DOCUMENTED_MIXER_SEMANTICS
+
+/* --------------------------------------------------------------------- */
+
+#ifndef PCI_VENDOR_ID_ESS
+#define PCI_VENDOR_ID_ESS 0x125d
+#endif
+#ifndef PCI_DEVICE_ID_ESS_SOLO1
+#define PCI_DEVICE_ID_ESS_SOLO1 0x1969
+#endif
+
+#define SOLO1_MAGIC ((PCI_VENDOR_ID_ESS<<16)|PCI_DEVICE_ID_ESS_SOLO1)
+
+#define DDMABASE_OFFSET 0 /* chip bug workaround kludge */
+#define DDMABASE_EXTENT 16
+
+#define IOBASE_EXTENT 16
+#define SBBASE_EXTENT 16
+#define VCBASE_EXTENT (DDMABASE_EXTENT+DDMABASE_OFFSET)
+#define MPUBASE_EXTENT 4
+#define GPBASE_EXTENT 4
+#define GAMEPORT_EXTENT 4
+
+#define FMSYNTH_EXTENT 4
+
+/* MIDI buffer sizes */
+
+#define MIDIINBUF 256
+#define MIDIOUTBUF 256
+
+#define FMODE_MIDI_SHIFT 3
+#define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
+#define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
+
+#define FMODE_DMFM 0x10
+
+static struct pci_driver solo1_driver;
+
+/* --------------------------------------------------------------------- */
+
+struct solo1_state {
+ /* magic */
+ unsigned int magic;
+
+ /* the corresponding pci_dev structure */
+ struct pci_dev *dev;
+
+ /* soundcore stuff */
+ int dev_audio;
+ int dev_mixer;
+ int dev_midi;
+ int dev_dmfm;
+
+ /* hardware resources */
+ unsigned long iobase, sbbase, vcbase, ddmabase, mpubase; /* long for SPARC */
+ unsigned int irq;
+
+ /* mixer registers */
+ struct {
+ unsigned short vol[10];
+ unsigned int recsrc;
+ unsigned int modcnt;
+ unsigned short micpreamp;
+ } mix;
+
+ /* wave stuff */
+ unsigned fmt;
+ unsigned channels;
+ unsigned rate;
+ unsigned char clkdiv;
+ unsigned ena;
+
+ spinlock_t lock;
+ struct semaphore open_sem;
+ mode_t open_mode;
+ wait_queue_head_t open_wait;
+
+ struct dmabuf {
+ void *rawbuf;
+ dma_addr_t dmaaddr;
+ unsigned buforder;
+ unsigned numfrag;
+ unsigned fragshift;
+ unsigned hwptr, swptr;
+ unsigned total_bytes;
+ int count;
+ unsigned error; /* over/underrun */
+ wait_queue_head_t wait;
+ /* redundant, but makes calculations easier */
+ unsigned fragsize;
+ unsigned dmasize;
+ unsigned fragsamples;
+ /* OSS stuff */
+ unsigned mapped:1;
+ unsigned ready:1;
+ unsigned endcleared:1;
+ unsigned enabled:1;
+ unsigned ossfragshift;
+ int ossmaxfrags;
+ unsigned subdivision;
+ } dma_dac, dma_adc;
+
+ /* midi stuff */
+ struct {
+ unsigned ird, iwr, icnt;
+ unsigned ord, owr, ocnt;
+ wait_queue_head_t iwait;
+ wait_queue_head_t owait;
+ struct timer_list timer;
+ unsigned char ibuf[MIDIINBUF];
+ unsigned char obuf[MIDIOUTBUF];
+ } midi;
+
+ struct gameport *gameport;
+};
+
+/* --------------------------------------------------------------------- */
+
+static inline void write_seq(struct solo1_state *s, unsigned char data)
+{
+ int i;
+ unsigned long flags;
+
+ /* the local_irq_save stunt is to send the data within the command window */
+ for (i = 0; i < 0xffff; i++) {
+ local_irq_save(flags);
+ if (!(inb(s->sbbase+0xc) & 0x80)) {
+ outb(data, s->sbbase+0xc);
+ local_irq_restore(flags);
+ return;
+ }
+ local_irq_restore(flags);
+ }
+ printk(KERN_ERR "esssolo1: write_seq timeout\n");
+ outb(data, s->sbbase+0xc);
+}
+
+static inline int read_seq(struct solo1_state *s, unsigned char *data)
+{
+ int i;
+
+ if (!data)
+ return 0;
+ for (i = 0; i < 0xffff; i++)
+ if (inb(s->sbbase+0xe) & 0x80) {
+ *data = inb(s->sbbase+0xa);
+ return 1;
+ }
+ printk(KERN_ERR "esssolo1: read_seq timeout\n");
+ return 0;
+}
+
+static inline int reset_ctrl(struct solo1_state *s)
+{
+ int i;
+
+ outb(3, s->sbbase+6); /* clear sequencer and FIFO */
+ udelay(10);
+ outb(0, s->sbbase+6);
+ for (i = 0; i < 0xffff; i++)
+ if (inb(s->sbbase+0xe) & 0x80)
+ if (inb(s->sbbase+0xa) == 0xaa) {
+ write_seq(s, 0xc6); /* enter enhanced mode */
+ return 1;
+ }
+ return 0;
+}
+
+static void write_ctrl(struct solo1_state *s, unsigned char reg, unsigned char data)
+{
+ write_seq(s, reg);
+ write_seq(s, data);
+}
+
+#if 0 /* unused */
+static unsigned char read_ctrl(struct solo1_state *s, unsigned char reg)
+{
+ unsigned char r;
+
+ write_seq(s, 0xc0);
+ write_seq(s, reg);
+ read_seq(s, &r);
+ return r;
+}
+#endif /* unused */
+
+static void write_mixer(struct solo1_state *s, unsigned char reg, unsigned char data)
+{
+ outb(reg, s->sbbase+4);
+ outb(data, s->sbbase+5);
+}
+
+static unsigned char read_mixer(struct solo1_state *s, unsigned char reg)
+{
+ outb(reg, s->sbbase+4);
+ return inb(s->sbbase+5);
+}
+
+/* --------------------------------------------------------------------- */
+
+static inline unsigned ld2(unsigned int x)
+{
+ unsigned r = 0;
+
+ if (x >= 0x10000) {
+ x >>= 16;
+ r += 16;
+ }
+ if (x >= 0x100) {
+ x >>= 8;
+ r += 8;
+ }
+ if (x >= 0x10) {
+ x >>= 4;
+ r += 4;
+ }
+ if (x >= 4) {
+ x >>= 2;
+ r += 2;
+ }
+ if (x >= 2)
+ r++;
+ return r;
+}
+
+/* --------------------------------------------------------------------- */
+
+static inline void stop_dac(struct solo1_state *s)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&s->lock, flags);
+ s->ena &= ~FMODE_WRITE;
+ write_mixer(s, 0x78, 0x10);
+ spin_unlock_irqrestore(&s->lock, flags);
+}
+
+static void start_dac(struct solo1_state *s)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&s->lock, flags);
+ if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
+ s->ena |= FMODE_WRITE;
+ write_mixer(s, 0x78, 0x12);
+ udelay(10);
+ write_mixer(s, 0x78, 0x13);
+ }
+ spin_unlock_irqrestore(&s->lock, flags);
+}
+
+static inline void stop_adc(struct solo1_state *s)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&s->lock, flags);
+ s->ena &= ~FMODE_READ;
+ write_ctrl(s, 0xb8, 0xe);
+ spin_unlock_irqrestore(&s->lock, flags);
+}
+
+static void start_adc(struct solo1_state *s)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&s->lock, flags);
+ if (!(s->ena & FMODE_READ) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
+ && s->dma_adc.ready) {
+ s->ena |= FMODE_READ;
+ write_ctrl(s, 0xb8, 0xf);
+#if 0
+ printk(KERN_DEBUG "solo1: DMAbuffer: 0x%08lx\n", (long)s->dma_adc.rawbuf);
+ printk(KERN_DEBUG "solo1: DMA: mask: 0x%02x cnt: 0x%04x addr: 0x%08x stat: 0x%02x\n",
+ inb(s->ddmabase+0xf), inw(s->ddmabase+4), inl(s->ddmabase), inb(s->ddmabase+8));
+#endif
+ outb(0, s->ddmabase+0xd); /* master reset */
+ outb(1, s->ddmabase+0xf); /* mask */
+ outb(0x54/*0x14*/, s->ddmabase+0xb); /* DMA_MODE_READ | DMA_MODE_AUTOINIT */
+ outl(virt_to_bus(s->dma_adc.rawbuf), s->ddmabase);
+ outw(s->dma_adc.dmasize-1, s->ddmabase+4);
+ outb(0, s->ddmabase+0xf);
+ }
+ spin_unlock_irqrestore(&s->lock, flags);
+#if 0
+ printk(KERN_DEBUG "solo1: start DMA: reg B8: 0x%02x SBstat: 0x%02x\n"
+ KERN_DEBUG "solo1: DMA: stat: 0x%02x cnt: 0x%04x mask: 0x%02x\n",
+ read_ctrl(s, 0xb8), inb(s->sbbase+0xc),
+ inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->ddmabase+0xf));
+ printk(KERN_DEBUG "solo1: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
+ KERN_DEBUG "solo1: B1: 0x%02x B2: 0x%02x B4: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n",
+ read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
+ read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb4), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8),
+ read_ctrl(s, 0xb9));
+#endif
+}
+
+/* --------------------------------------------------------------------- */
+
+#define DMABUF_DEFAULTORDER (15-PAGE_SHIFT)
+#define DMABUF_MINORDER 1
+
+static inline void dealloc_dmabuf(struct solo1_state *s, struct dmabuf *db)
+{
+ struct page *page, *pend;
+
+ if (db->rawbuf) {
+ /* undo marking the pages as reserved */
+ pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
+ for (page = virt_to_page(db->rawbuf); page <= pend; page++)
+ ClearPageReserved(page);
+ pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
+ }
+ db->rawbuf = NULL;
+ db->mapped = db->ready = 0;
+}
+
+static int prog_dmabuf(struct solo1_state *s, struct dmabuf *db)
+{
+ int order;
+ unsigned bytespersec;
+ unsigned bufs, sample_shift = 0;
+ struct page *page, *pend;
+
+ db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
+ if (!db->rawbuf) {
+ db->ready = db->mapped = 0;
+ for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
+ if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
+ break;
+ if (!db->rawbuf)
+ return -ENOMEM;
+ db->buforder = order;
+ /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
+ pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
+ for (page = virt_to_page(db->rawbuf); page <= pend; page++)
+ SetPageReserved(page);
+ }
+ if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
+ sample_shift++;
+ if (s->channels > 1)
+ sample_shift++;
+ bytespersec = s->rate << sample_shift;
+ bufs = PAGE_SIZE << db->buforder;
+ if (db->ossfragshift) {
+ if ((1000 << db->ossfragshift) < bytespersec)
+ db->fragshift = ld2(bytespersec/1000);
+ else
+ db->fragshift = db->ossfragshift;
+ } else {
+ db->fragshift = ld2(bytespersec/100/(db->subdivision ? db->subdivision : 1));
+ if (db->fragshift < 3)
+ db->fragshift = 3;
+ }
+ db->numfrag = bufs >> db->fragshift;
+ while (db->numfrag < 4 && db->fragshift > 3) {
+ db->fragshift--;
+ db->numfrag = bufs >> db->fragshift;
+ }
+ db->fragsize = 1 << db->fragshift;
+ if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
+ db->numfrag = db->ossmaxfrags;
+ db->fragsamples = db->fragsize >> sample_shift;
+ db->dmasize = db->numfrag << db->fragshift;
+ db->enabled = 1;
+ return 0;
+}
+
+static inline int prog_dmabuf_adc(struct solo1_state *s)
+{
+ unsigned long va;
+ int c;
+
+ stop_adc(s);
+ /* check if PCI implementation supports 24bit busmaster DMA */
+ if (s->dev->dma_mask > 0xffffff)
+ return -EIO;
+ if ((c = prog_dmabuf(s, &s->dma_adc)))
+ return c;
+ va = s->dma_adc.dmaaddr;
+ if ((va & ~((1<<24)-1)))
+ panic("solo1: buffer above 16M boundary");
+ outb(0, s->ddmabase+0xd); /* clear */
+ outb(1, s->ddmabase+0xf); /* mask */
+ /*outb(0, s->ddmabase+8);*/ /* enable (enable is active low!) */
+ outb(0x54, s->ddmabase+0xb); /* DMA_MODE_READ | DMA_MODE_AUTOINIT */
+ outl(va, s->ddmabase);
+ outw(s->dma_adc.dmasize-1, s->ddmabase+4);
+ c = - s->dma_adc.fragsamples;
+ write_ctrl(s, 0xa4, c);
+ write_ctrl(s, 0xa5, c >> 8);
+ outb(0, s->ddmabase+0xf);
+ s->dma_adc.ready = 1;
+ return 0;
+}
+
+static inline int prog_dmabuf_dac(struct solo1_state *s)
+{
+ unsigned long va;
+ int c;
+
+ stop_dac(s);
+ if ((c = prog_dmabuf(s, &s->dma_dac)))
+ return c;
+ memset(s->dma_dac.rawbuf, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0 : 0x80, s->dma_dac.dmasize); /* almost correct for U16 */
+ va = s->dma_dac.dmaaddr;
+ if ((va ^ (va + s->dma_dac.dmasize - 1)) & ~((1<<20)-1))
+ panic("solo1: buffer crosses 1M boundary");
+ outl(va, s->iobase);
+ /* warning: s->dma_dac.dmasize & 0xffff must not be zero! i.e. this limits us to a 32k buffer */
+ outw(s->dma_dac.dmasize, s->iobase+4);
+ c = - s->dma_dac.fragsamples;
+ write_mixer(s, 0x74, c);
+ write_mixer(s, 0x76, c >> 8);
+ outb(0xa, s->iobase+6);
+ s->dma_dac.ready = 1;
+ return 0;
+}
+
+static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
+{
+ if (bptr + len > bsize) {
+ unsigned x = bsize - bptr;
+ memset(((char *)buf) + bptr, c, x);
+ bptr = 0;
+ len -= x;
+ }
+ memset(((char *)buf) + bptr, c, len);
+}
+
+/* call with spinlock held! */
+
+static void solo1_update_ptr(struct solo1_state *s)
+{
+ int diff;
+ unsigned hwptr;
+
+ /* update ADC pointer */
+ if (s->ena & FMODE_READ) {
+ hwptr = (s->dma_adc.dmasize - 1 - inw(s->ddmabase+4)) % s->dma_adc.dmasize;
+ diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
+ s->dma_adc.hwptr = hwptr;
+ s->dma_adc.total_bytes += diff;
+ s->dma_adc.count += diff;
+#if 0
+ printk(KERN_DEBUG "solo1: rd: hwptr %u swptr %u dmasize %u count %u\n",
+ s->dma_adc.hwptr, s->dma_adc.swptr, s->dma_adc.dmasize, s->dma_adc.count);
+#endif
+ if (s->dma_adc.mapped) {
+ if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
+ wake_up(&s->dma_adc.wait);
+ } else {
+ if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
+ s->ena &= ~FMODE_READ;
+ write_ctrl(s, 0xb8, 0xe);
+ s->dma_adc.error++;
+ }
+ if (s->dma_adc.count > 0)
+ wake_up(&s->dma_adc.wait);
+ }
+ }
+ /* update DAC pointer */
+ if (s->ena & FMODE_WRITE) {
+ hwptr = (s->dma_dac.dmasize - inw(s->iobase+4)) % s->dma_dac.dmasize;
+ diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
+ s->dma_dac.hwptr = hwptr;
+ s->dma_dac.total_bytes += diff;
+#if 0
+ printk(KERN_DEBUG "solo1: wr: hwptr %u swptr %u dmasize %u count %u\n",
+ s->dma_dac.hwptr, s->dma_dac.swptr, s->dma_dac.dmasize, s->dma_dac.count);
+#endif
+ if (s->dma_dac.mapped) {
+ s->dma_dac.count += diff;
+ if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
+ wake_up(&s->dma_dac.wait);
+ } else {
+ s->dma_dac.count -= diff;
+ if (s->dma_dac.count <= 0) {
+ s->ena &= ~FMODE_WRITE;
+ write_mixer(s, 0x78, 0x12);
+ s->dma_dac.error++;
+ } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
+ clear_advance(s->dma_dac.rawbuf, s->dma_dac.dmasize, s->dma_dac.swptr,
+ s->dma_dac.fragsize, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0 : 0x80);
+ s->dma_dac.endcleared = 1;
+ }
+ if (s->dma_dac.count < (signed)s->dma_dac.dmasize)
+ wake_up(&s->dma_dac.wait);
+ }
+ }
+}
+
+/* --------------------------------------------------------------------- */
+
+static void prog_codec(struct solo1_state *s)
+{
+ unsigned long flags;
+ int fdiv, filter;
+ unsigned char c;
+
+ reset_ctrl(s);
+ write_seq(s, 0xd3);
+ /* program sampling rates */
+ filter = s->rate * 9 / 20; /* Set filter roll-off to 90% of rate/2 */
+ fdiv = 256 - 7160000 / (filter * 82);
+ spin_lock_irqsave(&s->lock, flags);
+ write_ctrl(s, 0xa1, s->clkdiv);
+ write_ctrl(s, 0xa2, fdiv);
+ write_mixer(s, 0x70, s->clkdiv);
+ write_mixer(s, 0x72, fdiv);
+ /* program ADC parameters */
+ write_ctrl(s, 0xb8, 0xe);
+ write_ctrl(s, 0xb9, /*0x1*/0);
+ write_ctrl(s, 0xa8, (s->channels > 1) ? 0x11 : 0x12);
+ c = 0xd0;
+ if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
+ c |= 0x04;
+ if (s->fmt & (AFMT_S16_LE | AFMT_S8))
+ c |= 0x20;
+ if (s->channels > 1)
+ c ^= 0x48;
+ write_ctrl(s, 0xb7, (c & 0x70) | 1);
+ write_ctrl(s, 0xb7, c);
+ write_ctrl(s, 0xb1, 0x50);
+ write_ctrl(s, 0xb2, 0x50);
+ /* program DAC parameters */
+ c = 0x40;
+ if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
+ c |= 1;
+ if (s->fmt & (AFMT_S16_LE | AFMT_S8))
+ c |= 4;
+ if (s->channels > 1)
+ c |= 2;
+ write_mixer(s, 0x7a, c);
+ write_mixer(s, 0x78, 0x10);
+ s->ena = 0;
+ spin_unlock_irqrestore(&s->lock, flags);
+}
+
+/* --------------------------------------------------------------------- */
+
+static const char invalid_magic[] = KERN_CRIT "solo1: invalid magic value\n";
+
+#define VALIDATE_STATE(s) \
+({ \
+ if (!(s) || (s)->magic != SOLO1_MAGIC) { \
+ printk(invalid_magic); \
+ return -ENXIO; \
+ } \
+})
+
+/* --------------------------------------------------------------------- */
+
+static int mixer_ioctl(struct solo1_state *s, unsigned int cmd, unsigned long arg)
+{
+ static const unsigned int mixer_src[8] = {
+ SOUND_MASK_MIC, SOUND_MASK_MIC, SOUND_MASK_CD, SOUND_MASK_VOLUME,
+ SOUND_MASK_MIC, 0, SOUND_MASK_LINE, 0
+ };
+ static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
+ [SOUND_MIXER_PCM] = 1, /* voice */
+ [SOUND_MIXER_SYNTH] = 2, /* FM */
+ [SOUND_MIXER_CD] = 3, /* CD */
+ [SOUND_MIXER_LINE] = 4, /* Line */
+ [SOUND_MIXER_LINE1] = 5, /* AUX */
+ [SOUND_MIXER_MIC] = 6, /* Mic */
+ [SOUND_MIXER_LINE2] = 7, /* Mono in */
+ [SOUND_MIXER_SPEAKER] = 8, /* Speaker */
+ [SOUND_MIXER_RECLEV] = 9, /* Recording level */
+ [SOUND_MIXER_VOLUME] = 10 /* Master Volume */
+ };
+ static const unsigned char mixreg[] = {
+ 0x7c, /* voice */
+ 0x36, /* FM */
+ 0x38, /* CD */
+ 0x3e, /* Line */
+ 0x3a, /* AUX */
+ 0x1a, /* Mic */
+ 0x6d /* Mono in */
+ };
+ unsigned char l, r, rl, rr, vidx;
+ int i, val;
+ int __user *p = (int __user *)arg;
+
+ VALIDATE_STATE(s);
+
+ if (cmd == SOUND_MIXER_PRIVATE1) {
+ /* enable/disable/query mixer preamp */
+ if (get_user(val, p))
+ return -EFAULT;
+ if (val != -1) {
+ val = val ? 0xff : 0xf7;
+ write_mixer(s, 0x7d, (read_mixer(s, 0x7d) | 0x08) & val);
+ }
+ val = (read_mixer(s, 0x7d) & 0x08) ? 1 : 0;
+ return put_user(val, p);
+ }
+ if (cmd == SOUND_MIXER_PRIVATE2) {
+ /* enable/disable/query spatializer */
+ if (get_user(val, p))
+ return -EFAULT;
+ if (val != -1) {
+ val &= 0x3f;
+ write_mixer(s, 0x52, val);
+ write_mixer(s, 0x50, val ? 0x08 : 0);
+ }
+ return put_user(read_mixer(s, 0x52), p);
+ }
+ if (cmd == SOUND_MIXER_INFO) {
+ mixer_info info;
+ strncpy(info.id, "Solo1", sizeof(info.id));
+ strncpy(info.name, "ESS Solo1", sizeof(info.name));
+ info.modify_counter = s->mix.modcnt;
+ if (copy_to_user((void __user *)arg, &info, sizeof(info)))
+ return -EFAULT;
+ return 0;
+ }
+ if (cmd == SOUND_OLD_MIXER_INFO) {
+ _old_mixer_info info;
+ strncpy(info.id, "Solo1", sizeof(info.id));
+ strncpy(info.name, "ESS Solo1", sizeof(info.name));
+ if (copy_to_user((void __user *)arg, &info, sizeof(info)))
+ return -EFAULT;
+ return 0;
+ }
+ if (cmd == OSS_GETVERSION)
+ return put_user(SOUND_VERSION, p);
+ if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
+ return -EINVAL;
+ if (_SIOC_DIR(cmd) == _SIOC_READ) {
+ switch (_IOC_NR(cmd)) {
+ case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
+ return put_user(mixer_src[read_mixer(s, 0x1c) & 7], p);
+
+ case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
+ return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
+ SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
+ SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV |
+ SOUND_MASK_SPEAKER, p);
+
+ case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
+ return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_VOLUME, p);
+
+ case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
+ return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
+ SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
+ SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV, p);
+
+ case SOUND_MIXER_CAPS:
+ return put_user(SOUND_CAP_EXCL_INPUT, p);
+
+ default:
+ i = _IOC_NR(cmd);
+ if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
+ return -EINVAL;
+ return put_user(s->mix.vol[vidx-1], p);
+ }
+ }
+ if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
+ return -EINVAL;
+ s->mix.modcnt++;
+ switch (_IOC_NR(cmd)) {
+ case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
+#if 0
+ {
+ static const unsigned char regs[] = {
+ 0x1c, 0x1a, 0x36, 0x38, 0x3a, 0x3c, 0x3e, 0x60, 0x62, 0x6d, 0x7c
+ };
+ int i;
+
+ for (i = 0; i < sizeof(regs); i++)
+ printk(KERN_DEBUG "solo1: mixer reg 0x%02x: 0x%02x\n",
+ regs[i], read_mixer(s, regs[i]));
+ printk(KERN_DEBUG "solo1: ctrl reg 0x%02x: 0x%02x\n",
+ 0xb4, read_ctrl(s, 0xb4));
+ }
+#endif
+ if (get_user(val, p))
+ return -EFAULT;
+ i = hweight32(val);
+ if (i == 0)
+ return 0;
+ else if (i > 1)
+ val &= ~mixer_src[read_mixer(s, 0x1c) & 7];
+ for (i = 0; i < 8; i++) {
+ if (mixer_src[i] & val)
+ break;
+ }
+ if (i > 7)
+ return 0;
+ write_mixer(s, 0x1c, i);
+ return 0;
+
+ case SOUND_MIXER_VOLUME:
+ if (get_user(val, p))
+ return -EFAULT;
+ l = val & 0xff;
+ if (l > 100)
+ l = 100;
+ r = (val >> 8) & 0xff;
+ if (r > 100)
+ r = 100;
+ if (l < 6) {
+ rl = 0x40;
+ l = 0;
+ } else {
+ rl = (l * 2 - 11) / 3;
+ l = (rl * 3 + 11) / 2;
+ }
+ if (r < 6) {
+ rr = 0x40;
+ r = 0;
+ } else {
+ rr = (r * 2 - 11) / 3;
+ r = (rr * 3 + 11) / 2;
+ }
+ write_mixer(s, 0x60, rl);
+ write_mixer(s, 0x62, rr);
+#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
+ s->mix.vol[9] = ((unsigned int)r << 8) | l;
+#else
+ s->mix.vol[9] = val;
+#endif
+ return put_user(s->mix.vol[9], p);
+
+ case SOUND_MIXER_SPEAKER:
+ if (get_user(val, p))
+ return -EFAULT;
+ l = val & 0xff;
+ if (l > 100)
+ l = 100;
+ else if (l < 2)
+ l = 2;
+ rl = (l - 2) / 14;
+ l = rl * 14 + 2;
+ write_mixer(s, 0x3c, rl);
+#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
+ s->mix.vol[7] = l * 0x101;
+#else
+ s->mix.vol[7] = val;
+#endif
+ return put_user(s->mix.vol[7], p);
+
+ case SOUND_MIXER_RECLEV:
+ if (get_user(val, p))
+ return -EFAULT;
+ l = (val << 1) & 0x1fe;
+ if (l > 200)
+ l = 200;
+ else if (l < 5)
+ l = 5;
+ r = (val >> 7) & 0x1fe;
+ if (r > 200)
+ r = 200;
+ else if (r < 5)
+ r = 5;
+ rl = (l - 5) / 13;
+ rr = (r - 5) / 13;
+ r = (rl * 13 + 5) / 2;
+ l = (rr * 13 + 5) / 2;
+ write_ctrl(s, 0xb4, (rl << 4) | rr);
+#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
+ s->mix.vol[8] = ((unsigned int)r << 8) | l;
+#else
+ s->mix.vol[8] = val;
+#endif
+ return put_user(s->mix.vol[8], p);
+
+ default:
+ i = _IOC_NR(cmd);
+ if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
+ return -EINVAL;
+ if (get_user(val, p))
+ return -EFAULT;
+ l = (val << 1) & 0x1fe;
+ if (l > 200)
+ l = 200;
+ else if (l < 5)
+ l = 5;
+ r = (val >> 7) & 0x1fe;
+ if (r > 200)
+ r = 200;
+ else if (r < 5)
+ r = 5;
+ rl = (l - 5) / 13;
+ rr = (r - 5) / 13;
+ r = (rl * 13 + 5) / 2;
+ l = (rr * 13 + 5) / 2;
+ write_mixer(s, mixreg[vidx-1], (rl << 4) | rr);
+#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
+ s->mix.vol[vidx-1] = ((unsigned int)r << 8) | l;
+#else
+ s->mix.vol[vidx-1] = val;
+#endif
+ return put_user(s->mix.vol[vidx-1], p);
+ }
+}
+
+/* --------------------------------------------------------------------- */
+
+static int solo1_open_mixdev(struct inode *inode, struct file *file)
+{
+ unsigned int minor = iminor(inode);
+ struct solo1_state *s = NULL;
+ struct pci_dev *pci_dev = NULL;
+
+ while ((pci_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL) {
+ struct pci_driver *drvr;
+ drvr = pci_dev_driver (pci_dev);
+ if (drvr != &solo1_driver)
+ continue;
+ s = (struct solo1_state*)pci_get_drvdata(pci_dev);
+ if (!s)
+ continue;
+ if (s->dev_mixer == minor)
+ break;
+ }
+ if (!s)
+ return -ENODEV;
+ VALIDATE_STATE(s);
+ file->private_data = s;
+ return nonseekable_open(inode, file);
+}
+
+static int solo1_release_mixdev(struct inode *inode, struct file *file)
+{
+ struct solo1_state *s = (struct solo1_state *)file->private_data;
+
+ VALIDATE_STATE(s);
+ return 0;
+}
+
+static int solo1_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+ return mixer_ioctl((struct solo1_state *)file->private_data, cmd, arg);
+}
+
+static /*const*/ struct file_operations solo1_mixer_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .ioctl = solo1_ioctl_mixdev,
+ .open = solo1_open_mixdev,
+ .release = solo1_release_mixdev,
+};
+
+/* --------------------------------------------------------------------- */
+
+static int drain_dac(struct solo1_state *s, int nonblock)
+{
+ DECLARE_WAITQUEUE(wait, current);
+ unsigned long flags;
+ int count;
+ unsigned tmo;
+
+ if (s->dma_dac.mapped)
+ return 0;
+ add_wait_queue(&s->dma_dac.wait, &wait);
+ for (;;) {
+ set_current_state(TASK_INTERRUPTIBLE);
+ spin_lock_irqsave(&s->lock, flags);
+ count = s->dma_dac.count;
+ spin_unlock_irqrestore(&s->lock, flags);
+ if (count <= 0)
+ break;
+ if (signal_pending(current))
+ break;
+ if (nonblock) {
+ remove_wait_queue(&s->dma_dac.wait, &wait);
+ set_current_state(TASK_RUNNING);
+ return -EBUSY;
+ }
+ tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->rate;
+ if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
+ tmo >>= 1;
+ if (s->channels > 1)
+ tmo >>= 1;
+ if (!schedule_timeout(tmo + 1))
+ printk(KERN_DEBUG "solo1: dma timed out??\n");
+ }
+ remove_wait_queue(&s->dma_dac.wait, &wait);
+ set_current_state(TASK_RUNNING);
+ if (signal_pending(current))
+ return -ERESTARTSYS;
+ return 0;
+}
+
+/* --------------------------------------------------------------------- */
+
+static ssize_t solo1_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
+{
+ struct solo1_state *s = (struct solo1_state *)file->private_data;
+ DECLARE_WAITQUEUE(wait, current);
+ ssize_t ret;
+ unsigned long flags;
+ unsigned swptr;
+ int cnt;
+
+ VALIDATE_STATE(s);
+ if (s->dma_adc.mapped)
+ return -ENXIO;
+ if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
+ return ret;
+ if (!access_ok(VERIFY_WRITE, buffer, count))
+ return -EFAULT;
+ ret = 0;
+ add_wait_queue(&s->dma_adc.wait, &wait);
+ while (count > 0) {
+ spin_lock_irqsave(&s->lock, flags);
+ swptr = s->dma_adc.swptr;
+ cnt = s->dma_adc.dmasize-swptr;
+ if (s->dma_adc.count < cnt)
+ cnt = s->dma_adc.count;
+ if (cnt <= 0)
+ __set_current_state(TASK_INTERRUPTIBLE);
+ spin_unlock_irqrestore(&s->lock, flags);
+ if (cnt > count)
+ cnt = count;
+#ifdef DEBUGREC
+ printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x cnt: %u\n",
+ read_ctrl(s, 0xb8), inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->sbbase+0xc), cnt);
+#endif
+ if (cnt <= 0) {
+ if (s->dma_adc.enabled)
+ start_adc(s);
+#ifdef DEBUGREC
+ printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
+ KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
+ KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
+ KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
+ read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
+ read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8), read_ctrl(s, 0xb9),
+ inl(s->ddmabase), inw(s->ddmabase+4), inb(s->ddmabase+8), inb(s->ddmabase+15), inb(s->sbbase+0xc), cnt);
+#endif
+ if (inb(s->ddmabase+15) & 1)
+ printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
+ if (file->f_flags & O_NONBLOCK) {
+ if (!ret)
+ ret = -EAGAIN;
+ break;
+ }
+ schedule();
+#ifdef DEBUGREC
+ printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
+ KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
+ KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
+ KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
+ read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
+ read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8), read_ctrl(s, 0xb9),
+ inl(s->ddmabase), inw(s->ddmabase+4), inb(s->ddmabase+8), inb(s->ddmabase+15), inb(s->sbbase+0xc), cnt);
+#endif
+ if (signal_pending(current)) {
+ if (!ret)
+ ret = -ERESTARTSYS;
+ break;