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-rw-r--r--drivers/staging/sb105x/Kconfig9
-rw-r--r--drivers/staging/sb105x/Makefile3
-rw-r--r--drivers/staging/sb105x/sb_mp_register.h295
-rw-r--r--drivers/staging/sb105x/sb_pci_mp.c3196
-rw-r--r--drivers/staging/sb105x/sb_pci_mp.h293
-rw-r--r--drivers/staging/sb105x/sb_ser_core.h368
6 files changed, 4164 insertions, 0 deletions
diff --git a/drivers/staging/sb105x/Kconfig b/drivers/staging/sb105x/Kconfig
new file mode 100644
index 000000000000..ac87c5e38dee
--- /dev/null
+++ b/drivers/staging/sb105x/Kconfig
@@ -0,0 +1,9 @@
+config SB105X
+ tristate "SystemBase PCI Multiport UART"
+ select SERIAL_CORE
+ depends on PCI
+ help
+ A driver for the SystemBase Multi-2/PCI serial card
+
+ To compile this driver a module, choose M here: the module
+ will be called "sb105x".
diff --git a/drivers/staging/sb105x/Makefile b/drivers/staging/sb105x/Makefile
new file mode 100644
index 000000000000..b1bf3779acae
--- /dev/null
+++ b/drivers/staging/sb105x/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_SB105X) += sb105x.o
+
+sb105x-y := sb_pci_mp.o
diff --git a/drivers/staging/sb105x/sb_mp_register.h b/drivers/staging/sb105x/sb_mp_register.h
new file mode 100644
index 000000000000..5480ae11368f
--- /dev/null
+++ b/drivers/staging/sb105x/sb_mp_register.h
@@ -0,0 +1,295 @@
+
+/*
+ * SB105X_UART.h
+ *
+ * Copyright (C) 2008 systembase
+ *
+ * UART registers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef UART_SB105X_H
+#define UART_SB105X_H
+
+/*
+ * option register
+ */
+
+/* Device Infomation Register */
+#define MP_OPTR_DIR0 0x04 /* port0 ~ port8 */
+#define MP_OPTR_DIR1 0x05 /* port8 ~ port15 */
+#define MP_OPTR_DIR2 0x06 /* port16 ~ port23 */
+#define MP_OPTR_DIR3 0x07 /* port24 ~ port31 */
+
+#define DIR_UART_16C550 0
+#define DIR_UART_16C1050 1
+#define DIR_UART_16C1050A 2
+
+#define DIR_CLK_1843200 0x0 /* input clock 1843200 Hz */
+#define DIR_CLK_3686400 0x1 /* input clock 3686400 Hz */
+#define DIR_CLK_7372800 0x2 /* input clock 7372800 Hz */
+#define DIR_CLK_14745600 0x3 /* input clock 14745600 Hz */
+#define DIR_CLK_29491200 0x4 /* input clock 29491200 Hz */
+#define DIR_CLK_58985400 0x5 /* input clock 58985400 Hz */
+
+/* Interface Information Register */
+#define MP_OPTR_IIR0 0x08 /* port0 ~ port8 */
+#define MP_OPTR_IIR1 0x09 /* port8 ~ port15 */
+#define MP_OPTR_IIR2 0x0A /* port16 ~ port23 */
+#define MP_OPTR_IIR3 0x0B /* port24 ~ port31 */
+
+#define IIR_RS232 0x00 /* RS232 type */
+#define IIR_RS422 0x10 /* RS422 type */
+#define IIR_RS485 0x20 /* RS485 type */
+#define IIR_UNKNOWN 0x30 /* unknown type */
+
+/* Interrrupt Mask Register */
+#define MP_OPTR_IMR0 0x0C /* port0 ~ port8 */
+#define MP_OPTR_IMR1 0x0D /* port8 ~ port15 */
+#define MP_OPTR_IMR2 0x0E /* port16 ~ port23 */
+#define MP_OPTR_IMR3 0x0F /* port24 ~ port31 */
+
+/* Interrupt Poll Register */
+#define MP_OPTR_IPR0 0x10 /* port0 ~ port8 */
+#define MP_OPTR_IPR1 0x11 /* port8 ~ port15 */
+#define MP_OPTR_IPR2 0x12 /* port16 ~ port23 */
+#define MP_OPTR_IPR3 0x13 /* port24 ~ port31 */
+
+/* General Purpose Output Control Register */
+#define MP_OPTR_GPOCR 0x20
+
+/* General Purpose Output Data Register */
+#define MP_OPTR_GPODR 0x21
+
+/* Parallel Additional Function Register */
+#define MP_OPTR_PAFR 0x23
+
+/*
+ * systembase 16c105x UART register
+ */
+
+#define PAGE_0 0
+#define PAGE_1 1
+#define PAGE_2 2
+#define PAGE_3 3
+#define PAGE_4 4
+
+/*
+ * ******************************************************************
+ * * DLAB=0 =============== Page 0 Registers *
+ * ******************************************************************
+ */
+
+#define SB105X_RX 0 /* In: Receive buffer */
+#define SB105X_TX 0 /* Out: Transmit buffer */
+
+#define SB105X_IER 1 /* Out: Interrupt Enable Register */
+
+#define SB105X_IER_CTSI 0x80 /* CTS# Interrupt Enable (Requires EFR[4] = 1) */
+#define SB105X_IER_RTSI 0x40 /* RTS# Interrupt Enable (Requires EFR[4] = 1) */
+#define SB105X_IER_XOI 0x20 /* Xoff Interrupt Enable (Requires EFR[4] = 1) */
+#define SB105X_IER_SME 0x10 /* Sleep Mode Enable (Requires EFR[4] = 1) */
+#define SB105X_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define SB105X_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define SB105X_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define SB105X_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+#define SB105X_ISR 2 /* In: Interrupt ID Register */
+
+#define SB105X_ISR_NOINT 0x01 /* No interrupts pending */
+#define SB105X_ISR_RLSI 0x06 /* Receiver line status interrupt (Priority = 1)*/
+#define SB105X_ISR_RDAI 0x0c /* Receive Data Available interrupt */
+#define SB105X_ISR_CTII 0x04 /* Character Timeout Indication interrupt */
+#define SB105X_ISR_THRI 0x02 /* Transmitter holding register empty */
+#define SB105X_ISR_MSI 0x00 /* Modem status interrupt */
+#define SB105X_ISR_RXCI 0x10 /* Receive Xoff or Special Character interrupt */
+#define SB105X_ISR_RCSI 0x20 /* RTS#, CTS# status interrupt during Auto RTS/CTS flow control */
+
+#define SB105X_FCR 2 /* Out: FIFO Control Register */
+
+#define SB105X_FCR_FEN 0x01 /* FIFO Enable */
+#define SB105X_FCR_RXFR 0x02 /* RX FIFO Reset */
+#define SB105X_FCR_TXFR 0x04 /* TX FIFO Reset */
+#define SB105X_FCR_DMS 0x08 /* DMA Mode Select */
+
+#define SB105X_FCR_RTR08 0x00 /* Receice Trigger Level set at 8 */
+#define SB105X_FCR_RTR16 0x40 /* Receice Trigger Level set at 16 */
+#define SB105X_FCR_RTR56 0x80 /* Receice Trigger Level set at 56 */
+#define SB105X_FCR_RTR60 0xc0 /* Receice Trigger Level set at 60 */
+#define SB105X_FCR_TTR08 0x00 /* Transmit Trigger Level set at 8 */
+#define SB105X_FCR_TTR16 0x10 /* Transmit Trigger Level set at 16 */
+#define SB105X_FCR_TTR32 0x20 /* Transmit Trigger Level set at 32 */
+#define SB105X_FCR_TTR56 0x30 /* Transmit Trigger Level set at 56 */
+
+#define SB105X_LCR 3 /* Out: Line Control Register */
+/*
+ * * Note: if the word length is 5 bits (SB105X_LCR_WLEN5), then setting
+ * * SB105X_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define SB105X_LCR_DLAB 0x80 /* Divisor Latch Enable */
+#define SB105X_LCR_SBC 0x40 /* Break Enable*/
+#define SB105X_LCR_SPAR 0x20 /* Set Stick parity */
+#define SB105X_LCR_EPAR 0x10 /* Even parity select */
+#define SB105X_LCR_PAREN 0x08 /* Parity Enable */
+#define SB105X_LCR_STOP 0x04 /* Stop bits: 0->1 bit, 1->2 bits, 1 and SB105X_LCR_WLEN5 -> 1.5 bit */
+#define SB105X_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
+#define SB105X_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
+#define SB105X_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
+#define SB105X_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
+
+#define SB105X_LCR_BF 0xBF
+
+#define SB105X_MCR 4 /* Out: Modem Control Register */
+#define SB105X_MCR_CPS 0x80 /* Clock Prescaler Select */
+#define SB105X_MCR_P2S 0x40 /* Page 2 Select /Xoff Re-Transmit Access Enable */
+#define SB105X_MCR_XOA 0x20 /* Xon Any Enable */
+#define SB105X_MCR_ILB 0x10 /* Internal Loopback Enable */
+#define SB105X_MCR_OUT2 0x08 /* Out2/Interrupt Output Enable*/
+#define SB105X_MCR_OUT1 0x04 /* Out1/Interrupt Output Enable */
+#define SB105X_MCR_RTS 0x02 /* RTS# Output */
+#define SB105X_MCR_DTR 0x01 /* DTR# Output */
+
+#define SB105X_LSR 5 /* In: Line Status Register */
+#define SB105X_LSR_RFEI 0x80 /* Receive FIFO data error Indicator */
+#define SB105X_LSR_TEMI 0x40 /* THR and TSR Empty Indicator */
+#define SB105X_LSR_THRE 0x20 /* THR Empty Indicator */
+#define SB105X_LSR_BII 0x10 /* Break interrupt indicator */
+#define SB105X_LSR_FEI 0x08 /* Frame error indicator */
+#define SB105X_LSR_PEI 0x04 /* Parity error indicator */
+#define SB105X_LSR_OEI 0x02 /* Overrun error indicator */
+#define SB105X_LSR_RDRI 0x01 /* Receive data ready Indicator*/
+
+#define SB105X_MSR 6 /* In: Modem Status Register */
+#define SB105X_MSR_DCD 0x80 /* Data Carrier Detect */
+#define SB105X_MSR_RI 0x40 /* Ring Indicator */
+#define SB105X_MSR_DSR 0x20 /* Data Set Ready */
+#define SB105X_MSR_CTS 0x10 /* Clear to Send */
+#define SB105X_MSR_DDCD 0x08 /* Delta DCD */
+#define SB105X_MSR_DRI 0x04 /* Delta ring indicator */
+#define SB105X_MSR_DDSR 0x02 /* Delta DSR */
+#define SB105X_MSR_DCTS 0x01 /* Delta CTS */
+
+#define SB105XA_MDR 6 /* Out: Multi Drop mode Register */
+#define SB105XA_MDR_NPS 0x08 /* 9th Bit Polarity Select */
+#define SB105XA_MDR_AME 0x02 /* Auto Multi-drop Enable */
+#define SB105XA_MDR_MDE 0x01 /* Multi Drop Enable */
+
+#define SB105X_SPR 7 /* I/O: Scratch Register */
+
+/*
+ * DLAB=1
+ */
+#define SB105X_DLL 0 /* Out: Divisor Latch Low */
+#define SB105X_DLM 1 /* Out: Divisor Latch High */
+
+/*
+ * ******************************************************************
+ * * DLAB(LCR[7]) = 0 , MCR[6] = 1 ============= Page 2 Registers *
+ * ******************************************************************
+ */
+#define SB105X_GICR 1 /* Global Interrupt Control Register */
+#define SB105X_GICR_GIM 0x01 /* Global Interrupt Mask */
+
+#define SB105X_GISR 2 /* Global Interrupt Status Register */
+#define SB105X_GISR_MGICR0 0x80 /* Mirror the content of GICR[0] */
+#define SB105X_GISR_CS3IS 0x08 /* SB105X of CS3# Interrupt Status */
+#define SB105X_GISR_CS2IS 0x04 /* SB105X of CS2# Interrupt Status */
+#define SB105X_GISR_CS1IS 0x02 /* SB105X of CS1# Interrupt Status */
+#define SB105X_GISR_CS0IS 0x01 /* SB105X of CS0# Interrupt Status */
+
+#define SB105X_TFCR 5 /* Transmit FIFO Count Register */
+
+#define SB105X_RFCR 6 /* Receive FIFO Count Register */
+
+#define SB105X_FSR 7 /* Flow Control Status Register */
+#define SB105X_FSR_THFS 0x20 /* Transmit Hardware Flow Control Status */
+#define SB105X_FSR_TSFS 0x10 /* Transmit Software Flow Control Status */
+#define SB105X_FSR_RHFS 0x02 /* Receive Hardware Flow Control Status */
+#define SB105X_FSR_RSFS 0x01 /* Receive Software Flow Control Status */
+
+/*
+ * ******************************************************************
+ * * LCR = 0xBF, PSR[0] = 0 ============= Page 3 Registers *
+ * ******************************************************************
+ */
+
+#define SB105X_PSR 0 /* Page Select Register */
+#define SB105X_PSR_P3KEY 0xA4 /* Page 3 Select Key */
+#define SB105X_PSR_P4KEY 0xA5 /* Page 5 Select Key */
+
+#define SB105X_ATR 1 /* Auto Toggle Control Register */
+#define SB105X_ATR_RPS 0x80 /* RXEN Polarity Select */
+#define SB105X_ATR_RCMS 0x40 /* RXEN Control Mode Select */
+#define SB105X_ATR_TPS 0x20 /* TXEN Polarity Select */
+#define SB105X_ATR_TCMS 0x10 /* TXEN Control Mode Select */
+#define SB105X_ATR_ATDIS 0x00 /* Auto Toggle is disabled */
+#define SB105X_ATR_ART 0x01 /* RTS#/TXEN pin operates as TXEN */
+#define SB105X_ATR_ADT 0x02 /* DTR#/TXEN pin operates as TXEN */
+#define SB105X_ATR_A80 0x03 /* only in 80 pin use */
+
+#define SB105X_EFR 2 /* (Auto) Enhanced Feature Register */
+#define SB105X_EFR_ACTS 0x80 /* Auto-CTS Flow Control Enable */
+#define SB105X_EFR_ARTS 0x40 /* Auto-RTS Flow Control Enable */
+#define SB105X_EFR_SCD 0x20 /* Special Character Detect */
+#define SB105X_EFR_EFBEN 0x10 /* Enhanced Function Bits Enable */
+
+#define SB105X_XON1 4 /* Xon1 Character Register */
+#define SB105X_XON2 5 /* Xon2 Character Register */
+#define SB105X_XOFF1 6 /* Xoff1 Character Register */
+#define SB105X_XOFF2 7 /* Xoff2 Character Register */
+
+/*
+ * ******************************************************************
+ * * LCR = 0xBF, PSR[0] = 1 ============ Page 4 Registers *
+ * ******************************************************************
+ */
+
+#define SB105X_AFR 1 /* Additional Feature Register */
+#define SB105X_AFR_GIPS 0x20 /* Global Interrupt Polarity Select */
+#define SB105X_AFR_GIEN 0x10 /* Global Interrupt Enable */
+#define SB105X_AFR_AFEN 0x01 /* 256-byte FIFO Enable */
+
+#define SB105X_XRCR 2 /* Xoff Re-transmit Count Register */
+#define SB105X_XRCR_NRC1 0x00 /* Transmits Xoff Character whenever the number of received data is 1 during XOFF status */
+#define SB105X_XRCR_NRC4 0x01 /* Transmits Xoff Character whenever the number of received data is 4 during XOFF status */
+#define SB105X_XRCR_NRC8 0x02 /* Transmits Xoff Character whenever the number of received data is 8 during XOFF status */
+#define SB105X_XRCR_NRC16 0x03 /* Transmits Xoff Character whenever the number of received data is 16 during XOFF status */
+
+#define SB105X_TTR 4 /* Transmit FIFO Trigger Level Register */
+#define SB105X_RTR 5 /* Receive FIFO Trigger Level Register */
+#define SB105X_FUR 6 /* Flow Control Upper Threshold Register */
+#define SB105X_FLR 7 /* Flow Control Lower Threshold Register */
+
+
+/* page 0 */
+
+#define SB105X_GET_CHAR(port) inb((port)->iobase + SB105X_RX)
+#define SB105X_GET_IER(port) inb((port)->iobase + SB105X_IER)
+#define SB105X_GET_ISR(port) inb((port)->iobase + SB105X_ISR)
+#define SB105X_GET_LCR(port) inb((port)->iobase + SB105X_LCR)
+#define SB105X_GET_MCR(port) inb((port)->iobase + SB105X_MCR)
+#define SB105X_GET_LSR(port) inb((port)->iobase + SB105X_LSR)
+#define SB105X_GET_MSR(port) inb((port)->iobase + SB105X_MSR)
+#define SB105X_GET_SPR(port) inb((port)->iobase + SB105X_SPR)
+
+#define SB105X_PUT_CHAR(port,v) outb((v),(port)->iobase + SB105X_TX )
+#define SB105X_PUT_IER(port,v) outb((v),(port)->iobase + SB105X_IER )
+#define SB105X_PUT_FCR(port,v) outb((v),(port)->iobase + SB105X_FCR )
+#define SB105X_PUT_LCR(port,v) outb((v),(port)->iobase + SB105X_LCR )
+#define SB105X_PUT_MCR(port,v) outb((v),(port)->iobase + SB105X_MCR )
+#define SB105X_PUT_SPR(port,v) outb((v),(port)->iobase + SB105X_SPR )
+
+
+/* page 1 */
+#define SB105X_GET_REG(port,reg) inb((port)->iobase + (reg))
+#define SB105X_PUT_REG(port,reg,v) outb((v),(port)->iobase + (reg))
+
+/* page 2 */
+
+#define SB105X_PUT_PSR(port,v) outb((v),(port)->iobase + SB105X_PSR )
+
+#endif
diff --git a/drivers/staging/sb105x/sb_pci_mp.c b/drivers/staging/sb105x/sb_pci_mp.c
new file mode 100644
index 000000000000..edb2a85b9d52
--- /dev/null
+++ b/drivers/staging/sb105x/sb_pci_mp.c
@@ -0,0 +1,3196 @@
+#include "sb_pci_mp.h"
+#include <linux/module.h>
+#include <linux/parport.h>
+
+extern struct parport *parport_pc_probe_port(unsigned long base_lo,
+ unsigned long base_hi,
+ int irq, int dma,
+ struct device *dev,
+ int irqflags);
+
+static struct mp_device_t mp_devs[MAX_MP_DEV];
+static int mp_nrpcibrds = sizeof(mp_pciboards)/sizeof(mppcibrd_t);
+static int NR_BOARD=0;
+static int NR_PORTS=0;
+static struct mp_port multi_ports[MAX_MP_PORT];
+static struct irq_info irq_lists[NR_IRQS];
+
+static _INLINE_ unsigned int serial_in(struct mp_port *mtpt, int offset);
+static _INLINE_ void serial_out(struct mp_port *mtpt, int offset, int value);
+static _INLINE_ unsigned int read_option_register(struct mp_port *mtpt, int offset);
+static int sb1054_get_register(struct sb_uart_port * port, int page, int reg);
+static int sb1054_set_register(struct sb_uart_port * port, int page, int reg, int value);
+static void SendATCommand(struct mp_port * mtpt);
+static int set_deep_fifo(struct sb_uart_port * port, int status);
+static int get_deep_fifo(struct sb_uart_port * port);
+static int get_device_type(int arg);
+static int set_auto_rts(struct sb_uart_port *port, int status);
+static void mp_stop(struct tty_struct *tty);
+static void __mp_start(struct tty_struct *tty);
+static void mp_start(struct tty_struct *tty);
+static void mp_tasklet_action(unsigned long data);
+static inline void mp_update_mctrl(struct sb_uart_port *port, unsigned int set, unsigned int clear);
+static int mp_startup(struct sb_uart_state *state, int init_hw);
+static void mp_shutdown(struct sb_uart_state *state);
+static void mp_change_speed(struct sb_uart_state *state, struct MP_TERMIOS *old_termios);
+
+static inline int __mp_put_char(struct sb_uart_port *port, struct circ_buf *circ, unsigned char c);
+static int mp_put_char(struct tty_struct *tty, unsigned char ch);
+
+static void mp_put_chars(struct tty_struct *tty);
+static int mp_write(struct tty_struct *tty, const unsigned char * buf, int count);
+static int mp_write_room(struct tty_struct *tty);
+static int mp_chars_in_buffer(struct tty_struct *tty);
+static void mp_flush_buffer(struct tty_struct *tty);
+static void mp_send_xchar(struct tty_struct *tty, char ch);
+static void mp_throttle(struct tty_struct *tty);
+static void mp_unthrottle(struct tty_struct *tty);
+static int mp_get_info(struct sb_uart_state *state, struct serial_struct *retinfo);
+static int mp_set_info(struct sb_uart_state *state, struct serial_struct *newinfo);
+static int mp_get_lsr_info(struct sb_uart_state *state, unsigned int *value);
+
+static int mp_tiocmget(struct tty_struct *tty);
+static int mp_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear);
+static int mp_break_ctl(struct tty_struct *tty, int break_state);
+static int mp_do_autoconfig(struct sb_uart_state *state);
+static int mp_wait_modem_status(struct sb_uart_state *state, unsigned long arg);
+static int mp_get_count(struct sb_uart_state *state, struct serial_icounter_struct *icnt);
+static int mp_ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
+static void mp_set_termios(struct tty_struct *tty, struct MP_TERMIOS *old_termios);
+static void mp_close(struct tty_struct *tty, struct file *filp);
+static void mp_wait_until_sent(struct tty_struct *tty, int timeout);
+static void mp_hangup(struct tty_struct *tty);
+static void mp_update_termios(struct sb_uart_state *state);
+static int mp_block_til_ready(struct file *filp, struct sb_uart_state *state);
+static struct sb_uart_state *uart_get(struct uart_driver *drv, int line);
+static int mp_open(struct tty_struct *tty, struct file *filp);
+static const char *mp_type(struct sb_uart_port *port);
+static void mp_change_pm(struct sb_uart_state *state, int pm_state);
+static inline void mp_report_port(struct uart_driver *drv, struct sb_uart_port *port);
+static void mp_configure_port(struct uart_driver *drv, struct sb_uart_state *state, struct sb_uart_port *port);
+static void mp_unconfigure_port(struct uart_driver *drv, struct sb_uart_state *state);
+static int mp_register_driver(struct uart_driver *drv);
+static void mp_unregister_driver(struct uart_driver *drv);
+static int mp_add_one_port(struct uart_driver *drv, struct sb_uart_port *port);
+static int mp_remove_one_port(struct uart_driver *drv, struct sb_uart_port *port);
+static void autoconfig(struct mp_port *mtpt, unsigned int probeflags);
+static void autoconfig_irq(struct mp_port *mtpt);
+static void multi_stop_tx(struct sb_uart_port *port);
+static void multi_start_tx(struct sb_uart_port *port);
+static void multi_stop_rx(struct sb_uart_port *port);
+static void multi_enable_ms(struct sb_uart_port *port);
+static _INLINE_ void receive_chars(struct mp_port *mtpt, int *status );
+static _INLINE_ void transmit_chars(struct mp_port *mtpt);
+static _INLINE_ void check_modem_status(struct mp_port *mtpt);
+static inline void multi_handle_port(struct mp_port *mtpt);
+static irqreturn_t multi_interrupt(int irq, void *dev_id);
+static void serial_do_unlink(struct irq_info *i, struct mp_port *mtpt);
+static int serial_link_irq_chain(struct mp_port *mtpt);
+static void serial_unlink_irq_chain(struct mp_port *mtpt);
+static void multi_timeout(unsigned long data);
+static unsigned int multi_tx_empty(struct sb_uart_port *port);
+static unsigned int multi_get_mctrl(struct sb_uart_port *port);
+static void multi_set_mctrl(struct sb_uart_port *port, unsigned int mctrl);
+static void multi_break_ctl(struct sb_uart_port *port, int break_state);
+static int multi_startup(struct sb_uart_port *port);
+static void multi_shutdown(struct sb_uart_port *port);
+static unsigned int multi_get_divisor(struct sb_uart_port *port, unsigned int baud);
+static void multi_set_termios(struct sb_uart_port *port, struct MP_TERMIOS *termios, struct MP_TERMIOS *old);
+static void multi_pm(struct sb_uart_port *port, unsigned int state, unsigned int oldstate);
+static void multi_release_std_resource(struct mp_port *mtpt);
+static void multi_release_port(struct sb_uart_port *port);
+static int multi_request_port(struct sb_uart_port *port);
+static void multi_config_port(struct sb_uart_port *port, int flags);
+static int multi_verify_port(struct sb_uart_port *port, struct serial_struct *ser);
+static const char * multi_type(struct sb_uart_port *port);
+static void __init multi_init_ports(void);
+static void __init multi_register_ports(struct uart_driver *drv);
+static int init_mp_dev(struct pci_dev *pcidev, mppcibrd_t brd);
+
+static int deep[256];
+static int deep_count;
+static int fcr_arr[256];
+static int fcr_count;
+static int ttr[256];
+static int ttr_count;
+static int rtr[256];
+static int rtr_count;
+
+module_param_array(deep,int,&deep_count,0);
+module_param_array(fcr_arr,int,&fcr_count,0);
+module_param_array(ttr,int,&ttr_count,0);
+module_param_array(rtr,int,&rtr_count,0);
+
+static _INLINE_ unsigned int serial_in(struct mp_port *mtpt, int offset)
+{
+ return inb(mtpt->port.iobase + offset);
+}
+
+static _INLINE_ void serial_out(struct mp_port *mtpt, int offset, int value)
+{
+ outb(value, mtpt->port.iobase + offset);
+}
+
+static _INLINE_ unsigned int read_option_register(struct mp_port *mtpt, int offset)
+{
+ return inb(mtpt->option_base_addr + offset);
+}
+
+static int sb1053a_get_interface(struct mp_port *mtpt, int port_num)
+{
+ unsigned long option_base_addr = mtpt->option_base_addr;
+ unsigned int interface = 0;
+
+ switch (port_num)
+ {
+ case 0:
+ case 1:
+ /* set GPO[1:0] = 00 */
+ outb(0x00, option_base_addr + MP_OPTR_GPODR);
+ break;
+ case 2:
+ case 3:
+ /* set GPO[1:0] = 01 */
+ outb(0x01, option_base_addr + MP_OPTR_GPODR);
+ break;
+ case 4:
+ case 5:
+ /* set GPO[1:0] = 10 */
+ outb(0x02, option_base_addr + MP_OPTR_GPODR);
+ break;
+ default:
+ break;
+ }
+
+ port_num &= 0x1;
+
+ /* get interface */
+ interface = inb(option_base_addr + MP_OPTR_IIR0 + port_num);
+
+ /* set GPO[1:0] = 11 */
+ outb(0x03, option_base_addr + MP_OPTR_GPODR);
+
+ return (interface);
+}
+
+static int sb1054_get_register(struct sb_uart_port * port, int page, int reg)
+{
+ int ret = 0;
+ unsigned int lcr = 0;
+ unsigned int mcr = 0;
+ unsigned int tmp = 0;
+
+ if( page <= 0)
+ {
+ printk(" page 0 can not use this fuction\n");
+ return -1;
+ }
+
+ switch(page)
+ {
+ case 1:
+ lcr = SB105X_GET_LCR(port);
+ tmp = lcr | SB105X_LCR_DLAB;
+ SB105X_PUT_LCR(port, tmp);
+
+ tmp = SB105X_GET_LCR(port);
+
+ ret = SB105X_GET_REG(port,reg);
+ SB105X_PUT_LCR(port,lcr);
+ break;
+ case 2:
+ mcr = SB105X_GET_MCR(port);
+ tmp = mcr | SB105X_MCR_P2S;
+ SB105X_PUT_MCR(port,tmp);
+
+ ret = SB105X_GET_REG(port,reg);
+
+ SB105X_PUT_MCR(port,mcr);
+ break;
+ case 3:
+ lcr = SB105X_GET_LCR(port);
+ tmp = lcr | SB105X_LCR_BF;
+ SB105X_PUT_LCR(port,tmp);
+ SB105X_PUT_REG(port,SB105X_PSR,SB105X_PSR_P3KEY);
+
+ ret = SB105X_GET_REG(port,reg);
+
+ SB105X_PUT_LCR(port,lcr);
+ break;
+ case 4:
+ lcr = SB105X_GET_LCR(port);
+ tmp = lcr | SB105X_LCR_BF;
+ SB105X_PUT_LCR(port,tmp);
+ SB105X_PUT_REG(port,SB105X_PSR,SB105X_PSR_P4KEY);
+
+ ret = SB105X_GET_REG(port,reg);
+
+ SB105X_PUT_LCR(port,lcr);
+ break;
+ default:
+ printk(" error invalid page number \n");
+ return -1;
+ }
+
+ return ret;
+}
+
+static int sb1054_set_register(struct sb_uart_port * port, int page, int reg, int value)
+{
+ int lcr = 0;
+ int mcr = 0;
+ int ret = 0;
+
+ if( page <= 0)
+ {
+ printk(" page 0 can not use this fuction\n");
+ return -1;
+ }
+ switch(page)
+ {
+ case 1:
+ lcr = SB105X_GET_LCR(port);
+ SB105X_PUT_LCR(port, lcr | SB105X_LCR_DLAB);
+
+ SB105X_PUT_REG(port,reg,value);
+
+ SB105X_PUT_LCR(port, lcr);
+ ret = 1;
+ break;
+ case 2:
+ mcr = SB105X_GET_MCR(port);
+ SB105X_PUT_MCR(port, mcr | SB105X_MCR_P2S);
+
+ SB105X_PUT_REG(port,reg,value);
+
+ SB105X_PUT_MCR(port, mcr);
+ ret = 1;
+ break;
+ case 3:
+ lcr = SB105X_GET_LCR(port);
+ SB105X_PUT_LCR(port, lcr | SB105X_LCR_BF);
+ SB105X_PUT_PSR(port, SB105X_PSR_P3KEY);
+
+ SB105X_PUT_REG(port,reg,value);
+
+ SB105X_PUT_LCR(port, lcr);
+ ret = 1;
+ break;
+ case 4:
+ lcr = SB105X_GET_LCR(port);
+ SB105X_PUT_LCR(port, lcr | SB105X_LCR_BF);
+ SB105X_PUT_PSR(port, SB105X_PSR_P4KEY);
+
+ SB105X_PUT_REG(port,reg,value);
+
+ SB105X_PUT_LCR(port, lcr);
+ ret = 1;
+ break;
+ default:
+ printk(" error invalid page number \n");
+ return -1;
+ }
+
+ return ret;
+}
+
+static int set_multidrop_mode(struct sb_uart_port *port, unsigned int mode)
+{
+ int mdr = SB105XA_MDR_NPS;
+
+ if (mode & MDMODE_ENABLE)
+ {
+ mdr |= SB105XA_MDR_MDE;
+ }
+
+ if (1) //(mode & MDMODE_AUTO)
+ {
+ int efr = 0;
+ mdr |= SB105XA_MDR_AME;
+ efr = sb1054_get_register(port, PAGE_3, SB105X_EFR);
+ efr |= SB105X_EFR_SCD;
+ sb1054_set_register(port, PAGE_3, SB105X_EFR, efr);
+ }
+
+ sb1054_set_register(port, PAGE_1, SB105XA_MDR, mdr);
+ port->mdmode &= ~0x6;
+ port->mdmode |= mode;
+ printk("[%d] multidrop init: %x\n", port->line, port->mdmode);
+
+ return 0;
+}
+
+static int get_multidrop_addr(struct sb_uart_port *port)
+{
+ return sb1054_get_register(port, PAGE_3, SB105X_XOFF2);
+}
+
+static int set_multidrop_addr(struct sb_uart_port *port, unsigned int addr)
+{
+ sb1054_set_register(port, PAGE_3, SB105X_XOFF2, addr);
+
+ return 0;
+}
+
+static void SendATCommand(struct mp_port * mtpt)
+{
+ // a t cr lf
+ unsigned char ch[] = {0x61,0x74,0x0d,0x0a,0x0};
+ unsigned char lineControl;
+ unsigned char i=0;
+ unsigned char Divisor = 0xc;
+
+ lineControl = serial_inp(mtpt,UART_LCR);
+ serial_outp(mtpt,UART_LCR,(lineControl | UART_LCR_DLAB));
+ serial_outp(mtpt,UART_DLL,(Divisor & 0xff));
+ serial_outp(mtpt,UART_DLM,(Divisor & 0xff00)>>8); //baudrate is 4800
+
+
+ serial_outp(mtpt,UART_LCR,lineControl);
+ serial_outp(mtpt,UART_LCR,0x03); // N-8-1
+ serial_outp(mtpt,UART_FCR,7);
+ serial_outp(mtpt,UART_MCR,0x3);
+ while(ch[i]){
+ while((serial_inp(mtpt,UART_LSR) & 0x60) !=0x60){
+ ;
+ }
+ serial_outp(mtpt,0,ch[i++]);
+ }
+
+
+}// end of SendATCommand()
+
+static int set_deep_fifo(struct sb_uart_port * port, int status)
+{
+ int afr_status = 0;
+ afr_status = sb1054_get_register(port, PAGE_4, SB105X_AFR);
+
+ if(status == ENABLE)
+ {
+ afr_status |= SB105X_AFR_AFEN;
+ }
+ else
+ {
+ afr_status &= ~SB105X_AFR_AFEN;
+ }
+
+ sb1054_set_register(port,PAGE_4,SB105X_AFR,afr_status);
+ sb1054_set_register(port,PAGE_4,SB105X_TTR,ttr[port->line]);
+ sb1054_set_register(port,PAGE_4,SB105X_RTR,rtr[port->line]);
+ afr_status = sb1054_get_register(port, PAGE_4, SB105X_AFR);
+
+ return afr_status;
+}
+
+static int get_device_type(int arg)
+{
+ int ret;
+ ret = inb(mp_devs[arg].option_reg_addr+MP_OPTR_DIR0);
+ ret = (ret & 0xf0) >> 4;
+ switch (ret)
+ {
+ case DIR_UART_16C550:
+ return PORT_16C55X;
+ case DIR_UART_16C1050:
+ return PORT_16C105X;
+ case DIR_UART_16C1050A:
+ /*
+ if (mtpt->port.line < 2)
+ {
+ return PORT_16C105XA;
+ }
+ else
+ {
+ if (mtpt->device->device_id & 0x50)
+ {
+ return PORT_16C55X;
+ }
+ else
+ {
+ return PORT_16C105X;
+ }
+ }*/
+ return PORT_16C105XA;
+ default:
+ return PORT_UNKNOWN;
+ }
+
+}
+static int get_deep_fifo(struct sb_uart_port * port)
+{
+ int afr_status = 0;
+ afr_status = sb1054_get_register(port, PAGE_4, SB105X_AFR);
+ return afr_status;
+}
+
+static int set_auto_rts(struct sb_uart_port *port, int status)
+{
+ int atr_status = 0;
+
+#if 0
+ int efr_status = 0;
+
+ efr_status = sb1054_get_register(port, PAGE_3, SB105X_EFR);
+ if(status == ENABLE)
+ efr_status |= SB105X_EFR_ARTS;
+ else
+ efr_status &= ~SB105X_EFR_ARTS;
+ sb1054_set_register(port,PAGE_3,SB105X_EFR,efr_status);
+ efr_status = sb1054_get_register(port, PAGE_3, SB105X_EFR);
+#endif
+
+//ATR
+ atr_status = sb1054_get_register(port, PAGE_3, SB105X_ATR);
+ switch(status)
+ {
+ case RS422PTP:
+ atr_status = (SB105X_ATR_TPS) | (SB105X_ATR_A80);
+ break;
+ case RS422MD:
+ atr_status = (SB105X_ATR_TPS) | (SB105X_ATR_TCMS) | (SB105X_ATR_A80);
+ break;
+ case RS485NE:
+ atr_status = (SB105X_ATR_RCMS) | (SB105X_ATR_TPS) | (SB105X_ATR_TCMS) | (SB105X_ATR_A80);
+ break;
+ case RS485ECHO:
+ atr_status = (SB105X_ATR_TPS) | (SB105X_ATR_TCMS) | (SB105X_ATR_A80);
+ break;
+ }
+
+ sb1054_set_register(port,PAGE_3,SB105X_ATR,atr_status);
+ atr_status = sb1054_get_register(port, PAGE_3, SB105X_ATR);
+
+ return atr_status;
+}
+
+static void mp_stop(struct tty_struct *tty)
+{
+ struct sb_uart_state *state = tty->driver_data;
+ struct sb_uart_port *port = state->port;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->lock, flags);
+ port->ops->stop_tx(port);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void __mp_start(struct tty_struct *tty)
+{
+ struct sb_uart_state *state = tty->driver_data;
+ struct sb_uart_port *port = state->port;
+
+ if (!uart_circ_empty(&state->info->xmit) && state->info->xmit.buf &&
+ !tty->stopped && !tty->hw_stopped)
+ port->ops->start_tx(port);
+}
+
+static void mp_start(struct tty_struct *tty)
+{
+ __mp_start(tty);
+}
+
+static void mp_tasklet_action(unsigned long data)
+{
+ struct sb_uart_state *state = (struct sb_uart_state *)data;
+ struct tty_struct *tty;
+
+ printk("tasklet is called!\n");
+ tty = state->info->tty;
+ tty_wakeup(tty);
+}
+
+static inline void mp_update_mctrl(struct sb_uart_port *port, unsigned int set, unsigned int clear)
+{
+ unsigned int old;
+
+ old = port->mctrl;
+ port->mctrl = (old & ~clear) | set;
+ if (old != port->mctrl)
+ port->ops->set_mctrl(port, port->mctrl);
+}
+
+#define uart_set_mctrl(port,set) mp_update_mctrl(port,set,0)
+#define uart_clear_mctrl(port,clear) mp_update_mctrl(port,0,clear)
+
+static int mp_startup(struct sb_uart_state *state, int init_hw)
+{
+ struct sb_uart_info *info = state->info;
+ struct sb_uart_port *port = state->port;
+ unsigned long page;
+ int retval = 0;
+
+ if (info->flags & UIF_INITIALIZED)
+ return 0;
+
+ if (info->tty)
+ set_bit(TTY_IO_ERROR, &info->tty->flags);
+
+ if (port->type == PORT_UNKNOWN)
+ return 0;
+
+ if (!info->xmit.buf) {
+ page = get_zeroed_page(GFP_KERNEL);
+ if (!page)
+ return -ENOMEM;
+
+ info->xmit.buf = (unsigned char *) page;
+
+ uart_circ_clear(&info->xmit);
+ }
+
+ retval = port->ops->startup(port);
+ if (retval == 0) {
+ if (init_hw) {
+ mp_change_speed(state, NULL);
+
+ if (info->tty->termios.c_cflag & CBAUD)
+ uart_set_mctrl(port, TIOCM_RTS | TIOCM_DTR);
+ }
+
+ info->flags |= UIF_INITIALIZED;
+
+
+ clear_bit(TTY_IO_ERROR, &info->tty->flags);
+ }
+
+ if (retval && capable(CAP_SYS_ADMIN))
+ retval = 0;
+
+ return retval;
+}
+
+static void mp_shutdown(struct sb_uart_state *state)
+{
+ struct sb_uart_info *info = state->info;
+ struct sb_uart_port *port = state->port;
+
+ if (info->tty)
+ set_bit(TTY_IO_ERROR, &info->tty->flags);
+
+ if (info->flags & UIF_INITIALIZED) {
+ info->flags &= ~UIF_INITIALIZED;
+
+ if (!info->tty || (info->tty->termios.c_cflag & HUPCL))
+ uart_clear_mctrl(port, TIOCM_DTR | TIOCM_RTS);
+
+ wake_up_interruptible(&info->delta_msr_wait);
+
+ port->ops->shutdown(port);
+
+ synchronize_irq(port->irq);
+ }
+ tasklet_kill(&info->tlet);
+
+ if (info->xmit.buf) {
+ free_page((unsigned long)info->xmit.buf);
+ info->xmit.buf = NULL;
+ }
+}
+
+static void mp_change_speed(struct sb_uart_state *state, struct MP_TERMIOS *old_termios)
+{
+ struct tty_struct *tty = state->info->tty;
+ struct sb_uart_port *port = state->port;
+
+ if (!tty || port->type == PORT_UNKNOWN)
+ return;
+
+ if (tty->termios.c_cflag & CRTSCTS)
+ state->info->flags |= UIF_CTS_FLOW;
+ else
+ state->info->flags &= ~UIF_CTS_FLOW;
+
+ if (tty->termios.c_cflag & CLOCAL)
+ state->info->flags &= ~UIF_CHECK_CD;
+ else
+ state->info->flags |= UIF_CHECK_CD;
+
+ port->ops->set_termios(port, &tty->termios, old_termios);
+}
+
+static inline int __mp_put_char(struct sb_uart_port *port, struct circ_buf *circ, unsigned char c)
+{
+ unsigned long flags;
+ int ret = 0;
+
+ if (!circ->buf)
+ return 0;
+
+ spin_lock_irqsave(&port->lock, flags);
+ if (uart_circ_chars_free(circ) != 0) {
+ circ->buf[circ->head] = c;
+ circ->head = (circ->head + 1) & (UART_XMIT_SIZE - 1);
+ ret = 1;
+ }
+ spin_unlock_irqrestore(&port->lock, flags);
+ return ret;
+}
+
+static int mp_put_char(struct tty_struct *tty, unsigned char ch)
+{
+ struct sb_uart_state *state = tty->driver_data;
+
+ return __mp_put_char(state->port, &state->info->xmit, ch);
+}
+
+static void mp_put_chars(struct tty_struct *tty)
+{
+ mp_start(tty);
+}
+
+static int mp_write(struct tty_struct *tty, const unsigned char * buf, int count)
+{
+ struct sb_uart_state *state = tty->driver_data;
+ struct sb_uart_port *port;
+ struct circ_buf *circ;
+ int c, ret = 0;
+
+ if (!state || !state->info) {
+ return -EL3HLT;
+ }
+
+ port = state->port;
+ circ = &state->info->xmit;
+
+ if (!circ->buf)
+ return 0;
+
+ while (1) {
+ c = CIRC_SPACE_TO_END(circ->head, circ->tail, UART_XMIT_SIZE);
+ if (count < c)
+ c = count;
+ if (c <= 0)
+ break;
+ memcpy(circ->buf + circ->head, buf, c);
+
+ circ->head = (circ->head + c) & (UART_XMIT_SIZE - 1);
+ buf += c;
+ count -= c;
+ ret += c;
+ }
+ mp_start(tty);
+ return ret;
+}
+
+static int mp_write_room(struct tty_struct *tty)
+{
+ struct sb_uart_state *state = tty->driver_data;
+
+ return uart_circ_chars_free(&state->info->xmit);
+}
+
+static int mp_chars_in_buffer(struct tty_struct *tty)
+{
+ struct sb_uart_state *state = tty->driver_data;
+
+ return uart_circ_chars_pending(&state->info->xmit);
+}
+
+static void mp_flush_buffer(struct tty_struct *tty)
+{
+ struct sb_uart_state *state = tty->driver_data;
+ struct sb_uart_port *port;
+ unsigned long flags;
+
+ if (!state || !state->info) {
+ return;
+ }
+
+ port = state->port;
+ spin_lock_irqsave(&port->lock, flags);
+ uart_circ_clear(&state->info->xmit);
+ spin_unlock_irqrestore(&port->lock, flags);
+ wake_up_int