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Diffstat (limited to 'drivers/staging/octeon-usb/octeon-hcd.h')
| -rw-r--r-- | drivers/staging/octeon-usb/octeon-hcd.h | 1847 |
1 files changed, 0 insertions, 1847 deletions
diff --git a/drivers/staging/octeon-usb/octeon-hcd.h b/drivers/staging/octeon-usb/octeon-hcd.h deleted file mode 100644 index 9ed619c93a4e..000000000000 --- a/drivers/staging/octeon-usb/octeon-hcd.h +++ /dev/null @@ -1,1847 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Octeon HCD hardware register definitions. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Some parts of the code were originally released under BSD license: - * - * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights - * reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * - * * Neither the name of Cavium Networks nor the names of - * its contributors may be used to endorse or promote products - * derived from this software without specific prior written - * permission. - * - * This Software, including technical data, may be subject to U.S. export - * control laws, including the U.S. Export Administration Act and its associated - * regulations, and may be subject to export or import regulations in other - * countries. - * - * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" - * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR - * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO - * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION - * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM - * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, - * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF - * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR - * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR - * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. - */ - -#ifndef __OCTEON_HCD_H__ -#define __OCTEON_HCD_H__ - -#include <asm/bitfield.h> - -#define CVMX_USBCXBASE 0x00016F0010000000ull -#define CVMX_USBCXREG1(reg, bid) \ - (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \ - ((bid) & 1) * 0x100000000000ull) -#define CVMX_USBCXREG2(reg, bid, off) \ - (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \ - (((off) & 7) + ((bid) & 1) * 0x8000000000ull) * 32) - -#define CVMX_USBCX_GAHBCFG(bid) CVMX_USBCXREG1(0x008, bid) -#define CVMX_USBCX_GHWCFG3(bid) CVMX_USBCXREG1(0x04c, bid) -#define CVMX_USBCX_GINTMSK(bid) CVMX_USBCXREG1(0x018, bid) -#define CVMX_USBCX_GINTSTS(bid) CVMX_USBCXREG1(0x014, bid) -#define CVMX_USBCX_GNPTXFSIZ(bid) CVMX_USBCXREG1(0x028, bid) -#define CVMX_USBCX_GNPTXSTS(bid) CVMX_USBCXREG1(0x02c, bid) -#define CVMX_USBCX_GOTGCTL(bid) CVMX_USBCXREG1(0x000, bid) -#define CVMX_USBCX_GRSTCTL(bid) CVMX_USBCXREG1(0x010, bid) -#define CVMX_USBCX_GRXFSIZ(bid) CVMX_USBCXREG1(0x024, bid) -#define CVMX_USBCX_GRXSTSPH(bid) CVMX_USBCXREG1(0x020, bid) -#define CVMX_USBCX_GUSBCFG(bid) CVMX_USBCXREG1(0x00c, bid) -#define CVMX_USBCX_HAINT(bid) CVMX_USBCXREG1(0x414, bid) -#define CVMX_USBCX_HAINTMSK(bid) CVMX_USBCXREG1(0x418, bid) -#define CVMX_USBCX_HCCHARX(off, bid) CVMX_USBCXREG2(0x500, bid, off) -#define CVMX_USBCX_HCFG(bid) CVMX_USBCXREG1(0x400, bid) -#define CVMX_USBCX_HCINTMSKX(off, bid) CVMX_USBCXREG2(0x50c, bid, off) -#define CVMX_USBCX_HCINTX(off, bid) CVMX_USBCXREG2(0x508, bid, off) -#define CVMX_USBCX_HCSPLTX(off, bid) CVMX_USBCXREG2(0x504, bid, off) -#define CVMX_USBCX_HCTSIZX(off, bid) CVMX_USBCXREG2(0x510, bid, off) -#define CVMX_USBCX_HFIR(bid) CVMX_USBCXREG1(0x404, bid) -#define CVMX_USBCX_HFNUM(bid) CVMX_USBCXREG1(0x408, bid) -#define CVMX_USBCX_HPRT(bid) CVMX_USBCXREG1(0x440, bid) -#define CVMX_USBCX_HPTXFSIZ(bid) CVMX_USBCXREG1(0x100, bid) -#define CVMX_USBCX_HPTXSTS(bid) CVMX_USBCXREG1(0x410, bid) - -#define CVMX_USBNXBID1(bid) (((bid) & 1) * 0x10000000ull) -#define CVMX_USBNXBID2(bid) (((bid) & 1) * 0x100000000000ull) - -#define CVMX_USBNXREG1(reg, bid) \ - (CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid)) -#define CVMX_USBNXREG2(reg, bid) \ - (CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid)) - -#define CVMX_USBNX_CLK_CTL(bid) CVMX_USBNXREG1(0x10, bid) -#define CVMX_USBNX_DMA0_INB_CHN0(bid) CVMX_USBNXREG2(0x818, bid) -#define CVMX_USBNX_DMA0_OUTB_CHN0(bid) CVMX_USBNXREG2(0x858, bid) -#define CVMX_USBNX_USBP_CTL_STATUS(bid) CVMX_USBNXREG1(0x18, bid) - -/** - * cvmx_usbc#_gahbcfg - * - * Core AHB Configuration Register (GAHBCFG) - * - * This register can be used to configure the core after power-on or a change in - * mode of operation. This register mainly contains AHB system-related - * configuration parameters. The AHB is the processor interface to the O2P USB - * core. In general, software need not know about this interface except to - * program the values as specified. - * - * The application must program this register as part of the O2P USB core - * initialization. Do not change this register after the initial programming. - */ -union cvmx_usbcx_gahbcfg { - u32 u32; - /** - * struct cvmx_usbcx_gahbcfg_s - * @ptxfemplvl: Periodic TxFIFO Empty Level (PTxFEmpLvl) - * Software should set this bit to 0x1. - * Indicates when the Periodic TxFIFO Empty Interrupt bit in the - * Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This - * bit is used only in Slave mode. - * * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic - * TxFIFO is half empty - * * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic - * TxFIFO is completely empty - * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) - * Software should set this bit to 0x1. - * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in - * the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. - * This bit is used only in Slave mode. - * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non- - * Periodic TxFIFO is half empty - * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non- - * Periodic TxFIFO is completely empty - * @dmaen: DMA Enable (DMAEn) - * * 1'b0: Core operates in Slave mode - * * 1'b1: Core operates in a DMA mode - * @hbstlen: Burst Length/Type (HBstLen) - * This field has not effect and should be left as 0x0. - * @glblintrmsk: Global Interrupt Mask (GlblIntrMsk) - * Software should set this field to 0x1. - * The application uses this bit to mask or unmask the interrupt - * line assertion to itself. Irrespective of this bit's setting, - * the interrupt status registers are updated by the core. - * * 1'b0: Mask the interrupt assertion to the application. - * * 1'b1: Unmask the interrupt assertion to the application. - */ - struct cvmx_usbcx_gahbcfg_s { - __BITFIELD_FIELD(u32 reserved_9_31 : 23, - __BITFIELD_FIELD(u32 ptxfemplvl : 1, - __BITFIELD_FIELD(u32 nptxfemplvl : 1, - __BITFIELD_FIELD(u32 reserved_6_6 : 1, - __BITFIELD_FIELD(u32 dmaen : 1, - __BITFIELD_FIELD(u32 hbstlen : 4, - __BITFIELD_FIELD(u32 glblintrmsk : 1, - ;))))))) - } s; -}; - -/** - * cvmx_usbc#_ghwcfg3 - * - * User HW Config3 Register (GHWCFG3) - * - * This register contains the configuration options of the O2P USB core. - */ -union cvmx_usbcx_ghwcfg3 { - u32 u32; - /** - * struct cvmx_usbcx_ghwcfg3_s - * @dfifodepth: DFIFO Depth (DfifoDepth) - * This value is in terms of 32-bit words. - * * Minimum value is 32 - * * Maximum value is 32768 - * @ahbphysync: AHB and PHY Synchronous (AhbPhySync) - * Indicates whether AHB and PHY clocks are synchronous to - * each other. - * * 1'b0: No - * * 1'b1: Yes - * This bit is tied to 1. - * @rsttype: Reset Style for Clocked always Blocks in RTL (RstType) - * * 1'b0: Asynchronous reset is used in the core - * * 1'b1: Synchronous reset is used in the core - * @optfeature: Optional Features Removed (OptFeature) - * Indicates whether the User ID register, GPIO interface ports, - * and SOF toggle and counter ports were removed for gate count - * optimization. - * @vendor_control_interface_support: Vendor Control Interface Support - * * 1'b0: Vendor Control Interface is not available on the core. - * * 1'b1: Vendor Control Interface is available. - * @i2c_selection: I2C Selection - * * 1'b0: I2C Interface is not available on the core. - * * 1'b1: I2C Interface is available on the core. - * @otgen: OTG Function Enabled (OtgEn) - * The application uses this bit to indicate the O2P USB core's - * OTG capabilities. - * * 1'b0: Not OTG capable - * * 1'b1: OTG Capable - * @pktsizewidth: Width of Packet Size Counters (PktSizeWidth) - * * 3'b000: 4 bits - * * 3'b001: 5 bits - * * 3'b010: 6 bits - * * 3'b011: 7 bits - * * 3'b100: 8 bits - * * 3'b101: 9 bits - * * 3'b110: 10 bits - * * Others: Reserved - * @xfersizewidth: Width of Transfer Size Counters (XferSizeWidth) - * * 4'b0000: 11 bits - * * 4'b0001: 12 bits - * - ... - * * 4'b1000: 19 bits - * * Others: Reserved - */ - struct cvmx_usbcx_ghwcfg3_s { - __BITFIELD_FIELD(u32 dfifodepth : 16, - __BITFIELD_FIELD(u32 reserved_13_15 : 3, - __BITFIELD_FIELD(u32 ahbphysync : 1, - __BITFIELD_FIELD(u32 rsttype : 1, - __BITFIELD_FIELD(u32 optfeature : 1, - __BITFIELD_FIELD(u32 vendor_control_interface_support : 1, - __BITFIELD_FIELD(u32 i2c_selection : 1, - __BITFIELD_FIELD(u32 otgen : 1, - __BITFIELD_FIELD(u32 pktsizewidth : 3, - __BITFIELD_FIELD(u32 xfersizewidth : 4, - ;)))))))))) - } s; -}; - -/** - * cvmx_usbc#_gintmsk - * - * Core Interrupt Mask Register (GINTMSK) - * - * This register works with the Core Interrupt register to interrupt the - * application. When an interrupt bit is masked, the interrupt associated with - * that bit will not be generated. However, the Core Interrupt (GINTSTS) - * register bit corresponding to that interrupt will still be set. - * Mask interrupt: 1'b0, Unmask interrupt: 1'b1 - */ -union cvmx_usbcx_gintmsk { - u32 u32; - /** - * struct cvmx_usbcx_gintmsk_s - * @wkupintmsk: Resume/Remote Wakeup Detected Interrupt Mask - * (WkUpIntMsk) - * @sessreqintmsk: Session Request/New Session Detected Interrupt Mask - * (SessReqIntMsk) - * @disconnintmsk: Disconnect Detected Interrupt Mask (DisconnIntMsk) - * @conidstschngmsk: Connector ID Status Change Mask (ConIDStsChngMsk) - * @ptxfempmsk: Periodic TxFIFO Empty Mask (PTxFEmpMsk) - * @hchintmsk: Host Channels Interrupt Mask (HChIntMsk) - * @prtintmsk: Host Port Interrupt Mask (PrtIntMsk) - * @fetsuspmsk: Data Fetch Suspended Mask (FetSuspMsk) - * @incomplpmsk: Incomplete Periodic Transfer Mask (incomplPMsk) - * Incomplete Isochronous OUT Transfer Mask - * (incompISOOUTMsk) - * @incompisoinmsk: Incomplete Isochronous IN Transfer Mask - * (incompISOINMsk) - * @oepintmsk: OUT Endpoints Interrupt Mask (OEPIntMsk) - * @inepintmsk: IN Endpoints Interrupt Mask (INEPIntMsk) - * @epmismsk: Endpoint Mismatch Interrupt Mask (EPMisMsk) - * @eopfmsk: End of Periodic Frame Interrupt Mask (EOPFMsk) - * @isooutdropmsk: Isochronous OUT Packet Dropped Interrupt Mask - * (ISOOutDropMsk) - * @enumdonemsk: Enumeration Done Mask (EnumDoneMsk) - * @usbrstmsk: USB Reset Mask (USBRstMsk) - * @usbsuspmsk: USB Suspend Mask (USBSuspMsk) - * @erlysuspmsk: Early Suspend Mask (ErlySuspMsk) - * @i2cint: I2C Interrupt Mask (I2CINT) - * @ulpickintmsk: ULPI Carkit Interrupt Mask (ULPICKINTMsk) - * I2C Carkit Interrupt Mask (I2CCKINTMsk) - * @goutnakeffmsk: Global OUT NAK Effective Mask (GOUTNakEffMsk) - * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask - * (GINNakEffMsk) - * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) - * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk) - * @sofmsk: Start of (micro)Frame Mask (SofMsk) - * @otgintmsk: OTG Interrupt Mask (OTGIntMsk) - * @modemismsk: Mode Mismatch Interrupt Mask (ModeMisMsk) - */ - struct cvmx_usbcx_gintmsk_s { - __BITFIELD_FIELD(u32 wkupintmsk : 1, - __BITFIELD_FIELD(u32 sessreqintmsk : 1, - __BITFIELD_FIELD(u32 disconnintmsk : 1, - __BITFIELD_FIELD(u32 conidstschngmsk : 1, - __BITFIELD_FIELD(u32 reserved_27_27 : 1, - __BITFIELD_FIELD(u32 ptxfempmsk : 1, - __BITFIELD_FIELD(u32 hchintmsk : 1, - __BITFIELD_FIELD(u32 prtintmsk : 1, - __BITFIELD_FIELD(u32 reserved_23_23 : 1, - __BITFIELD_FIELD(u32 fetsuspmsk : 1, - __BITFIELD_FIELD(u32 incomplpmsk : 1, - __BITFIELD_FIELD(u32 incompisoinmsk : 1, - __BITFIELD_FIELD(u32 oepintmsk : 1, - __BITFIELD_FIELD(u32 inepintmsk : 1, - __BITFIELD_FIELD(u32 epmismsk : 1, - __BITFIELD_FIELD(u32 reserved_16_16 : 1, - __BITFIELD_FIELD(u32 eopfmsk : 1, - __BITFIELD_FIELD(u32 isooutdropmsk : 1, - __BITFIELD_FIELD(u32 enumdonemsk : 1, - __BITFIELD_FIELD(u32 usbrstmsk : 1, - __BITFIELD_FIELD(u32 usbsuspmsk : 1, - __BITFIELD_FIELD(u32 erlysuspmsk : 1, - __BITFIELD_FIELD(u32 i2cint : 1, - __BITFIELD_FIELD(u32 ulpickintmsk : 1, - __BITFIELD_FIELD(u32 goutnakeffmsk : 1, - __BITFIELD_FIELD(u32 ginnakeffmsk : 1, - __BITFIELD_FIELD(u32 nptxfempmsk : 1, - __BITFIELD_FIELD(u32 rxflvlmsk : 1, - __BITFIELD_FIELD(u32 sofmsk : 1, - __BITFIELD_FIELD(u32 otgintmsk : 1, - __BITFIELD_FIELD(u32 modemismsk : 1, - __BITFIELD_FIELD(u32 reserved_0_0 : 1, - ;)))))))))))))))))))))))))))))))) - } s; -}; - -/** - * cvmx_usbc#_gintsts - * - * Core Interrupt Register (GINTSTS) - * - * This register interrupts the application for system-level events in the - * current mode of operation (Device mode or Host mode). It is shown in - * Interrupt. Some of the bits in this register are valid only in Host mode, - * while others are valid in Device mode only. This register also indicates the - * current mode of operation. In order to clear the interrupt status bits of - * type R_SS_WC, the application must write 1'b1 into the bit. The FIFO status - * interrupts are read only; once software reads from or writes to the FIFO - * while servicing these interrupts, FIFO interrupt conditions are cleared - * automatically. - */ -union cvmx_usbcx_gintsts { - u32 u32; - /** - * struct cvmx_usbcx_gintsts_s - * @wkupint: Resume/Remote Wakeup Detected Interrupt (WkUpInt) - * In Device mode, this interrupt is asserted when a resume is - * detected on the USB. In Host mode, this interrupt is asserted - * when a remote wakeup is detected on the USB. - * For more information on how to use this interrupt, see "Partial - * Power-Down and Clock Gating Programming Model" on - * page 353. - * @sessreqint: Session Request/New Session Detected Interrupt - * (SessReqInt) - * In Host mode, this interrupt is asserted when a session request - * is detected from the device. In Device mode, this interrupt is - * asserted when the utmiotg_bvalid signal goes high. - * For more information on how to use this interrupt, see "Partial - * Power-Down and Clock Gating Programming Model" on - * page 353. - * @disconnint: Disconnect Detected Interrupt (DisconnInt) - * Asserted when a device disconnect is detected. - * @conidstschng: Connector ID Status Change (ConIDStsChng) - * The core sets this bit when there is a change in connector ID - * status. - * @ptxfemp: Periodic TxFIFO Empty (PTxFEmp) - * Asserted when the Periodic Transmit FIFO is either half or - * completely empty and there is space for at least one entry to be - * written in the Periodic Request Queue. The half or completely - * empty status is determined by the Periodic TxFIFO Empty Level - * bit in the Core AHB Configuration register - * (GAHBCFG.PTxFEmpLvl). - * @hchint: Host Channels Interrupt (HChInt) - * The core sets this bit to indicate that an interrupt is pending - * on one of the channels of the core (in Host mode). The - * application must read the Host All Channels Interrupt (HAINT) - * register to determine the exact number of the channel on which - * the interrupt occurred, and then read the corresponding Host - * Channel-n Interrupt (HCINTn) register to determine the exact - * cause of the interrupt. The application must clear the - * appropriate status bit in the HCINTn register to clear this bit. - * @prtint: Host Port Interrupt (PrtInt) - * The core sets this bit to indicate a change in port status of - * one of the O2P USB core ports in Host mode. The application must - * read the Host Port Control and Status (HPRT) register to - * determine the exact event that caused this interrupt. The - * application must clear the appropriate status bit in the Host - * Port Control and Status register to clear this bit. - * @fetsusp: Data Fetch Suspended (FetSusp) - * This interrupt is valid only in DMA mode. This interrupt - * indicates that the core has stopped fetching data for IN - * endpoints due to the unavailability of TxFIFO space or Request - * Queue space. This interrupt is used by the application for an - * endpoint mismatch algorithm. - * @incomplp: Incomplete Periodic Transfer (incomplP) - * In Host mode, the core sets this interrupt bit when there are - * incomplete periodic transactions still pending which are - * scheduled for the current microframe. - * Incomplete Isochronous OUT Transfer (incompISOOUT) - * The Device mode, the core sets this interrupt to indicate that - * there is at least one isochronous OUT endpoint on which the - * transfer is not completed in the current microframe. This - * interrupt is asserted along with the End of Periodic Frame - * Interrupt (EOPF) bit in this register. - * @incompisoin: Incomplete Isochronous IN Transfer (incompISOIN) - * The core sets this interrupt to indicate that there is at least - * one isochronous IN endpoint on which the transfer is not - * completed in the current microframe. This interrupt is asserted - * along with the End of Periodic Frame Interrupt (EOPF) bit in - * this register. - * @oepint: OUT Endpoints Interrupt (OEPInt) - * The core sets this bit to indicate that an interrupt is pending - * on one of the OUT endpoints of the core (in Device mode). The - * application must read the Device All Endpoints Interrupt - * (DAINT) register to determine the exact number of the OUT - * endpoint on which the interrupt occurred, and then read the - * corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) - * register to determine the exact cause of the interrupt. The - * application must clear the appropriate status bit in the - * corresponding DOEPINTn register to clear this bit. - * @iepint: IN Endpoints Interrupt (IEPInt) - * The core sets this bit to indicate that an interrupt is pending - * on one of the IN endpoints of the core (in Device mode). The - * application must read the Device All Endpoints Interrupt - * (DAINT) register to determine the exact number of the IN - * endpoint on which the interrupt occurred, and then read the - * corresponding Device IN Endpoint-n Interrupt (DIEPINTn) - * register to determine the exact cause of the interrupt. The - * application must clear the appropriate status bit in the - * corresponding DIEPINTn register to clear this bit. - * @epmis: Endpoint Mismatch Interrupt (EPMis) - * Indicates that an IN token has been received for a non-periodic - * endpoint, but the data for another endpoint is present in the - * top of the Non-Periodic Transmit FIFO and the IN endpoint - * mismatch count programmed by the application has expired. - * @eopf: End of Periodic Frame Interrupt (EOPF) - * Indicates that the period specified in the Periodic Frame - * Interval field of the Device Configuration register - * (DCFG.PerFrInt) has been reached in the current microframe. - * @isooutdrop: Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) - * The core sets this bit when it fails to write an isochronous OUT - * packet into the RxFIFO because the RxFIFO doesn't have - * enough space to accommodate a maximum packet size packet - * for the isochronous OUT endpoint. - * @enumdone: Enumeration Done (EnumDone) - * The core sets this bit to indicate that speed enumeration is - * complete. The application must read the Device Status (DSTS) - * register to obtain the enumerated speed. - * @usbrst: USB Reset (USBRst) - * The core sets this bit to indicate that a reset is detected on - * the USB. - * @usbsusp: USB Suspend (USBSusp) - * The core sets this bit to indicate that a suspend was detected - * on the USB. The core enters the Suspended state when there - * is no activity on the phy_line_state_i signal for an extended - * period of time. - * @erlysusp: Early Suspend (ErlySusp) - * The core sets this bit to indicate that an Idle state has been - * detected on the USB for 3 ms. - * @i2cint: I2C Interrupt (I2CINT) - * This bit is always 0x0. - * @ulpickint: ULPI Carkit Interrupt (ULPICKINT) - * This bit is always 0x0. - * @goutnakeff: Global OUT NAK Effective (GOUTNakEff) - * Indicates that the Set Global OUT NAK bit in the Device Control - * register (DCTL.SGOUTNak), set by the application, has taken - * effect in the core. This bit can be cleared by writing the Clear - * Global OUT NAK bit in the Device Control register - * (DCTL.CGOUTNak). - * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff) - * Indicates that the Set Global Non-Periodic IN NAK bit in the - * Device Control register (DCTL.SGNPInNak), set by the - * application, has taken effect in the core. That is, the core has - * sampled the Global IN NAK bit set by the application. This bit - * can be cleared by clearing the Clear Global Non-Periodic IN - * NAK bit in the Device Control register (DCTL.CGNPInNak). - * This interrupt does not necessarily mean that a NAK handshake - * is sent out on the USB. The STALL bit takes precedence over - * the NAK bit. - * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp) - * This interrupt is asserted when the Non-Periodic TxFIFO is - * either half or completely empty, and there is space for at least - * one entry to be written to the Non-Periodic Transmit Request - * Queue. The half or completely empty status is determined by - * the Non-Periodic TxFIFO Empty Level bit in the Core AHB - * Configuration register (GAHBCFG.NPTxFEmpLvl). - * @rxflvl: RxFIFO Non-Empty (RxFLvl) - * Indicates that there is at least one packet pending to be read - * from the RxFIFO. - * @sof: Start of (micro)Frame (Sof) - * In Host mode, the core sets this bit to indicate that an SOF - * (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the - * USB. The application must write a 1 to this bit to clear the - * interrupt. - * In Device mode, in the core sets this bit to indicate that an - * SOF token has been received on the USB. The application can read - * the Device Status register to get the current (micro)frame - * number. This interrupt is seen only when the core is operating - * at either HS or FS. - * @otgint: OTG Interrupt (OTGInt) - * The core sets this bit to indicate an OTG protocol event. The - * application must read the OTG Interrupt Status (GOTGINT) - * register to determine the exact event that caused this - * interrupt. The application must clear the appropriate status bit - * in the GOTGINT register to clear this bit. - * @modemis: Mode Mismatch Interrupt (ModeMis) - * The core sets this bit when the application is trying to access: - * * A Host mode register, when the core is operating in Device - * mode - * * A Device mode register, when the core is operating in Host - * mode - * The register access is completed on the AHB with an OKAY - * response, but is ignored by the core internally and doesn't - * affect the operation of the core. - * @curmod: Current Mode of Operation (CurMod) - * Indicates the current mode of operation. - * * 1'b0: Device mode - * * 1'b1: Host mode - */ - struct cvmx_usbcx_gintsts_s { - __BITFIELD_FIELD(u32 wkupint : 1, - __BITFIELD_FIELD(u32 sessreqint : 1, - __BITFIELD_FIELD(u32 disconnint : 1, - __BITFIELD_FIELD(u32 conidstschng : 1, - __BITFIELD_FIELD(u32 reserved_27_27 : 1, - __BITFIELD_FIELD(u32 ptxfemp : 1, - __BITFIELD_FIELD(u32 hchint : 1, - __BITFIELD_FIELD(u32 prtint : 1, - __BITFIELD_FIELD(u32 reserved_23_23 : 1, - __BITFIELD_FIELD(u32 fetsusp : 1, - __BITFIELD_FIELD(u32 incomplp : 1, - __BITFIELD_FIELD(u32 incompisoin : 1, - __BITFIELD_FIELD(u32 oepint : 1, - __BITFIELD_FIELD(u32 iepint : 1, - __BITFIELD_FIELD(u32 epmis : 1, - __BITFIELD_FIELD(u32 reserved_16_16 : 1, - __BITFIELD_FIELD(u32 eopf : 1, - __BITFIELD_FIELD(u32 isooutdrop : 1, - __BITFIELD_FIELD(u32 enumdone : 1, - __BITFIELD_FIELD(u32 usbrst : 1, - __BITFIELD_FIELD(u32 usbsusp : 1, - __BITFIELD_FIELD(u32 erlysusp : 1, - __BITFIELD_FIELD(u32 i2cint : 1, - __BITFIELD_FIELD(u32 ulpickint : 1, - __BITFIELD_FIELD(u32 goutnakeff : 1, - __BITFIELD_FIELD(u32 ginnakeff : 1, - __BITFIELD_FIELD(u32 nptxfemp : 1, - __BITFIELD_FIELD(u32 rxflvl : 1, - __BITFIELD_FIELD(u32 sof : 1, - __BITFIELD_FIELD(u32 otgint : 1, - __BITFIELD_FIELD(u32 modemis : 1, - __BITFIELD_FIELD(u32 curmod : 1, - ;)))))))))))))))))))))))))))))))) - } s; -}; - -/** - * cvmx_usbc#_gnptxfsiz - * - * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ) - * - * The application can program the RAM size and the memory start address for the - * Non-Periodic TxFIFO. - */ -union cvmx_usbcx_gnptxfsiz { - u32 u32; - /** - * struct cvmx_usbcx_gnptxfsiz_s - * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep) - * This value is in terms of 32-bit words. - * Minimum value is 16 - * Maximum value is 32768 - * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr) - * This field contains the memory start address for Non-Periodic - * Transmit FIFO RAM. - */ - struct cvmx_usbcx_gnptxfsiz_s { - __BITFIELD_FIELD(u32 nptxfdep : 16, - __BITFIELD_FIELD(u32 nptxfstaddr : 16, - ;)) - } s; -}; - -/** - * cvmx_usbc#_gnptxsts - * - * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS) - * - * This read-only register contains the free space information for the - * Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue. - */ -union cvmx_usbcx_gnptxsts { - u32 u32; - /** - * struct cvmx_usbcx_gnptxsts_s - * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop) - * Entry in the Non-Periodic Tx Request Queue that is currently - * being processed by the MAC. - * * Bits [30:27]: Channel/endpoint number - * * Bits [26:25]: - * - 2'b00: IN/OUT token - * - 2'b01: Zero-length transmit packet (device IN/host OUT) - * - 2'b10: PING/CSPLIT token - * - 2'b11: Channel halt command - * * Bit [24]: Terminate (last entry for selected channel/endpoint) - * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available - * (NPTxQSpcAvail) - * Indicates the amount of free space available in the Non- - * Periodic Transmit Request Queue. This queue holds both IN - * and OUT requests in Host mode. Device mode has only IN - * requests. - * * 8'h0: Non-Periodic Transmit Request Queue is full - * * 8'h1: 1 location available - * * 8'h2: 2 locations available - * * n: n locations available (0..8) - * * Others: Reserved - * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail) - * Indicates the amount of free space available in the Non- - * Periodic TxFIFO. - * Values are in terms of 32-bit words. - * * 16'h0: Non-Periodic TxFIFO is full - * * 16'h1: 1 word available - * * 16'h2: 2 words available - * * 16'hn: n words available (where 0..32768) - * * 16'h8000: 32768 words available - * * Others: Reserved - */ - struct cvmx_usbcx_gnptxsts_s { - __BITFIELD_FIELD(u32 reserved_31_31 : 1, - __BITFIELD_FIELD(u32 nptxqtop : 7, - __BITFIELD_FIELD(u32 nptxqspcavail : 8, - __BITFIELD_FIELD(u32 nptxfspcavail : 16, - ;)))) - } s; -}; - -/** - * cvmx_usbc#_grstctl - * - * Core Reset Register (GRSTCTL) - * - * The application uses this register to reset various hardware features inside - * the core. - */ -union cvmx_usbcx_grstctl { - u32 u32; - /** - * struct cvmx_usbcx_grstctl_s - * @ahbidle: AHB Master Idle (AHBIdle) - * Indicates that the AHB Master State Machine is in the IDLE - * condition. - * @dmareq: DMA Request Signal (DMAReq) - * Indicates that the DMA request is in progress. Used for debug. - * @txfnum: TxFIFO Number (TxFNum) - * This is the FIFO number that must be flushed using the TxFIFO - * Flush bit. This field must not be changed until the core clears - * the TxFIFO Flush bit. - * * 5'h0: Non-Periodic TxFIFO flush - * * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic - * TxFIFO flush in Host mode - * * 5'h2: Periodic TxFIFO 2 flush in Device mode - * - ... - * * 5'hF: Periodic TxFIFO 15 flush in Device mode - * * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the - * core - * @txfflsh: TxFIFO Flush (TxFFlsh) - * This bit selectively flushes a single or all transmit FIFOs, but - * cannot do so if the core is in the midst of a transaction. - * The application must only write this bit after checking that the - * core is neither writing to the TxFIFO nor reading from the - * TxFIFO. - * The application must wait until the core clears this bit before - * performing any operations. This bit takes 8 clocks (of phy_clk - * or hclk, whichever is slower) to clear. - * @rxfflsh: RxFIFO Flush (RxFFlsh) - * The application can flush the entire RxFIFO using this bit, but - * must first ensure that the core is not in the middle of a - * transaction. - * The application must only write to this bit after checking that - * the core is neither reading from the RxFIFO nor writing to the - * RxFIFO. - * The application must wait until the bit is cleared before - * performing any other operations. This bit will take 8 clocks - * (slowest of PHY or AHB clock) to clear. - * @intknqflsh: IN Token Sequence Learning Queue Flush (INTknQFlsh) - * The application writes this bit to flush the IN Token Sequence - * Learning Queue. - * @frmcntrrst: Host Frame Counter Reset (FrmCntrRst) - * The application writes this bit to reset the (micro)frame number - * counter inside the core. When the (micro)frame counter is reset, - * the subsequent SOF sent out by the core will have a - * (micro)frame number of 0. - * @hsftrst: HClk Soft Reset (HSftRst) - * The application uses this bit to flush the control logic in the - * AHB Clock domain. Only AHB Clock Domain pipelines are reset. - * * FIFOs are not flushed with this bit. - * * All state machines in the AHB clock domain are reset to the - * Idle state after terminating the transactions on the AHB, - * following the protocol. - * * CSR control bits used by the AHB clock domain state - * machines are cleared. - * * To clear this interrupt, status mask bits that control the - * interrupt status and are generated by the AHB clock domain - * state machine are cleared. - * * Because interrupt status bits are not cleared, the application - * can get the status of any core events that occurred after it set - * this bit. - * This is a self-clearing bit that the core clears after all - * necessary logic is reset in the core. This may take several - * clocks, depending on the core's current state. - * @csftrst: Core Soft Reset (CSftRst) - * Resets the hclk and phy_clock domains as follows: - * * Clears the interrupts and all the CSR registers except the - * following register bits: - * - PCGCCTL.RstPdwnModule - * - PCGCCTL.GateHclk - * - PCGCCTL.PwrClmp - * - PCGCCTL.StopPPhyLPwrClkSelclk - * - GUSBCFG.PhyLPwrClkSel - * - GUSBCFG.DDRSel - * - GUSBCFG.PHYSel - * - GUSBCFG.FSIntf - * - GUSBCFG.ULPI_UTMI_Sel - * - GUSBCFG.PHYIf - * - HCFG.FSLSPclkSel - * - DCFG.DevSpd - * * All module state machines (except the AHB Slave Unit) are - * reset to the IDLE state, and all the transmit FIFOs and the - * receive FIFO are flushed. - * * Any transactions on the AHB Master are terminated as soon - * as possible, after gracefully completing the last data phase of - * an AHB transfer. Any transactions on the USB are terminated - * immediately. - * The application can write to this bit any time it wants to reset - * the core. This is a self-clearing bit and the core clears this - * bit after all the necessary logic is reset in the core, which - * may take several clocks, depending on the current state of the - * core. Once this bit is cleared software should wait at least 3 - * PHY clocks before doing any access to the PHY domain - * (synchronization delay). Software should also should check that - * bit 31 of this register is 1 (AHB Master is IDLE) before - * starting any operation. - * Typically software reset is used during software development - * and also when you dynamically change the PHY selection bits - * in the USB configuration registers listed above. When you - * change the PHY, the corresponding clock for the PHY is - * selected and used in the PHY domain. Once a new clock is - * selected, the PHY domain has to be reset for proper operation. - */ - struct cvmx_usbcx_grstctl_s { - __BITFIELD_FIELD(u32 ahbidle : 1, - __BITFIELD_FIELD(u32 dmareq : 1, - __BITFIELD_FIELD(u32 reserved_11_29 : 19, - __BITFIELD_FIELD(u32 txfnum : 5, - __BITFIELD_FIELD(u32 txfflsh : 1, - __BITFIELD_FIELD(u32 rxfflsh : 1, - __BITFIELD_FIELD(u32 intknqflsh : 1, - __BITFIELD_FIELD(u32 frmcntrrst : 1, - __BITFIELD_FIELD(u32 hsftrst : 1, - __BITFIELD_FIELD(u32 csftrst : 1, - ;)))))))))) - } s; -}; - -/** - * cvmx_usbc#_grxfsiz - * - * Receive FIFO Size Register (GRXFSIZ) - * - * The application can program the RAM size that must be allocated to the - * RxFIFO. - */ -union cvmx_usbcx_grxfsiz { - u32 u32; - /** - * struct cvmx_usbcx_grxfsiz_s - * @rxfdep: RxFIFO Depth (RxFDep) - * This value is in terms of 32-bit words. - * * Minimum value is 16 - * * Maximum value is 32768 - */ - struct cvmx_usbcx_grxfsiz_s { - __BITFIELD_FIELD(u32 reserved_16_31 : 16, - __BITFIELD_FIELD(u32 rxfdep : 16, - ;)) - } s; -}; - -/** - * cvmx_usbc#_grxstsph - * - * Receive Status Read and Pop Register, Host Mode (GRXSTSPH) - * - * A read to the Receive Status Read and Pop register returns and additionally - * pops the top data entry out of the RxFIFO. - * This Description is only valid when the core is in Host Mode. For Device Mode - * use USBC_GRXSTSPD instead. - * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the - * same offset in the O2P USB core. The offset difference shown in this - * document is for software clarity and is actually ignored by the - * hardware. - */ -union cvmx_usbcx_grxstsph { - u32 u32; - /** - * struct cvmx_usbcx_grxstsph_s - * @pktsts: Packet Status (PktSts) - * Indicates the status of the received packet - * * 4'b0010: IN data packet received - * * 4'b0011: IN transfer completed (triggers an interrupt) - * * 4'b0101: Data toggle error (triggers an interrupt) - * * 4'b0111: Channel halted (triggers an interrupt) - * * Others: Reserved - * @dpid: Data PID (DPID) - * * 2'b00: DATA0 - * * 2'b10: DATA1 - * * 2'b01: DATA2 - * * 2'b11: MDATA - * @bcnt: Byte Count (BCnt) - * Indicates the byte count of the received IN data packet - * @chnum: Channel Number (ChNum) - * Indicates the channel number to which the current received - * packet belongs. - */ - struct cvmx_usbcx_grxstsph_s { - __BITFIELD_FIELD(u32 reserved_21_31 : 11, - __BITFIELD_FIELD(u32 pktsts : 4, - __BITFIELD_FIELD(u32 dpid : 2, - __BITFIELD_FIELD(u32 bcnt : 11, - __BITFIELD_FIELD(u32 chnum : 4, - ;))))) - } s; -}; - -/** - * cvmx_usbc#_gusbcfg - * - * Core USB Configuration Register (GUSBCFG) - * - * This register can be used to configure the core after power-on or a changing - * to Host mode or Device mode. It contains USB and USB-PHY related - * configuration parameters. The application must program this register before - * starting any transactions on either the AHB or the USB. Do not make changes - * to this register after the initial programming. - */ -union cvmx_usbcx_gusbcfg { - u32 u32; - /** - * struct cvmx_usbcx_gusbcfg_s - * @otgi2csel: UTMIFS or I2C Interface Select (OtgI2CSel) - * This bit is always 0x0. - * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel) - * Software should set this bit to 0x0. - * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In - * FS and LS modes, the PHY can usually operate on a 48-MHz - * clock to save power. - * * 1'b0: 480-MHz Internal PLL clock - * * 1'b1: 48-MHz External Clock - * In 480 MHz mode, the UTMI interface operates at either 60 or - * 30-MHz, depending upon whether 8- or 16-bit data width is - * selected. In 48-MHz mode, the UTMI interface operates at 48 - * MHz in FS mode and at either 48 or 6 MHz in LS mode - * (depending on the PHY vendor). - * This bit drives the utmi_fsls_low_power core output signal, and - * is valid only for UTMI+ PHYs. - * @usbtrdtim: USB Turnaround Time (USBTrdTim) - * Sets the turnaround time in PHY clocks. - * Specifies the response time for a MAC request to the Packet - * FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). - * This must be programmed to 0x5. - * @hnpcap: HNP-Capable (HNPCap) - * This bit is always 0x0. - * @srpcap: SRP-Capable (SRPCap) - * This bit is always 0x0. - * @ddrsel: ULPI DDR Select (DDRSel) - * Software should set this bit to 0x0. - * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial - * Software should set this bit to 0x0. - * @fsintf: Full-Speed Serial Interface Select (FSIntf) - * Software should set this bit to 0x0. - * @ulpi_utmi_sel: ULPI or UTMI+ Select (ULPI_UTMI_Sel) - * This bit is always 0x0. - * @phyif: PHY Interface (PHYIf) - * This bit is always 0x1. - * @toutcal: HS/FS Timeout Calibration (TOutCal) - * The number of PHY clocks that the application programs in this - * field is added to the high-speed/full-speed interpacket timeout - * duration in the core to account for any additional delays - * introduced by the PHY. This may be required, since the delay - * introduced by the PHY in generating the linestate condition may - * vary from one PHY to another. - * The USB standard timeout value for high-speed operation is - * 736 to 816 (inclusive) bit times. The USB standard timeout - * value for full-speed operation is 16 to 18 (inclusive) bit - * times. The application must program this field based on the - * speed of enumeration. The number of bit times added per PHY - * clock are: - * High-speed operation: - * * One 30-MHz PHY clock = 16 bit times - * * One 60-MHz PHY clock = 8 bit times - * Full-speed operation: - * * One 30-MHz PHY clock = 0.4 bit times - * * One 60-MHz PHY clock = 0.2 bit times - * * One 48-MHz PHY clock = 0.25 bit times - */ - struct cvmx_usbcx_gusbcfg_s { - __BITFIELD_FIELD(u32 reserved_17_31 : 15, - __BITFIELD_FIELD(u32 otgi2csel : 1, - __BITFIELD_FIELD(u32 phylpwrclksel : 1, - __BITFIELD_FIELD(u32 reserved_14_14 : 1, - __BITFIELD_FIELD(u32 usbtrdtim : 4, - __BITFIELD_FIELD(u32 hnpcap : 1, - __BITFIELD_FIELD(u32 srpcap : 1, - __BITFIELD_FIELD(u32 ddrsel : 1, - __BITFIELD_FIELD(u32 physel : 1, - __BITFIELD_FIELD(u32 fsintf : 1, - __BITFIELD_FIELD(u32 ulpi_utmi_sel : 1, - __BITFIELD_FIELD(u32 phyif : 1, - __BITFIELD_FIELD(u32 toutcal : 3, - ;))))))))))))) |