diff options
Diffstat (limited to 'drivers/pinctrl')
71 files changed, 9474 insertions, 1786 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 815095326e2d..d4b2f2e2ed75 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -82,6 +82,7 @@ config PINCTRL_AT91 config PINCTRL_AT91PIO4 bool "AT91 PIO4 pinctrl driver" depends on OF + depends on HAS_IOMEM depends on ARCH_AT91 || COMPILE_TEST select PINMUX select GENERIC_PINCONF @@ -374,6 +375,25 @@ config PINCTRL_OCELOT select OF_GPIO select REGMAP_MMIO +config PINCTRL_MICROCHIP_SGPIO + bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" + depends on OF + depends on HAS_IOMEM + select GPIOLIB + select GPIOLIB_IRQCHIP + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select OF_GPIO + help + Support for the serial GPIO interface used on Microsemi and + Microchip SoC's. By using a serial interface, the SIO + controller significantly extends the number of available + GPIOs with a minimum number of additional pins on the + device. The primary purpose of the SIO controller is to + connect control signals from SFP modules and to act as an + LED controller. + source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" @@ -385,6 +405,7 @@ source "drivers/pinctrl/nomadik/Kconfig" source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" +source "drivers/pinctrl/ralink/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/spear/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f53933b2ff02..5bb9bb6cc3ce 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o +obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o obj-y += actions/ @@ -59,6 +60,7 @@ obj-y += nomadik/ obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ +obj-$(CONFIG_PINCTRL_RALINK) += ralink/ obj-$(CONFIG_PINCTRL_RENESAS) += renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ diff --git a/drivers/pinctrl/actions/pinctrl-s500.c b/drivers/pinctrl/actions/pinctrl-s500.c index 38e30914af6e..ced778079b76 100644 --- a/drivers/pinctrl/actions/pinctrl-s500.c +++ b/drivers/pinctrl/actions/pinctrl-s500.c @@ -1485,7 +1485,7 @@ static PAD_PULLCTL_CONF(DNAND_D6, 2, 2, 1); static PAD_PULLCTL_CONF(DNAND_D7, 2, 2, 1); /* Pad info table */ -static struct owl_padinfo s500_padinfo[NUM_PADS] = { +static const struct owl_padinfo s500_padinfo[NUM_PADS] = { [DNAND_DQS] = PAD_INFO_PULLCTL(DNAND_DQS), [DNAND_DQSN] = PAD_INFO_PULLCTL(DNAND_DQSN), [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index d6b849552a1e..9c65d560d48f 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -286,14 +286,76 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr) { /* - * The signal type is GPIO if the signal name has "GPI" as a prefix. - * strncmp (rather than strcmp) is used to implement the prefix - * requirement. + * We need to differentiate between GPIO and non-GPIO signals to + * implement the gpio_request_enable() interface. For better or worse + * the ASPEED pinctrl driver uses the expression names to determine + * whether an expression will mux a pin for GPIO. * - * expr->signal might look like "GPIOB1" in the GPIO case. - * expr->signal might look like "GPIT0" in the GPI case. + * Generally we have the following - A GPIO such as B1 has: + * + * - expr->signal set to "GPIOB1" + * - expr->function set to "GPIOB1" + * + * Using this fact we can determine whether the provided expression is + * a GPIO expression by testing the signal name for the string prefix + * "GPIO". + * + * However, some GPIOs are input-only, and the ASPEED datasheets name + * them differently. An input-only GPIO such as T0 has: + * + * - expr->signal set to "GPIT0" + * - expr->function set to "GPIT0" + * + * It's tempting to generalise the prefix test from "GPIO" to "GPI" to + * account for both GPIOs and GPIs, but in doing so we run aground on + * another feature: + * + * Some pins in the ASPEED BMC SoCs have a "pass-through" GPIO + * function where the input state of one pin is replicated as the + * output state of another (as if they were shorted together - a mux + * configuration that is typically enabled by hardware strapping). + * This feature allows the BMC to pass e.g. power button state through + * to the host while the BMC is yet to boot, but take control of the + * button state once the BMC has booted by muxing each pin as a + * separate, pin-specific GPIO. + * + * Conceptually this pass-through mode is a form of GPIO and is named + * as such in the datasheets, e.g. "GPID0". This naming similarity + * trips us up with the simple GPI-prefixed-signal-name scheme + * discussed above, as the pass-through configuration is not what we + * want when muxing a pin as GPIO for the GPIO subsystem. + * + * On e.g. the AST2400, a pass-through function "GPID0" is grouped on + * balls A18 and D16, where we have: + * + * For ball A18: + * - expr->signal set to "GPID0IN" + * - expr->function set to "GPID0" + * + * For ball D16: + * - expr->signal set to "GPID0OUT" + * - expr->function set to "GPID0" + * + * By contrast, the pin-specific GPIO expressions for the same pins are + * as follows: + * + * For ball A18: + * - expr->signal looks like "GPIOD0" + * - expr->function looks like "GPIOD0" + * + * For ball D16: + * - expr->signal looks like "GPIOD1" + * - expr->function looks like "GPIOD1" + * + * Testing both the signal _and_ function names gives us the means + * differentiate the pass-through GPIO pinmux configuration from the + * pin-specific configuration that the GPIO subsystem is after: An + * expression is a pin-specific (non-pass-through) GPIO configuration + * if the signal prefix is "GPI" and the signal name matches the + * function name. */ - return strncmp(expr->signal, "GPI", 3) == 0; + return !strncmp(expr->signal, "GPI", 3) && + !strcmp(expr->signal, expr->function); } static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs) diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h index f86739e800c3..dba5875ff276 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.h +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h @@ -452,10 +452,11 @@ struct aspeed_sig_desc { * evaluation of the descriptors. * * @signal: The signal name for the priority level on the pin. If the signal - * type is GPIO, then the signal name must begin with the string - * "GPIO", e.g. GPIOA0, GPIOT4 etc. + * type is GPIO, then the signal name must begin with the + * prefix "GPI", e.g. GPIOA0, GPIT0 etc. * @function: The name of the function the signal participates in for the - * associated expression + * associated expression. For pin-specific GPIO, the function + * name must match the signal name. * @ndescs: The number of signal descriptors in the expression * @descs: Pointer to an array of signal descriptors that comprise the * function expression diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 3663d87f51a0..9fc4433fece4 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1602,9 +1602,11 @@ static int pinctrl_pins_show(struct seq_file *s, void *what) struct pinctrl_dev *pctldev = s->private; const struct pinctrl_ops *ops = pctldev->desc->pctlops; unsigned i, pin; +#ifdef CONFIG_GPIOLIB struct pinctrl_gpio_range *range; unsigned int gpio_num; struct gpio_chip *chip; +#endif seq_printf(s, "registered pins: %d\n", pctldev->desc->npins); diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index a1fbb3b9ae34..f294336430cc 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -24,13 +24,6 @@ config PINCTRL_IMX1 help Say Y here to enable the imx1 pinctrl driver -config PINCTRL_IMX21 - bool "i.MX21 pinctrl driver" - depends on SOC_IMX21 - select PINCTRL_IMX1_CORE - help - Say Y here to enable the i.MX21 pinctrl driver - config PINCTRL_IMX27 bool "IMX27 pinctrl driver" depends on SOC_IMX27 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index c61722565289..e476cb671037 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -4,7 +4,6 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o -obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx21.c b/drivers/pinctrl/freescale/pinctrl-imx21.c deleted file mode 100644 index 8a102275a053..000000000000 --- a/drivers/pinctrl/freescale/pinctrl-imx21.c +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// i.MX21 pinctrl driver based on imx pinmux core -// -// Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> - -#include <linux/init.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/pinctrl/pinctrl.h> - -#include "pinctrl-imx1.h" - -#define PAD_ID(port, pin) ((port) * 32 + (pin)) -#define PA 0 -#define PB 1 -#define PC 2 -#define PD 3 -#define PE 4 -#define PF 5 - -enum imx21_pads { - MX21_PAD_LSCLK = PAD_ID(PA, 5), - MX21_PAD_LD0 = PAD_ID(PA, 6), - MX21_PAD_LD1 = PAD_ID(PA, 7), - MX21_PAD_LD2 = PAD_ID(PA, 8), - MX21_PAD_LD3 = PAD_ID(PA, 9), - MX21_PAD_LD4 = PAD_ID(PA, 10), - MX21_PAD_LD5 = PAD_ID(PA, 11), - MX21_PAD_LD6 = PAD_ID(PA, 12), - MX21_PAD_LD7 = PAD_ID(PA, 13), - MX21_PAD_LD8 = PAD_ID(PA, 14), - MX21_PAD_LD9 = PAD_ID(PA, 15), - MX21_PAD_LD10 = PAD_ID(PA, 16), - MX21_PAD_LD11 = PAD_ID(PA, 17), - MX21_PAD_LD12 = PAD_ID(PA, 18), - MX21_PAD_LD13 = PAD_ID(PA, 19), - MX21_PAD_LD14 = PAD_ID(PA, 20), - MX21_PAD_LD15 = PAD_ID(PA, 21), - MX21_PAD_LD16 = PAD_ID(PA, 22), - MX21_PAD_LD17 = PAD_ID(PA, 23), - MX21_PAD_REV = PAD_ID(PA, 24), - MX21_PAD_CLS = PAD_ID(PA, 25), - MX21_PAD_PS = PAD_ID(PA, 26), - MX21_PAD_SPL_SPR = PAD_ID(PA, 27), - MX21_PAD_HSYNC = PAD_ID(PA, 28), - MX21_PAD_VSYNC = PAD_ID(PA, 29), - MX21_PAD_CONTRAST = PAD_ID(PA, 30), - MX21_PAD_OE_ACD = PAD_ID(PA, 31), - MX21_PAD_SD2_D0 = PAD_ID(PB, 4), - MX21_PAD_SD2_D1 = PAD_ID(PB, 5), - MX21_PAD_SD2_D2 = PAD_ID(PB, 6), - MX21_PAD_SD2_D3 = PAD_ID(PB, 7), - MX21_PAD_SD2_CMD = PAD_ID(PB, 8), - MX21_PAD_SD2_CLK = PAD_ID(PB, 9), - MX21_PAD_CSI_D0 = PAD_ID(PB, 10), - MX21_PAD_CSI_D1 = PAD_ID(PB, 11), - MX21_PAD_CSI_D2 = PAD_ID(PB, 12), - MX21_PAD_CSI_D3 = PAD_ID(PB, 13), - MX21_PAD_CSI_D4 = PAD_ID(PB, 14), - MX21_PAD_CSI_MCLK = PAD_ID(PB, 15), - MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16), - MX21_PAD_CSI_D5 = PAD_ID(PB, 17), - MX21_PAD_CSI_D6 = PAD_ID(PB, 18), - MX21_PAD_CSI_D7 = PAD_ID(PB, 19), - MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20), - MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21), - MX21_PAD_USB_BYP = PAD_ID(PB, 22), - MX21_PAD_USB_PWR = PAD_ID(PB, 23), - MX21_PAD_USB_OC = PAD_ID(PB, 24), - MX21_PAD_USBH_ON = PAD_ID(PB, 25), - MX21_PAD_USBH1_FS = PAD_ID(PB, 26), - MX21_PAD_USBH1_OE = PAD_ID(PB, 27), - MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28), - MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29), - MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30), - MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31), - MX21_PAD_USBG_SDA = PAD_ID(PC, 5), - MX21_PAD_USBG_SCL = PAD_ID(PC, 6), - MX21_PAD_USBG_ON = PAD_ID(PC, 7), - MX21_PAD_USBG_FS = PAD_ID(PC, 8), - MX21_PAD_USBG_OE = PAD_ID(PC, 9), - MX21_PAD_USBG_TXDM = PAD_ID(PC, 10), - MX21_PAD_USBG_TXDP = PAD_ID(PC, 11), - MX21_PAD_USBG_RXDM = PAD_ID(PC, 12), - MX21_PAD_USBG_RXDP = PAD_ID(PC, 13), - MX21_PAD_TOUT = PAD_ID(PC, 14), - MX21_PAD_TIN = PAD_ID(PC, 15), - MX21_PAD_SAP_FS = PAD_ID(PC, 16), - MX21_PAD_SAP_RXD = PAD_ID(PC, 17), - MX21_PAD_SAP_TXD = PAD_ID(PC, 18), - MX21_PAD_SAP_CLK = PAD_ID(PC, 19), - MX21_PAD_SSI1_FS = PAD_ID(PC, 20), - MX21_PAD_SSI1_RXD = PAD_ID(PC, 21), - MX21_PAD_SSI1_TXD = PAD_ID(PC, 22), - MX21_PAD_SSI1_CLK = PAD_ID(PC, 23), - MX21_PAD_SSI2_FS = PAD_ID(PC, 24), - MX21_PAD_SSI2_RXD = PAD_ID(PC, 25), - MX21_PAD_SSI2_TXD = PAD_ID(PC, 26), - MX21_PAD_SSI2_CLK = PAD_ID(PC, 27), - MX21_PAD_SSI3_FS = PAD_ID(PC, 28), - MX21_PAD_SSI3_RXD = PAD_ID(PC, 29), - MX21_PAD_SSI3_TXD = PAD_ID(PC, 30), - MX21_PAD_SSI3_CLK = PAD_ID(PC, 31), - MX21_PAD_I2C_DATA = PAD_ID(PD, 17), - MX21_PAD_I2C_CLK = PAD_ID(PD, 18), - MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19), - MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20), - MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21), - MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22), - MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23), - MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24), - MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25), - MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26), - MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27), - MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28), - MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29), - MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30), - MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31), - MX21_PAD_TEST_WB2 = PAD_ID(PE, 0), - MX21_PAD_TEST_WB1 = PAD_ID(PE, 1), - MX21_PAD_TEST_WB0 = PAD_ID(PE, 2), - MX21_PAD_UART2_CTS = PAD_ID(PE, 3), - MX21_PAD_UART2_RTS = PAD_ID(PE, 4), - MX21_PAD_PWMO = PAD_ID(PE, 5), - MX21_PAD_UART2_TXD = PAD_ID(PE, 6), - MX21_PAD_UART2_RXD = PAD_ID(PE, 7), - MX21_PAD_UART3_TXD = PAD_ID(PE, 8), - MX21_PAD_UART3_RXD = PAD_ID(PE, 9), - MX21_PAD_UART3_CTS = PAD_ID(PE, 10), - MX21_PAD_UART3_RTS = PAD_ID(PE, 11), - MX21_PAD_UART1_TXD = PAD_ID(PE, 12), - MX21_PAD_UART1_RXD = PAD_ID(PE, 13), - MX21_PAD_UART1_CTS = PAD_ID(PE, 14), - MX21_PAD_UART1_RTS = PAD_ID(PE, 15), - MX21_PAD_RTCK = PAD_ID(PE, 16), - MX21_PAD_RESET_OUT = PAD_ID(PE, 17), - MX21_PAD_SD1_D0 = PAD_ID(PE, 18), - MX21_PAD_SD1_D1 = PAD_ID(PE, 19), - MX21_PAD_SD1_D2 = PAD_ID(PE, 20), - MX21_PAD_SD1_D3 = PAD_ID(PE, 21), - MX21_PAD_SD1_CMD = PAD_ID(PE, 22), - MX21_PAD_SD1_CLK = PAD_ID(PE, 23), - MX21_PAD_NFRB = PAD_ID(PF, 0), - MX21_PAD_NFCE = PAD_ID(PF, 1), - MX21_PAD_NFWP = PAD_ID(PF, 2), - MX21_PAD_NFCLE = PAD_ID(PF, 3), - MX21_PAD_NFALE = PAD_ID(PF, 4), - MX21_PAD_NFRE = PAD_ID(PF, 5), - MX21_PAD_NFWE = PAD_ID(PF, 6), - MX21_PAD_NFIO0 = PAD_ID(PF, 7), - MX21_PAD_NFIO1 = PAD_ID(PF, 8), - MX21_PAD_NFIO2 = PAD_ID(PF, 9), - MX21_PAD_NFIO3 = PAD_ID(PF, 10), - MX21_PAD_NFIO4 = PAD_ID(PF, 11), - MX21_PAD_NFIO5 = PAD_ID(PF, 12), - MX21_PAD_NFIO6 = PAD_ID(PF, 13), - MX21_PAD_NFIO7 = PAD_ID(PF, 14), - MX21_PAD_CLKO = PAD_ID(PF, 15), - MX21_PAD_RESERVED = PAD_ID(PF, 16), - MX21_PAD_CS4 = PAD_ID(PF, 21), - MX21_PAD_CS5 = PAD_ID(PF, 22), -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX21_PAD_LSCLK), - IMX_PINCTRL_PIN(MX21_PAD_LD0), - IMX_PINCTRL_PIN(MX21_PAD_LD1), - IMX_PINCTRL_PIN(MX21_PAD_LD2), - IMX_PINCTRL_PIN(MX21_PAD_LD3), - IMX_PINCTRL_PIN(MX21_PAD_LD4), - IMX_PINCTRL_PIN(MX21_PAD_LD5), - IMX_PINCTRL_PIN(MX21_PAD_LD6), - IMX_PINCTRL_PIN(MX21_PAD_LD7), - IMX_PINCTRL_PIN(MX21_PAD_LD8), - IMX_PINCTRL_PIN(MX21_PAD_LD9), - IMX_PINCTRL_PIN(MX21_PAD_LD10), - IMX_PINCTRL_PIN(MX21_PAD_LD11), - IMX_PINCTRL_PIN(MX21_PAD_LD12), - IMX_PINCTRL_PIN(MX21_PAD_LD13), - IMX_PINCTRL_PIN(MX21_PAD_LD14), - IMX_PINCTRL_PIN(MX21_PAD_LD15), - IMX_PINCTRL_PIN(MX21_PAD_LD16), - IMX_PINCTRL_PIN(MX21_PAD_LD17), - IMX_PINCTRL_PIN(MX21_PAD_REV), - IMX_PINCTRL_PIN(MX21_PAD_CLS), - IMX_PINCTRL_PIN(MX21_PAD_PS), - IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR), - IMX_PINCTRL_PIN(MX21_PAD_HSYNC), - IMX_PINCTRL_PIN(MX21_PAD_VSYNC), - IMX_PINCTRL_PIN(MX21_PAD_CONTRAST), - IMX_PINCTRL_PIN(MX21_PAD_OE_ACD), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D0), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D1), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D2), - IMX_PINCTRL_PIN(MX21_PAD_SD2_D3), - IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D0), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D1), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D2), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D3), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D4), - IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK), - IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D5), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D6), - IMX_PINCTRL_PIN(MX21_PAD_CSI_D7), - IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC), - IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC), - IMX_PINCTRL_PIN(MX21_PAD_USB_BYP), - IMX_PINCTRL_PIN(MX21_PAD_USB_PWR), - IMX_PINCTRL_PIN(MX21_PAD_USB_OC), - IMX_PINCTRL_PIN(MX21_PAD_USBH_ON), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP), - IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA), - IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL), - IMX_PINCTRL_PIN(MX21_PAD_USBG_ON), - IMX_PINCTRL_PIN(MX21_PAD_USBG_FS), - IMX_PINCTRL_PIN(MX21_PAD_USBG_OE), - IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP), - IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM), - IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP), - IMX_PINCTRL_PIN(MX21_PAD_TOUT), - IMX_PINCTRL_PIN(MX21_PAD_TIN), - IMX_PINCTRL_PIN(MX21_PAD_SAP_FS), - IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD), - IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK),< |