diff options
Diffstat (limited to 'drivers/net/wireless/ipw2200.c')
| -rw-r--r-- | drivers/net/wireless/ipw2200.c | 7348 |
1 files changed, 7348 insertions, 0 deletions
diff --git a/drivers/net/wireless/ipw2200.c b/drivers/net/wireless/ipw2200.c new file mode 100644 index 000000000000..69733465354b --- /dev/null +++ b/drivers/net/wireless/ipw2200.c @@ -0,0 +1,7348 @@ +/****************************************************************************** + + Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved. + + 802.11 status code portion of this file from ethereal-0.10.6: + Copyright 2000, Axis Communications AB + Ethereal - Network traffic analyzer + By Gerald Combs <gerald@ethereal.com> + Copyright 1998 Gerald Combs + + This program is free software; you can redistribute it and/or modify it + under the terms of version 2 of the GNU General Public License as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program; if not, write to the Free Software Foundation, Inc., 59 + Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + The full GNU General Public License is included in this distribution in the + file called LICENSE. + + Contact Information: + James P. Ketrenos <ipw2100-admin@linux.intel.com> + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +******************************************************************************/ + +#include "ipw2200.h" + +#define IPW2200_VERSION "1.0.0" +#define DRV_DESCRIPTION "Intel(R) PRO/Wireless 2200/2915 Network Driver" +#define DRV_COPYRIGHT "Copyright(c) 2003-2004 Intel Corporation" +#define DRV_VERSION IPW2200_VERSION + +MODULE_DESCRIPTION(DRV_DESCRIPTION); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR(DRV_COPYRIGHT); +MODULE_LICENSE("GPL"); + +static int debug = 0; +static int channel = 0; +static char *ifname; +static int mode = 0; + +static u32 ipw_debug_level; +static int associate = 1; +static int auto_create = 1; +static int disable = 0; +static const char ipw_modes[] = { + 'a', 'b', 'g', '?' +}; + +static void ipw_rx(struct ipw_priv *priv); +static int ipw_queue_tx_reclaim(struct ipw_priv *priv, + struct clx2_tx_queue *txq, int qindex); +static int ipw_queue_reset(struct ipw_priv *priv); + +static int ipw_queue_tx_hcmd(struct ipw_priv *priv, int hcmd, void *buf, + int len, int sync); + +static void ipw_tx_queue_free(struct ipw_priv *); + +static struct ipw_rx_queue *ipw_rx_queue_alloc(struct ipw_priv *); +static void ipw_rx_queue_free(struct ipw_priv *, struct ipw_rx_queue *); +static void ipw_rx_queue_replenish(void *); + +static int ipw_up(struct ipw_priv *); +static void ipw_down(struct ipw_priv *); +static int ipw_config(struct ipw_priv *); +static int init_supported_rates(struct ipw_priv *priv, struct ipw_supported_rates *prates); + +static u8 band_b_active_channel[MAX_B_CHANNELS] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0 +}; +static u8 band_a_active_channel[MAX_A_CHANNELS] = { + 36, 40, 44, 48, 149, 153, 157, 161, 165, 52, 56, 60, 64, 0 +}; + +static int is_valid_channel(int mode_mask, int channel) +{ + int i; + + if (!channel) + return 0; + + if (mode_mask & IEEE_A) + for (i = 0; i < MAX_A_CHANNELS; i++) + if (band_a_active_channel[i] == channel) + return IEEE_A; + + if (mode_mask & (IEEE_B | IEEE_G)) + for (i = 0; i < MAX_B_CHANNELS; i++) + if (band_b_active_channel[i] == channel) + return mode_mask & (IEEE_B | IEEE_G); + + return 0; +} + +static char *snprint_line(char *buf, size_t count, + const u8 *data, u32 len, u32 ofs) +{ + int out, i, j, l; + char c; + + out = snprintf(buf, count, "%08X", ofs); + + for (l = 0, i = 0; i < 2; i++) { + out += snprintf(buf + out, count - out, " "); + for (j = 0; j < 8 && l < len; j++, l++) + out += snprintf(buf + out, count - out, "%02X ", + data[(i * 8 + j)]); + for (; j < 8; j++) + out += snprintf(buf + out, count - out, " "); + } + + out += snprintf(buf + out, count - out, " "); + for (l = 0, i = 0; i < 2; i++) { + out += snprintf(buf + out, count - out, " "); + for (j = 0; j < 8 && l < len; j++, l++) { + c = data[(i * 8 + j)]; + if (!isascii(c) || !isprint(c)) + c = '.'; + + out += snprintf(buf + out, count - out, "%c", c); + } + + for (; j < 8; j++) + out += snprintf(buf + out, count - out, " "); + } + + return buf; +} + +static void printk_buf(int level, const u8 *data, u32 len) +{ + char line[81]; + u32 ofs = 0; + if (!(ipw_debug_level & level)) + return; + + while (len) { + printk(KERN_DEBUG "%s\n", + snprint_line(line, sizeof(line), &data[ofs], + min(len, 16U), ofs)); + ofs += 16; + len -= min(len, 16U); + } +} + +static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg); +#define ipw_read_reg32(a, b) _ipw_read_reg32(a, b) + +static u8 _ipw_read_reg8(struct ipw_priv *ipw, u32 reg); +#define ipw_read_reg8(a, b) _ipw_read_reg8(a, b) + +static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value); +static inline void ipw_write_reg8(struct ipw_priv *a, u32 b, u8 c) +{ + IPW_DEBUG_IO("%s %d: write_indirect8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(b), (u32)(c)); + _ipw_write_reg8(a, b, c); +} + +static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value); +static inline void ipw_write_reg16(struct ipw_priv *a, u32 b, u16 c) +{ + IPW_DEBUG_IO("%s %d: write_indirect16(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(b), (u32)(c)); + _ipw_write_reg16(a, b, c); +} + +static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value); +static inline void ipw_write_reg32(struct ipw_priv *a, u32 b, u32 c) +{ + IPW_DEBUG_IO("%s %d: write_indirect32(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(b), (u32)(c)); + _ipw_write_reg32(a, b, c); +} + +#define _ipw_write8(ipw, ofs, val) writeb((val), (ipw)->hw_base + (ofs)) +#define ipw_write8(ipw, ofs, val) \ + IPW_DEBUG_IO("%s %d: write_direct8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \ + _ipw_write8(ipw, ofs, val) + +#define _ipw_write16(ipw, ofs, val) writew((val), (ipw)->hw_base + (ofs)) +#define ipw_write16(ipw, ofs, val) \ + IPW_DEBUG_IO("%s %d: write_direct16(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \ + _ipw_write16(ipw, ofs, val) + +#define _ipw_write32(ipw, ofs, val) writel((val), (ipw)->hw_base + (ofs)) +#define ipw_write32(ipw, ofs, val) \ + IPW_DEBUG_IO("%s %d: write_direct32(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \ + _ipw_write32(ipw, ofs, val) + +#define _ipw_read8(ipw, ofs) readb((ipw)->hw_base + (ofs)) +static inline u8 __ipw_read8(char *f, u32 l, struct ipw_priv *ipw, u32 ofs) { + IPW_DEBUG_IO("%s %d: read_direct8(0x%08X)\n", f, l, (u32)(ofs)); + return _ipw_read8(ipw, ofs); +} +#define ipw_read8(ipw, ofs) __ipw_read8(__FILE__, __LINE__, ipw, ofs) + +#define _ipw_read16(ipw, ofs) readw((ipw)->hw_base + (ofs)) +static inline u16 __ipw_read16(char *f, u32 l, struct ipw_priv *ipw, u32 ofs) { + IPW_DEBUG_IO("%s %d: read_direct16(0x%08X)\n", f, l, (u32)(ofs)); + return _ipw_read16(ipw, ofs); +} +#define ipw_read16(ipw, ofs) __ipw_read16(__FILE__, __LINE__, ipw, ofs) + +#define _ipw_read32(ipw, ofs) readl((ipw)->hw_base + (ofs)) +static inline u32 __ipw_read32(char *f, u32 l, struct ipw_priv *ipw, u32 ofs) { + IPW_DEBUG_IO("%s %d: read_direct32(0x%08X)\n", f, l, (u32)(ofs)); + return _ipw_read32(ipw, ofs); +} +#define ipw_read32(ipw, ofs) __ipw_read32(__FILE__, __LINE__, ipw, ofs) + +static void _ipw_read_indirect(struct ipw_priv *, u32, u8 *, int); +#define ipw_read_indirect(a, b, c, d) \ + IPW_DEBUG_IO("%s %d: read_inddirect(0x%08X) %d bytes\n", __FILE__, __LINE__, (u32)(b), d); \ + _ipw_read_indirect(a, b, c, d) + +static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 *data, int num); +#define ipw_write_indirect(a, b, c, d) \ + IPW_DEBUG_IO("%s %d: write_indirect(0x%08X) %d bytes\n", __FILE__, __LINE__, (u32)(b), d); \ + _ipw_write_indirect(a, b, c, d) + +/* indirect write s */ +static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, + u32 value) +{ + IPW_DEBUG_IO(" %p : reg = 0x%8X : value = 0x%8X\n", + priv, reg, value); + _ipw_write32(priv, CX2_INDIRECT_ADDR, reg); + _ipw_write32(priv, CX2_INDIRECT_DATA, value); +} + + +static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value) +{ + IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value); + _ipw_write32(priv, CX2_INDIRECT_ADDR, reg & CX2_INDIRECT_ADDR_MASK); + _ipw_write8(priv, CX2_INDIRECT_DATA, value); + IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", + (unsigned)(priv->hw_base + CX2_INDIRECT_DATA), + value); +} + +static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, + u16 value) +{ + IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value); + _ipw_write32(priv, CX2_INDIRECT_ADDR, reg & CX2_INDIRECT_ADDR_MASK); + _ipw_write16(priv, CX2_INDIRECT_DATA, value); +} + +/* indirect read s */ + +static u8 _ipw_read_reg8(struct ipw_priv *priv, u32 reg) +{ + u32 word; + _ipw_write32(priv, CX2_INDIRECT_ADDR, reg & CX2_INDIRECT_ADDR_MASK); + IPW_DEBUG_IO(" reg = 0x%8X : \n", reg); + word = _ipw_read32(priv, CX2_INDIRECT_DATA); + return (word >> ((reg & 0x3)*8)) & 0xff; +} + +static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg) +{ + u32 value; + + IPW_DEBUG_IO("%p : reg = 0x%08x\n", priv, reg); + + _ipw_write32(priv, CX2_INDIRECT_ADDR, reg); + value = _ipw_read32(priv, CX2_INDIRECT_DATA); + IPW_DEBUG_IO(" reg = 0x%4X : value = 0x%4x \n", reg, value); + return value; +} + +/* iterative/auto-increment 32 bit reads and writes */ +static void _ipw_read_indirect(struct ipw_priv *priv, u32 addr, u8 * buf, + int num) +{ + u32 aligned_addr = addr & CX2_INDIRECT_ADDR_MASK; + u32 dif_len = addr - aligned_addr; + u32 aligned_len; + u32 i; + + IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num); + + /* Read the first nibble byte by byte */ + if (unlikely(dif_len)) { + /* Start reading at aligned_addr + dif_len */ + _ipw_write32(priv, CX2_INDIRECT_ADDR, aligned_addr); + for (i = dif_len; i < 4; i++, buf++) + *buf = _ipw_read8(priv, CX2_INDIRECT_DATA + i); + num -= dif_len; + aligned_addr += 4; + } + + /* Read DWs through autoinc register */ + _ipw_write32(priv, CX2_AUTOINC_ADDR, aligned_addr); + aligned_len = num & CX2_INDIRECT_ADDR_MASK; + for (i = 0; i < aligned_len; i += 4, buf += 4, aligned_addr += 4) + *(u32*)buf = ipw_read32(priv, CX2_AUTOINC_DATA); + + /* Copy the last nibble */ + dif_len = num - aligned_len; + _ipw_write32(priv, CX2_INDIRECT_ADDR, aligned_addr); + for (i = 0; i < dif_len; i++, buf++) + *buf = ipw_read8(priv, CX2_INDIRECT_DATA + i); +} + +static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 *buf, + int num) +{ + u32 aligned_addr = addr & CX2_INDIRECT_ADDR_MASK; + u32 dif_len = addr - aligned_addr; + u32 aligned_len; + u32 i; + + IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num); + + /* Write the first nibble byte by byte */ + if (unlikely(dif_len)) { + /* Start writing at aligned_addr + dif_len */ + _ipw_write32(priv, CX2_INDIRECT_ADDR, aligned_addr); + for (i = dif_len; i < 4; i++, buf++) + _ipw_write8(priv, CX2_INDIRECT_DATA + i, *buf); + num -= dif_len; + aligned_addr += 4; + } + + /* Write DWs through autoinc register */ + _ipw_write32(priv, CX2_AUTOINC_ADDR, aligned_addr); + aligned_len = num & CX2_INDIRECT_ADDR_MASK; + for (i = 0; i < aligned_len; i += 4, buf += 4, aligned_addr += 4) + _ipw_write32(priv, CX2_AUTOINC_DATA, *(u32*)buf); + + /* Copy the last nibble */ + dif_len = num - aligned_len; + _ipw_write32(priv, CX2_INDIRECT_ADDR, aligned_addr); + for (i = 0; i < dif_len; i++, buf++) + _ipw_write8(priv, CX2_INDIRECT_DATA + i, *buf); +} + +static void ipw_write_direct(struct ipw_priv *priv, u32 addr, void *buf, + int num) +{ + memcpy_toio((priv->hw_base + addr), buf, num); +} + +static inline void ipw_set_bit(struct ipw_priv *priv, u32 reg, u32 mask) +{ + ipw_write32(priv, reg, ipw_read32(priv, reg) | mask); +} + +static inline void ipw_clear_bit(struct ipw_priv *priv, u32 reg, u32 mask) +{ + ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask); +} + +static inline void ipw_enable_interrupts(struct ipw_priv *priv) +{ + if (priv->status & STATUS_INT_ENABLED) + return; + priv->status |= STATUS_INT_ENABLED; + ipw_write32(priv, CX2_INTA_MASK_R, CX2_INTA_MASK_ALL); +} + +static inline void ipw_disable_interrupts(struct ipw_priv *priv) +{ + if (!(priv->status & STATUS_INT_ENABLED)) + return; + priv->status &= ~STATUS_INT_ENABLED; + ipw_write32(priv, CX2_INTA_MASK_R, ~CX2_INTA_MASK_ALL); +} + +static char *ipw_error_desc(u32 val) +{ + switch (val) { + case IPW_FW_ERROR_OK: + return "ERROR_OK"; + case IPW_FW_ERROR_FAIL: + return "ERROR_FAIL"; + case IPW_FW_ERROR_MEMORY_UNDERFLOW: + return "MEMORY_UNDERFLOW"; + case IPW_FW_ERROR_MEMORY_OVERFLOW: + return "MEMORY_OVERFLOW"; + case IPW_FW_ERROR_BAD_PARAM: + return "ERROR_BAD_PARAM"; + case IPW_FW_ERROR_BAD_CHECKSUM: + return "ERROR_BAD_CHECKSUM"; + case IPW_FW_ERROR_NMI_INTERRUPT: + return "ERROR_NMI_INTERRUPT"; + case IPW_FW_ERROR_BAD_DATABASE: + return "ERROR_BAD_DATABASE"; + case IPW_FW_ERROR_ALLOC_FAIL: + return "ERROR_ALLOC_FAIL"; + case IPW_FW_ERROR_DMA_UNDERRUN: + return "ERROR_DMA_UNDERRUN"; + case IPW_FW_ERROR_DMA_STATUS: + return "ERROR_DMA_STATUS"; + case IPW_FW_ERROR_DINOSTATUS_ERROR: + return "ERROR_DINOSTATUS_ERROR"; + case IPW_FW_ERROR_EEPROMSTATUS_ERROR: + return "ERROR_EEPROMSTATUS_ERROR"; + case IPW_FW_ERROR_SYSASSERT: + return "ERROR_SYSASSERT"; + case IPW_FW_ERROR_FATAL_ERROR: + return "ERROR_FATALSTATUS_ERROR"; + default: + return "UNKNOWNSTATUS_ERROR"; + } +} + +static void ipw_dump_nic_error_log(struct ipw_priv *priv) +{ + u32 desc, time, blink1, blink2, ilink1, ilink2, idata, i, count, base; + + base = ipw_read32(priv, IPWSTATUS_ERROR_LOG); + count = ipw_read_reg32(priv, base); + + if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { + IPW_ERROR("Start IPW Error Log Dump:\n"); + IPW_ERROR("Status: 0x%08X, Config: %08X\n", + priv->status, priv->config); + } + + for (i = ERROR_START_OFFSET; + i <= count * ERROR_ELEM_SIZE; + i += ERROR_ELEM_SIZE) { + desc = ipw_read_reg32(priv, base + i); + time = ipw_read_reg32(priv, base + i + 1*sizeof(u32)); + blink1 = ipw_read_reg32(priv, base + i + 2*sizeof(u32)); + blink2 = ipw_read_reg32(priv, base + i + 3*sizeof(u32)); + ilink1 = ipw_read_reg32(priv, base + i + 4*sizeof(u32)); + ilink2 = ipw_read_reg32(priv, base + i + 5*sizeof(u32)); + idata = ipw_read_reg32(priv, base + i + 6*sizeof(u32)); + + IPW_ERROR( + "%s %i 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", + ipw_error_desc(desc), time, blink1, blink2, + ilink1, ilink2, idata); + } +} + +static void ipw_dump_nic_event_log(struct ipw_priv *priv) +{ + u32 ev, time, data, i, count, base; + + base = ipw_read32(priv, IPW_EVENT_LOG); + count = ipw_read_reg32(priv, base); + + if (EVENT_START_OFFSET <= count * EVENT_ELEM_SIZE) + IPW_ERROR("Start IPW Event Log Dump:\n"); + + for (i = EVENT_START_OFFSET; + i <= count * EVENT_ELEM_SIZE; + i += EVENT_ELEM_SIZE) { + ev = ipw_read_reg32(priv, base + i); + time = ipw_read_reg32(priv, base + i + 1*sizeof(u32)); + data = ipw_read_reg32(priv, base + i + 2*sizeof(u32)); + +#ifdef CONFIG_IPW_DEBUG + IPW_ERROR("%i\t0x%08x\t%i\n", time, data, ev); +#endif + } +} + +static int ipw_get_ordinal(struct ipw_priv *priv, u32 ord, void *val, + u32 *len) +{ + u32 addr, field_info, field_len, field_count, total_len; + + IPW_DEBUG_ORD("ordinal = %i\n", ord); + + if (!priv || !val || !len) { + IPW_DEBUG_ORD("Invalid argument\n"); + return -EINVAL; + } + + /* verify device ordinal tables have been initialized */ + if (!priv->table0_addr || !priv->table1_addr || !priv->table2_addr) { + IPW_DEBUG_ORD("Access ordinals before initialization\n"); + return -EINVAL; + } + + switch (IPW_ORD_TABLE_ID_MASK & ord) { + case IPW_ORD_TABLE_0_MASK: + /* + * TABLE 0: Direct access to a table of 32 bit values + * + * This is a very simple table with the data directly + * read from the table + */ + + /* remove the table id from the ordinal */ + ord &= IPW_ORD_TABLE_VALUE_MASK; + + /* boundary check */ + if (ord > priv->table0_len) { + IPW_DEBUG_ORD("ordinal value (%i) longer then " + "max (%i)\n", ord, priv->table0_len); + return -EINVAL; + } + + /* verify we have enough room to store the value */ + if (*len < sizeof(u32)) { + IPW_DEBUG_ORD("ordinal buffer length too small, " + "need %d\n", sizeof(u32)); + return -EINVAL; + } + + IPW_DEBUG_ORD("Reading TABLE0[%i] from offset 0x%08x\n", + ord, priv->table0_addr + (ord << 2)); + + *len = sizeof(u32); + ord <<= 2; + *((u32 *)val) = ipw_read32(priv, priv->table0_addr + ord); + break; + + case IPW_ORD_TABLE_1_MASK: + /* + * TABLE 1: Indirect access to a table of 32 bit values + * + * This is a fairly large table of u32 values each + * representing starting addr for the data (which is + * also a u32) + */ + + /* remove the table id from the ordinal */ + ord &= IPW_ORD_TABLE_VALUE_MASK; + + /* boundary check */ + if (ord > priv->table1_len) { + IPW_DEBUG_ORD("ordinal value too long\n"); + return -EINVAL; + } + + /* verify we have enough room to store the value */ + if (*len < sizeof(u32)) { + IPW_DEBUG_ORD("ordinal buffer length too small, " + "need %d\n", sizeof(u32)); + return -EINVAL; + } + + *((u32 *)val) = ipw_read_reg32(priv, (priv->table1_addr + (ord << 2))); + *len = sizeof(u32); + break; + + case IPW_ORD_TABLE_2_MASK: + /* + * TABLE 2: Indirect access to a table of variable sized values + * + * This table consist of six values, each containing + * - dword containing the starting offset of the data + * - dword containing the lengh in the first 16bits + * and the count in the second 16bits + */ + + /* remove the table id from the ordinal */ + ord &= IPW_ORD_TABLE_VALUE_MASK; + + /* boundary check */ + if (ord > priv->table2_len) { + IPW_DEBUG_ORD("ordinal value too long\n"); + return -EINVAL; + } + + /* get the address of statistic */ + addr = ipw_read_reg32(priv, priv->table2_addr + (ord << 3)); + + /* get the second DW of statistics ; + * two 16-bit words - first is length, second is count */ + field_info = ipw_read_reg32(priv, priv->table2_addr + (ord << 3) + sizeof(u32)); + + /* get each entry length */ + field_len = *((u16 *)&field_info); + + /* get number of entries */ + field_count = *(((u16 *)&field_info) + 1); + + /* abort if not enought memory */ + total_len = field_len * field_count; + if (total_len > *len) { + *len = total_len; + return -EINVAL; + } + + *len = total_len; + if (!total_len) + return 0; + + IPW_DEBUG_ORD("addr = 0x%08x, total_len = %i, " + "field_info = 0x%08x\n", + addr, total_len, field_info); + ipw_read_indirect(priv, addr, val, total_len); + break; + + default: + IPW_DEBUG_ORD("Invalid ordinal!\n"); + return -EINVAL; + + } + + + return 0; +} + +static void ipw_init_ordinals(struct ipw_priv *priv) +{ + priv->table0_addr = IPW_ORDINALS_TABLE_LOWER; + priv->table0_len = ipw_read32(priv, priv->table0_addr); + + IPW_DEBUG_ORD("table 0 offset at 0x%08x, len = %i\n", + priv->table0_addr, priv->table0_len); + + priv->table1_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_1); + priv->table1_len = ipw_read_reg32(priv, priv->table1_addr); + + IPW_DEBUG_ORD("table 1 offset at 0x%08x, len = %i\n", + priv->table1_addr, priv->table1_len); + + priv->table2_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_2); + priv->table2_len = ipw_read_reg32(priv, priv->table2_addr); + priv->table2_len &= 0x0000ffff; /* use first two bytes */ + + IPW_DEBUG_ORD("table 2 offset at 0x%08x, len = %i\n", + priv->table2_addr, priv->table2_len); + +} + +/* + * The following adds a new attribute to the sysfs representation + * of this device driver (i.e. a new file in /sys/bus/pci/drivers/ipw/) + * used for controling the debug level. + * + * See the level definitions in ipw for details. + */ +static ssize_t show_debug_level(struct device_driver *d, char *buf) +{ + return sprintf(buf, "0x%08X\n", ipw_debug_level); +} +static ssize_t store_debug_level(struct device_driver *d, const char *buf, + size_t count) +{ + char *p = (char *)buf; + u32 val; + + if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') { + p++; + if (p[0] == 'x' || p[0] == 'X') + p++; + val = simple_strtoul(p, &p, 16); + } else + val = simple_strtoul(p, &p, 10); + if (p == buf) + printk(KERN_INFO DRV_NAME + ": %s is not in hex or decimal form.\n", buf); + else + ipw_debug_level = val; + + return strnlen(buf, count); +} + +static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO, + show_debug_level, store_debug_level); + +static ssize_t show_status(struct device *d, char *buf) +{ + struct ipw_priv *p = (struct ipw_priv *)d->driver_data; + return sprintf(buf, "0x%08x\n", (int)p->status); +} +static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); + +static ssize_t show_cfg(struct device *d, char *buf) +{ + struct ipw_priv *p = (struct ipw_priv *)d->driver_data; + return sprintf(buf, "0x%08x\n", (int)p->config); +} +static DEVICE_ATTR(cfg, S_IRUGO, show_cfg, NULL); + +static ssize_t show_nic_type(struct device *d, char *buf) +{ + struct ipw_priv *p = (struct ipw_priv *)d->driver_data; + u8 type = p->eeprom[EEPROM_NIC_TYPE]; + + switch (type) { + case EEPROM_NIC_TYPE_STANDARD: + return sprintf(buf, "STANDARD\n"); + case EEPROM_NIC_TYPE_DELL: + return sprintf(buf, "DELL\n"); + case EEPROM_NIC_TYPE_FUJITSU: + return sprintf(buf, "FUJITSU\n"); + case EEPROM_NIC_TYPE_IBM: + return sprintf(buf, "IBM\n"); + case EEPROM_NIC_TYPE_HP: + return sprintf(buf, "HP\n"); + } + + return sprintf(buf, "UNKNOWN\n"); +} +static DEVICE_ATTR(nic_type, S_IRUGO, show_nic_type, NULL); + +static ssize_t dump_error_log(struct device *d, const char *buf, + size_t count) +{ + char *p = (char *)buf; + + if (p[0] == '1') + ipw_dump_nic_error_log((struct ipw_priv*)d->driver_data); + + return strnlen(buf, count); +} +static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); + +static ssize_t dump_event_log(struct device *d, const char *buf, + size_t count) +{ + char *p = (char *)buf; + + if (p[0] == '1') + ipw_dump_nic_event_log((struct ipw_priv*)d->driver_data); + + return strnlen(buf, count); +} +static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); + +static ssize_t show_ucode_version(struct device *d, char *buf) +{ + u32 len = sizeof(u32), tmp = 0; + struct ipw_priv *p = (struct ipw_priv*)d->driver_data; + + if(ipw_get_ordinal(p, IPW_ORD_STAT_UCODE_VERSION, &tmp, &len)) + return 0; + + return sprintf(buf, "0x%08x\n", tmp); +} +static DEVICE_ATTR(ucode_version, S_IWUSR|S_IRUGO, show_ucode_version, NULL); + +static ssize_t show_rtc(struct device *d, char *buf) +{ + u32 len = sizeof(u32), tmp = 0; + struct ipw_priv *p = (struct ipw_priv*)d->driver_data; + + if(ipw_get_ordinal(p, IPW_ORD_STAT_RTC, &tmp, &len)) + return 0; + + return sprintf(buf, "0x%08x\n", tmp); +} +static DEVICE_ATTR(rtc, S_IWUSR|S_IRUGO, show_rtc, NULL); + +/* + * Add a device attribute to view/control the delay between eeprom + * operations. + */ +static ssize_t show_eeprom_delay(struct device *d, char *buf) +{ + int n = ((struct ipw_priv*)d->driver_data)->eeprom_delay; + return sprintf(buf, "%i\n", n); +} +static ssize_t store_eeprom_delay(struct device *d, const char *buf, + size_t count) +{ + struct ipw_priv *p = (struct ipw_priv*)d->driver_data; + sscanf(buf, "%i", &p->eeprom_delay); + return strnlen(buf, count); +} +static DEVICE_ATTR(eeprom_delay, S_IWUSR|S_IRUGO, + show_eeprom_delay,store_eeprom_delay); + +static ssize_t show_command_event_reg(struct device *d, char *buf) +{ + u32 reg = 0; + struct ipw_priv *p = (struct ipw_priv *)d->driver_data; + + reg = ipw_read_reg32(p, CX2_INTERNAL_CMD_EVENT); + return sprintf(buf, "0x%08x\n", reg); +} +static ssize_t store_command_event_reg(struct device *d, + const char *buf, + size_t count) +{ + u32 reg; + struct ipw_priv *p = (struct ipw_priv *)d->driver_data; + + sscanf(buf, "%x", ®); + ipw_write_reg32(p, CX2_INTERNAL_CMD_EVENT, reg); + return strnlen(buf, count); +} +static DEVICE_ATTR(command_event_reg, S_IWUSR|S_IRUGO, + show_command_event_reg,store_command_event_reg); + +static ssize_t show_mem_gpio_reg(struct device *d, char *buf) +{ + u32 reg = 0; + struct ipw_priv *p = (struct ipw_priv *)d->driver_data; + + reg = ipw_read_reg32(p, 0x301100); + return sprintf(buf, "0x%08x\n", reg); +} +static ssize_t store_mem_gpio_reg(struct device *d, + const char *buf, + size_t count) +{ + u32 reg; + struct ipw_priv *p = (struct ipw_priv *)d->driver_data; + + sscanf(buf, "%x", ®); + ipw_write_reg32(p, 0x301100, reg); + return strnlen(buf, count); +} +static DEVICE_ATTR(mem_gpio_reg, S_IWUSR|S_IRUGO, + show_mem_gpio_reg,store_mem_gpio_reg); + +static ssize_t show_indirect_dword(struct device *d, char *buf) +{ + u32 reg = 0; + struct ipw_priv *priv = (struct ipw_priv *)d->driver_data; + if (priv->status & STATUS_INDIRECT_DWORD) + reg = ipw_read_reg32(priv, priv->indirect_dword); + else + reg = 0; + + return sprintf(buf, "0x%08x\n", reg); +} +static ssize_t store_indirect_dword(struct device *d, + const char *buf, + size_t count) +{ + struct ipw_priv *priv = (struct ipw_priv *)d->driver_data; + + sscanf(buf, "%x", &priv->indirect_dword); + priv->status |= STATUS_INDIRECT_DWORD; + return strnlen(buf, count); +} +static DEVICE_ATTR(indirect_dword, S_IWUSR|S_IRUGO, + show_indirect_dword,store_indirect_dword); + +static ssize_t show_indirect_byte(struct device *d, char *buf) +{ + u8 reg = 0; + struct ipw_priv *priv = (struct ipw_priv *)d->driver_data; + if (priv->status & STATUS_INDIRECT_BYTE) + reg = ipw_read_reg8(priv, priv->indirect_byte); + else + reg = 0; + + return sprintf(buf, "0x%02x\n", reg); +} +static ssize_t store_indirect_byte(struct device *d, + const char *buf, + size_t count) +{ + struct ipw_priv *priv = (struct ipw_priv *)d->driver_data; + + sscanf(buf, "%x", &priv->indirect_byte); + priv->status |= STATUS_INDIRECT_BYTE; + return strnlen(buf, count); +} +static DEVICE_ATTR(indirect_byte, S_IWUSR|S_IRUGO, + show_indirect_byte, store_indirect_byte); + +static ssize_t show_direct_dword(struct device *d, char *buf) +{ + u32 reg = 0; + struct ipw_priv *priv = (struct ipw_priv *)d->driver_data; + + if (priv->status & STATUS_DIRECT_DWORD) + reg = ipw_read32(priv, priv->direct_dword); + else + reg = 0; + + return sprintf(buf, "0x%08x\n", reg); +} +static ssize_t store_direct_dword(struct device *d, + const char *buf, + size_t count) +{ + struct ipw_priv *priv = (struct ipw_priv *)d->driver_data; + + sscanf(buf, "%x", &priv->direct_dword); + priv->status |= STATUS_DIRECT_DWORD; + return strnlen(buf, count); +} +static DEVICE_ATTR(direct_dword, S_IWUSR|S_IRUGO, + show_direct_dword,store_direct_dword); + + +static inline int rf_kill_active(struct ipw_priv *priv) +{ + if (0 == (ipw_read32(priv, 0x30) & 0x10000)) + priv->status |= STATUS_RF_KILL_HW; + else + priv->status &= ~STATUS_RF_KILL_HW; + + return (priv->status & STATUS_RF_KILL_HW) ? 1 : 0; +} + +static ssize_t show_rf_kill(struct device *d, char *buf) +{ + /* 0 - RF kill not enabled + 1 - SW based RF kill active (sysfs) + 2 - HW based RF kill active + 3 - Both HW and SW baed RF kill active */ + struct ipw_priv *priv = (struct ipw_priv *)d->driver_data; + int val = ((priv->status & STATUS_RF_KILL_SW) ? 0x1 : 0x0) | + (rf_kill_active(priv) ? 0x2 : 0x0); + return sprintf(buf, "%i\n", val); +} + +static int ipw_radio_kill_sw(struct ipw_priv *priv, int disable_radio) +{ + if ((disable_radio ? 1 : 0) == + (priv->status & STATUS_RF_KILL_SW ? 1 : 0)) + return 0 ; + + IPW_DEBUG_RF_KILL("Manual SW RF Kill set to: RADIO %s\n", + disable_radio ? "OFF" : "ON"); + + if (disable_radio) { + priv->status |= STATUS_RF_KILL_SW; + + if (priv->workqueue) { + cancel_delayed_work(&priv->request_scan); + } + wake_up_interruptible(&priv->wait_command_queue); + queue_work(priv->workqueue, &priv->down); + } else { + priv->status &= ~STATUS_RF_KILL_SW; + if (rf_kill_active(priv)) { + IPW_DEBUG_RF_KILL("Can not turn radio back on - " + "disabled by HW switch\n"); + /* Make sure the RF_KILL check timer is running */ + cancel_delayed_work(&priv->rf_kill); + queue_delayed_work(priv->workqueue, &priv->rf_kill, + 2 * HZ); + } else + queue_work(priv->workqueue, &priv->up); + } + + return 1; +} + +static ssize_t store_rf_kill(struct device *d, const char *buf, size_t count) +{ + struct ipw_priv *priv = (struct ipw_priv *)d->driver_data; + + ipw_radio_kill_sw(priv, buf[0] == '1'); + + return count; +} +static DEVICE_ATTR(rf_kill, S_IWUSR|S_IRUGO, show_rf_kill, store_rf_kill); + +static void ipw_irq_tasklet(struct ipw_priv *priv) +{ + u32 inta, inta_mask, handled = 0; + unsigned long flags; + int rc = 0; + + spin_lock_irqsave(&priv->lock, flags); + + inta = ipw_read32(priv, CX2_INTA_RW); + inta_mask = ipw_read32(priv, CX2_INTA_MASK_R); + inta &= (CX2_INTA_MASK_ALL & inta_mask); + + /* Add any cached INTA values that need to be handled */ + inta |= priv->isr_inta; + + /* handle all the justifications for the interrupt */ + if (inta & CX2_INTA_BIT_RX_TRANSFER) { + ipw_rx(priv); + handled |= CX2_INTA_BIT_RX_TRANSFER; + } + + if (inta & CX2_INTA_BIT_TX_CMD_QUEUE) { + IPW_DEBUG_HC("Command completed.\n"); + rc = ipw_queue_tx_reclaim( priv, &priv->txq_cmd, -1); + priv->status &= ~STATUS_HCMD_ACTIVE; + wake_up_interruptible(&priv->wait_command_queue); + handled |= CX2_INTA_BIT_TX_CMD_QUEUE; + } + + if (inta & CX2_INTA_BIT_TX_QUEUE_1) { + IPW_DEBUG_TX("TX_QUEUE_1\n"); + rc = ipw_queue_tx_reclaim( priv, &priv->txq[0], 0); + handled |= CX2_INTA_BIT_TX_QUEUE_1; + } + + if (inta & CX2_INTA_BIT_TX_QUEUE_2) { + IPW_DEBUG_TX("TX_QUEUE_2\n"); + rc = ipw_queue_tx_reclaim( priv, &priv->txq[1], 1); + handled |= CX2_INTA_BIT_TX_QUEUE_2; + } + + if (inta & CX2_INTA_BIT_TX_QUEUE_3) { + IPW_DEBUG_TX("TX_QUEUE_3\n"); + rc = ipw_queue_tx_reclaim( priv, &priv->txq[2], 2); + handled |= CX2_INTA_BIT_TX_QUEUE_3; + } + + if (inta & CX2_INTA_BIT_TX_QUEUE_4) { + IPW_DEBUG_TX("TX_QUEUE_4\n"); + rc = ipw_queue_tx_reclaim( priv, &priv->txq[3], 3); + handled |= CX2_INTA_BIT_TX_QUEUE_4; + } + + if (inta & CX2_INTA_BIT_STATUS_CHANGE) { + IPW_WARNING("STATUS_CHANGE\n"); + handled |= CX2_INTA_BIT_STATUS_CHANGE; + } + + if (inta & CX2_INTA_BIT_BEACON_PERIOD_EXPIRED) { + IPW_WARNING("TX_PERIOD_EXPIRED\n"); + handled |= CX2_INTA_BIT_BEACON_PERIOD_EXPIRED; + } + + if (inta & CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE) { + IPW_WARNING("HOST_CMD_DONE\n"); + handled |= CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE; + } + + if (inta & CX2_INTA_BIT_FW_INITIALIZATION_DONE) { + IPW_WARNING("FW_INITIALIZATION_DONE\n"); + handled |= CX2_INTA_BIT_FW_INITIALIZATION_DONE; + } + + if (inta & CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE) { + IPW_WARNING("PHY_OFF_DONE\n"); + handled |= CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE; + } + + if (inta & CX2_INTA_BIT_RF_KILL_DONE) { + IPW_DEBUG_RF_KILL("RF_KILL_DONE\n"); + priv->status |= STATUS_RF_KILL_HW; + wake_up_interruptible(&priv->wait_command_queue); + netif_carrier_off(priv->net_dev); + netif_stop_queue(priv->net_dev); + cancel_delayed_work(&priv->request_scan); + queue_delayed_work(priv->workqueue, &priv->rf_kill, 2 * HZ); + handled |= CX2_INTA_BIT_RF_KILL_DONE; + } + + if (inta & CX2_INTA_BIT_FATAL_ERROR) { + IPW_ERROR("Firmware error detected. Restarting.\n"); +#ifdef CONFIG_IPW_DEBUG + if (ipw_debug_level & IPW_DL_FW_ERRORS) { + ipw_dump_nic_error_log(priv); + ipw_dump_nic_event_log(priv); + } +#endif + queue_work(priv->workqueue, &priv->adapter_restart); + handled |= CX2_INTA_BIT_FATAL_ERROR; + } + + if (inta & CX2_INTA_BIT_PARITY_ERROR) { + IPW_ERROR("Parity error\n"); + handled |= CX2_INTA_BIT_PARITY_ERROR; + } + + if (handled != inta) { + IPW_ERROR("Unhandled INTA bits 0x%08x\n", + inta & ~handled); + } + + /* enable all interrupts */ + ipw_enable_interrupts(priv); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +#ifdef CONFIG_IPW_DEBUG +#define IPW_CMD(x) case IPW_CMD_ ## x : return #x +static char *get_cmd_string(u8 cmd) +{ + switch (cmd) { + IPW_CMD(HOST_COMPLETE); + IPW_CMD(POWER_DOWN); + IPW_CMD(SYSTEM_CONFIG); + IPW_CMD(MULTICAST_ADDRESS); + IPW_CMD(SSID); + IPW_CMD(ADAPTER_ADDRESS); + IPW_CMD(PORT_TYPE); + IPW_CMD(RTS_THRESHOLD); + IPW_CMD(FRAG_THRESHOLD); + IPW_CMD(POWER_MODE); + IPW_CMD(WEP_KEY); + IPW_CMD(TGI_TX_KEY); + IPW_CMD(SCAN_REQUEST); + IPW_CMD(SCAN_REQUEST_EXT); + IPW_CMD(ASSOCIATE); + IPW_CMD(SUPPORTED_RATES); + IPW_CMD(SCAN_ABORT); + IPW_CMD(TX_FLUSH); + IPW_CMD(QOS_PARAMETERS); + IPW_CMD(DINO_CONFIG); + IPW_CMD(RSN_CAPABILITIES); + IPW_CMD(RX_KEY); + IPW_CMD(CARD_DISABLE); + IPW_CMD(SEED_NUMBER); + IPW_CMD(TX_POWER); + IPW_CMD(COUNTRY_INFO); + IPW_CMD(AIRONET_INFO); + IPW_CMD(AP_TX_POWER); + IPW_CMD(CCKM_INFO); + IPW_CMD(CCX_VER_INFO); + IPW_CMD(SET_CALIBRATION); + IPW_CMD(SENSITIVITY_CALIB); + IPW_CMD(RETRY_LIMIT); + IPW_CMD(IPW_PRE_POWER_DOWN); + IPW_CMD(VAP_BEACON_TEMPLATE); + IPW_CMD(VAP_DTIM_PERIOD); + IPW_CMD(EXT_SUPPORTED_RATES); + IPW_CMD(VAP_LOCAL_TX_PWR_CONSTRAINT); + IPW_CMD(VAP_QUIET_INTERVALS); + IPW_CMD(VAP_CHANNEL_SWITCH); + IPW_CMD(VAP_MANDATORY_CHANNELS); + IPW_CMD(VAP_CELL_PWR_LIMIT); + IPW_CMD(VAP_CF_PARAM_SET); + IPW_CMD(VAP_SET_BEACONING_STATE); + IPW_CMD(MEASUREMENT); + IPW_CMD(POWER_CAPABILITY); + IPW_CMD(SUPPORTED_CHANNELS); + IPW_CMD(TPC_REPORT); + IPW_CMD(WME_INFO); + IPW_CMD(PRODUCTION_COMMAND); + default: + return "UNKNOWN"; + } +} +#endif /* CONFIG_IPW_DEBUG */ + +#define HOST_COMPLETE_TIMEOUT HZ +static int ipw_ |