diff options
Diffstat (limited to 'drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c')
| -rw-r--r-- | drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c | 8139 |
1 files changed, 8139 insertions, 0 deletions
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c new file mode 100644 index 000000000000..218cbc8bf3a7 --- /dev/null +++ b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c @@ -0,0 +1,8139 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/pci_ids.h> +#include <linux/if_ether.h> +#include <net/cfg80211.h> +#include <net/mac80211.h> +#include <brcm_hw_ids.h> +#include <aiutils.h> +#include <chipcommon.h> +#include "rate.h" +#include "scb.h" +#include "phy/phy_hal.h" +#include "channel.h" +#include "antsel.h" +#include "stf.h" +#include "ampdu.h" +#include "mac80211_if.h" +#include "ucode_loader.h" +#include "main.h" +#include "soc.h" +#include "dma.h" +#include "debug.h" +#include "brcms_trace_events.h" + +/* watchdog timer, in unit of ms */ +#define TIMER_INTERVAL_WATCHDOG 1000 +/* radio monitor timer, in unit of ms */ +#define TIMER_INTERVAL_RADIOCHK 800 + +/* beacon interval, in unit of 1024TU */ +#define BEACON_INTERVAL_DEFAULT 100 + +/* n-mode support capability */ +/* 2x2 includes both 1x1 & 2x2 devices + * reserved #define 2 for future when we want to separate 1x1 & 2x2 and + * control it independently + */ +#define WL_11N_2x2 1 +#define WL_11N_3x3 3 +#define WL_11N_4x4 4 + +#define EDCF_ACI_MASK 0x60 +#define EDCF_ACI_SHIFT 5 +#define EDCF_ECWMIN_MASK 0x0f +#define EDCF_ECWMAX_SHIFT 4 +#define EDCF_AIFSN_MASK 0x0f +#define EDCF_AIFSN_MAX 15 +#define EDCF_ECWMAX_MASK 0xf0 + +#define EDCF_AC_BE_TXOP_STA 0x0000 +#define EDCF_AC_BK_TXOP_STA 0x0000 +#define EDCF_AC_VO_ACI_STA 0x62 +#define EDCF_AC_VO_ECW_STA 0x32 +#define EDCF_AC_VI_ACI_STA 0x42 +#define EDCF_AC_VI_ECW_STA 0x43 +#define EDCF_AC_BK_ECW_STA 0xA4 +#define EDCF_AC_VI_TXOP_STA 0x005e +#define EDCF_AC_VO_TXOP_STA 0x002f +#define EDCF_AC_BE_ACI_STA 0x03 +#define EDCF_AC_BE_ECW_STA 0xA4 +#define EDCF_AC_BK_ACI_STA 0x27 +#define EDCF_AC_VO_TXOP_AP 0x002f + +#define EDCF_TXOP2USEC(txop) ((txop) << 5) +#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1) + +#define APHY_SYMBOL_TIME 4 +#define APHY_PREAMBLE_TIME 16 +#define APHY_SIGNAL_TIME 4 +#define APHY_SIFS_TIME 16 +#define APHY_SERVICE_NBITS 16 +#define APHY_TAIL_NBITS 6 +#define BPHY_SIFS_TIME 10 +#define BPHY_PLCP_SHORT_TIME 96 + +#define PREN_PREAMBLE 24 +#define PREN_MM_EXT 12 +#define PREN_PREAMBLE_EXT 4 + +#define DOT11_MAC_HDR_LEN 24 +#define DOT11_ACK_LEN 10 +#define DOT11_BA_LEN 4 +#define DOT11_OFDM_SIGNAL_EXTENSION 6 +#define DOT11_MIN_FRAG_LEN 256 +#define DOT11_RTS_LEN 16 +#define DOT11_CTS_LEN 10 +#define DOT11_BA_BITMAP_LEN 128 +#define DOT11_MAXNUMFRAGS 16 +#define DOT11_MAX_FRAG_LEN 2346 + +#define BPHY_PLCP_TIME 192 +#define RIFS_11N_TIME 2 + +/* length of the BCN template area */ +#define BCN_TMPL_LEN 512 + +/* brcms_bss_info flag bit values */ +#define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */ + +/* chip rx buffer offset */ +#define BRCMS_HWRXOFF 38 + +/* rfdisable delay timer 500 ms, runs of ALP clock */ +#define RFDISABLE_DEFAULT 10000000 + +#define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */ + +/* synthpu_dly times in us */ +#define SYNTHPU_DLY_APHY_US 3700 +#define SYNTHPU_DLY_BPHY_US 1050 +#define SYNTHPU_DLY_NPHY_US 2048 +#define SYNTHPU_DLY_LPPHY_US 300 + +#define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */ + +/* Per-AC retry limit register definitions; uses defs.h bitfield macros */ +#define EDCF_SHORT_S 0 +#define EDCF_SFB_S 4 +#define EDCF_LONG_S 8 +#define EDCF_LFB_S 12 +#define EDCF_SHORT_M BITFIELD_MASK(4) +#define EDCF_SFB_M BITFIELD_MASK(4) +#define EDCF_LONG_M BITFIELD_MASK(4) +#define EDCF_LFB_M BITFIELD_MASK(4) + +#define RETRY_SHORT_DEF 7 /* Default Short retry Limit */ +#define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */ +#define RETRY_LONG_DEF 4 /* Default Long retry count */ +#define RETRY_SHORT_FB 3 /* Short count for fb rate */ +#define RETRY_LONG_FB 2 /* Long count for fb rate */ + +#define APHY_CWMIN 15 +#define PHY_CWMAX 1023 + +#define EDCF_AIFSN_MIN 1 + +#define FRAGNUM_MASK 0xF + +#define APHY_SLOT_TIME 9 +#define BPHY_SLOT_TIME 20 + +#define WL_SPURAVOID_OFF 0 +#define WL_SPURAVOID_ON1 1 +#define WL_SPURAVOID_ON2 2 + +/* invalid core flags, use the saved coreflags */ +#define BRCMS_USE_COREFLAGS 0xffffffff + +/* values for PLCPHdr_override */ +#define BRCMS_PLCP_AUTO -1 +#define BRCMS_PLCP_SHORT 0 +#define BRCMS_PLCP_LONG 1 + +/* values for g_protection_override and n_protection_override */ +#define BRCMS_PROTECTION_AUTO -1 +#define BRCMS_PROTECTION_OFF 0 +#define BRCMS_PROTECTION_ON 1 +#define BRCMS_PROTECTION_MMHDR_ONLY 2 +#define BRCMS_PROTECTION_CTS_ONLY 3 + +/* values for g_protection_control and n_protection_control */ +#define BRCMS_PROTECTION_CTL_OFF 0 +#define BRCMS_PROTECTION_CTL_LOCAL 1 +#define BRCMS_PROTECTION_CTL_OVERLAP 2 + +/* values for n_protection */ +#define BRCMS_N_PROTECTION_OFF 0 +#define BRCMS_N_PROTECTION_OPTIONAL 1 +#define BRCMS_N_PROTECTION_20IN40 2 +#define BRCMS_N_PROTECTION_MIXEDMODE 3 + +/* values for band specific 40MHz capabilities */ +#define BRCMS_N_BW_20ALL 0 +#define BRCMS_N_BW_40ALL 1 +#define BRCMS_N_BW_20IN2G_40IN5G 2 + +/* bitflags for SGI support (sgi_rx iovar) */ +#define BRCMS_N_SGI_20 0x01 +#define BRCMS_N_SGI_40 0x02 + +/* defines used by the nrate iovar */ +/* MSC in use,indicates b0-6 holds an mcs */ +#define NRATE_MCS_INUSE 0x00000080 +/* rate/mcs value */ +#define NRATE_RATE_MASK 0x0000007f +/* stf mode mask: siso, cdd, stbc, sdm */ +#define NRATE_STF_MASK 0x0000ff00 +/* stf mode shift */ +#define NRATE_STF_SHIFT 8 +/* bit indicate to override mcs only */ +#define NRATE_OVERRIDE_MCS_ONLY 0x40000000 +#define NRATE_SGI_MASK 0x00800000 /* sgi mode */ +#define NRATE_SGI_SHIFT 23 /* sgi mode */ +#define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */ +#define NRATE_LDPC_SHIFT 22 /* ldpc shift */ + +#define NRATE_STF_SISO 0 /* stf mode SISO */ +#define NRATE_STF_CDD 1 /* stf mode CDD */ +#define NRATE_STF_STBC 2 /* stf mode STBC */ +#define NRATE_STF_SDM 3 /* stf mode SDM */ + +#define MAX_DMA_SEGS 4 + +/* # of entries in Tx FIFO */ +#define NTXD 64 +/* Max # of entries in Rx FIFO based on 4kb page size */ +#define NRXD 256 + +/* Amount of headroom to leave in Tx FIFO */ +#define TX_HEADROOM 4 + +/* try to keep this # rbufs posted to the chip */ +#define NRXBUFPOST 32 + +/* max # frames to process in brcms_c_recv() */ +#define RXBND 8 +/* max # tx status to process in wlc_txstatus() */ +#define TXSBND 8 + +/* brcmu_format_flags() bit description structure */ +struct brcms_c_bit_desc { + u32 bit; + const char *name; +}; + +/* + * The following table lists the buffer memory allocated to xmt fifos in HW. + * the size is in units of 256bytes(one block), total size is HW dependent + * ucode has default fifo partition, sw can overwrite if necessary + * + * This is documented in twiki under the topic UcodeTxFifo. Please ensure + * the twiki is updated before making changes. + */ + +/* Starting corerev for the fifo size table */ +#define XMTFIFOTBL_STARTREV 17 + +struct d11init { + __le16 addr; + __le16 size; + __le32 value; +}; + +struct edcf_acparam { + u8 ACI; + u8 ECW; + u16 TXOP; +} __packed; + +/* debug/trace */ +uint brcm_msg_level; + +/* TX FIFO number to WME/802.1E Access Category */ +static const u8 wme_fifo2ac[] = { + IEEE80211_AC_BK, + IEEE80211_AC_BE, + IEEE80211_AC_VI, + IEEE80211_AC_VO, + IEEE80211_AC_BE, + IEEE80211_AC_BE +}; + +/* ieee80211 Access Category to TX FIFO number */ +static const u8 wme_ac2fifo[] = { + TX_AC_VO_FIFO, + TX_AC_VI_FIFO, + TX_AC_BE_FIFO, + TX_AC_BK_FIFO +}; + +static const u16 xmtfifo_sz[][NFIFO] = { + /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */ + {20, 192, 192, 21, 17, 5}, + /* corerev 18: */ + {0, 0, 0, 0, 0, 0}, + /* corerev 19: */ + {0, 0, 0, 0, 0, 0}, + /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */ + {20, 192, 192, 21, 17, 5}, + /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */ + {9, 58, 22, 14, 14, 5}, + /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */ + {20, 192, 192, 21, 17, 5}, + /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */ + {20, 192, 192, 21, 17, 5}, + /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */ + {9, 58, 22, 14, 14, 5}, + /* corerev 25: */ + {0, 0, 0, 0, 0, 0}, + /* corerev 26: */ + {0, 0, 0, 0, 0, 0}, + /* corerev 27: */ + {0, 0, 0, 0, 0, 0}, + /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */ + {9, 58, 22, 14, 14, 5}, +}; + +#ifdef DEBUG +static const char * const fifo_names[] = { + "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" }; +#else +static const char fifo_names[6][1]; +#endif + +#ifdef DEBUG +/* pointer to most recently allocated wl/wlc */ +static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL); +#endif + +/* Mapping of ieee80211 AC numbers to tx fifos */ +static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = { + [IEEE80211_AC_VO] = TX_AC_VO_FIFO, + [IEEE80211_AC_VI] = TX_AC_VI_FIFO, + [IEEE80211_AC_BE] = TX_AC_BE_FIFO, + [IEEE80211_AC_BK] = TX_AC_BK_FIFO, +}; + +/* Mapping of tx fifos to ieee80211 AC numbers */ +static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = { + [TX_AC_BK_FIFO] = IEEE80211_AC_BK, + [TX_AC_BE_FIFO] = IEEE80211_AC_BE, + [TX_AC_VI_FIFO] = IEEE80211_AC_VI, + [TX_AC_VO_FIFO] = IEEE80211_AC_VO, +}; + +static u8 brcms_ac_to_fifo(u8 ac) +{ + if (ac >= ARRAY_SIZE(ac_to_fifo_mapping)) + return TX_AC_BE_FIFO; + return ac_to_fifo_mapping[ac]; +} + +static u8 brcms_fifo_to_ac(u8 fifo) +{ + if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping)) + return IEEE80211_AC_BE; + return fifo_to_ac_mapping[fifo]; +} + +/* Find basic rate for a given rate */ +static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec) +{ + if (is_mcs_rate(rspec)) + return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK] + .leg_ofdm]; + return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK]; +} + +static u16 frametype(u32 rspec, u8 mimoframe) +{ + if (is_mcs_rate(rspec)) + return mimoframe; + return is_cck_rate(rspec) ? FT_CCK : FT_OFDM; +} + +/* currently the best mechanism for determining SIFS is the band in use */ +static u16 get_sifs(struct brcms_band *band) +{ + return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME : + BPHY_SIFS_TIME; +} + +/* + * Detect Card removed. + * Even checking an sbconfig register read will not false trigger when the core + * is in reset it breaks CF address mechanism. Accessing gphy phyversion will + * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible + * reg with fixed 0/1 pattern (some platforms return all 0). + * If clocks are present, call the sb routine which will figure out if the + * device is removed. + */ +static bool brcms_deviceremoved(struct brcms_c_info *wlc) +{ + u32 macctrl; + + if (!wlc->hw->clk) + return ai_deviceremoved(wlc->hw->sih); + macctrl = bcma_read32(wlc->hw->d11core, + D11REGOFFS(maccontrol)); + return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN; +} + +/* sum the individual fifo tx pending packet counts */ +static int brcms_txpktpendtot(struct brcms_c_info *wlc) +{ + int i; + int pending = 0; + + for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++) + if (wlc->hw->di[i]) + pending += dma_txpending(wlc->hw->di[i]); + return pending; +} + +static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc) +{ + return wlc->pub->_nbands > 1 && !wlc->bandlocked; +} + +static int brcms_chspec_bw(u16 chanspec) +{ + if (CHSPEC_IS40(chanspec)) + return BRCMS_40_MHZ; + if (CHSPEC_IS20(chanspec)) + return BRCMS_20_MHZ; + + return BRCMS_10_MHZ; +} + +static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg) +{ + if (cfg == NULL) + return; + + kfree(cfg->current_bss); + kfree(cfg); +} + +static void brcms_c_detach_mfree(struct brcms_c_info *wlc) +{ + if (wlc == NULL) + return; + + brcms_c_bsscfg_mfree(wlc->bsscfg); + kfree(wlc->pub); + kfree(wlc->modulecb); + kfree(wlc->default_bss); + kfree(wlc->protection); + kfree(wlc->stf); + kfree(wlc->bandstate[0]); + if (wlc->corestate) + kfree(wlc->corestate->macstat_snapshot); + kfree(wlc->corestate); + if (wlc->hw) + kfree(wlc->hw->bandstate[0]); + kfree(wlc->hw); + if (wlc->beacon) + dev_kfree_skb_any(wlc->beacon); + if (wlc->probe_resp) + dev_kfree_skb_any(wlc->probe_resp); + + kfree(wlc); +} + +static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit) +{ + struct brcms_bss_cfg *cfg; + + cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC); + if (cfg == NULL) + goto fail; + + cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC); + if (cfg->current_bss == NULL) + goto fail; + + return cfg; + + fail: + brcms_c_bsscfg_mfree(cfg); + return NULL; +} + +static struct brcms_c_info * +brcms_c_attach_malloc(uint unit, uint *err, uint devid) +{ + struct brcms_c_info *wlc; + + wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC); + if (wlc == NULL) { + *err = 1002; + goto fail; + } + + /* allocate struct brcms_c_pub state structure */ + wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC); + if (wlc->pub == NULL) { + *err = 1003; + goto fail; + } + wlc->pub->wlc = wlc; + + /* allocate struct brcms_hardware state structure */ + + wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC); + if (wlc->hw == NULL) { + *err = 1005; + goto fail; + } + wlc->hw->wlc = wlc; + + wlc->hw->bandstate[0] = + kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC); + if (wlc->hw->bandstate[0] == NULL) { + *err = 1006; + goto fail; + } else { + int i; + + for (i = 1; i < MAXBANDS; i++) + wlc->hw->bandstate[i] = (struct brcms_hw_band *) + ((unsigned long)wlc->hw->bandstate[0] + + (sizeof(struct brcms_hw_band) * i)); + } + + wlc->modulecb = + kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC); + if (wlc->modulecb == NULL) { + *err = 1009; + goto fail; + } + + wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC); + if (wlc->default_bss == NULL) { + *err = 1010; + goto fail; + } + + wlc->bsscfg = brcms_c_bsscfg_malloc(unit); + if (wlc->bsscfg == NULL) { + *err = 1011; + goto fail; + } + + wlc->protection = kzalloc(sizeof(struct brcms_protection), + GFP_ATOMIC); + if (wlc->protection == NULL) { + *err = 1016; + goto fail; + } + + wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC); + if (wlc->stf == NULL) { + *err = 1017; + goto fail; + } + + wlc->bandstate[0] = + kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC); + if (wlc->bandstate[0] == NULL) { + *err = 1025; + goto fail; + } else { + int i; + + for (i = 1; i < MAXBANDS; i++) + wlc->bandstate[i] = (struct brcms_band *) + ((unsigned long)wlc->bandstate[0] + + (sizeof(struct brcms_band)*i)); + } + + wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC); + if (wlc->corestate == NULL) { + *err = 1026; + goto fail; + } + + wlc->corestate->macstat_snapshot = + kzalloc(sizeof(struct macstat), GFP_ATOMIC); + if (wlc->corestate->macstat_snapshot == NULL) { + *err = 1027; + goto fail; + } + + return wlc; + + fail: + brcms_c_detach_mfree(wlc); + return NULL; +} + +/* + * Update the slot timing for standard 11b/g (20us slots) + * or shortslot 11g (9us slots) + * The PSM needs to be suspended for this call. + */ +static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw, + bool shortslot) +{ + struct bcma_device *core = wlc_hw->d11core; + + if (shortslot) { + /* 11g short slot: 11a timing */ + bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207); + brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME); + } else { + /* 11g long slot: 11b timing */ + bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212); + brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME); + } +} + +/* + * calculate frame duration of a given rate and length, return + * time in usec unit + */ +static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec, + u8 preamble_type, uint mac_len) +{ + uint nsyms, dur = 0, Ndps, kNdps; + uint rate = rspec2rate(ratespec); + + if (rate == 0) { + brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n", + wlc->pub->unit); + rate = BRCM_RATE_1M; + } + + if (is_mcs_rate(ratespec)) { + uint mcs = ratespec & RSPEC_RATE_MASK; + int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec); + + dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT); + if (preamble_type == BRCMS_MM_PREAMBLE) + dur += PREN_MM_EXT; + /* 1000Ndbps = kbps * 4 */ + kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), + rspec_issgi(ratespec)) * 4; + + if (rspec_stc(ratespec) == 0) + nsyms = + CEIL((APHY_SERVICE_NBITS + 8 * mac_len + + APHY_TAIL_NBITS) * 1000, kNdps); + else + /* STBC needs to have even number of symbols */ + nsyms = + 2 * + CEIL((APHY_SERVICE_NBITS + 8 * mac_len + + APHY_TAIL_NBITS) * 1000, 2 * kNdps); + + dur += APHY_SYMBOL_TIME * nsyms; + if (wlc->band->bandtype == BRCM_BAND_2G) + dur += DOT11_OFDM_SIGNAL_EXTENSION; + } else if (is_ofdm_rate(rate)) { + dur = APHY_PREAMBLE_TIME; + dur += APHY_SIGNAL_TIME; + /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */ + Ndps = rate * 2; + /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */ + nsyms = + CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS), + Ndps); + dur += APHY_SYMBOL_TIME * nsyms; + if (wlc->band->bandtype == BRCM_BAND_2G) + dur += DOT11_OFDM_SIGNAL_EXTENSION; + } else { + /* + * calc # bits * 2 so factor of 2 in rate (1/2 mbps) + * will divide out + */ + mac_len = mac_len * 8 * 2; + /* calc ceiling of bits/rate = microseconds of air time */ + dur = (mac_len + rate - 1) / rate; + if (preamble_type & BRCMS_SHORT_PREAMBLE) + dur += BPHY_PLCP_SHORT_TIME; + else + dur += BPHY_PLCP_TIME; + } + return dur; +} + +static void brcms_c_write_inits(struct brcms_hardware *wlc_hw, + const struct d11init *inits) +{ + struct bcma_device *core = wlc_hw->d11core; + int i; + uint offset; + u16 size; + u32 value; + + brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); + + for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) { + size = le16_to_cpu(inits[i].size); + offset = le16_to_cpu(inits[i].addr); + value = le32_to_cpu(inits[i].value); + if (size == 2) + bcma_write16(core, offset, value); + else if (size == 4) + bcma_write32(core, offset, value); + else + break; + } +} + +static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs) +{ + u8 idx; + u16 addr[] = { + M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, + M_HOST_FLAGS5 + }; + + for (idx = 0; idx < MHFMAX; idx++) + brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]); +} + +static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw) +{ + struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; + + /* init microcode host flags */ + brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs); + + /* do band-specific ucode IHR, SHM, and SCR inits */ + if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) { + if (BRCMS_ISNPHY(wlc_hw->band)) + brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16); + else + brcms_err(wlc_hw->d11core, + "%s: wl%d: unsupported phy in corerev %d\n", + __func__, wlc_hw->unit, + wlc_hw->corerev); + } else { + if (D11REV_IS(wlc_hw->corerev, 24)) { + if (BRCMS_ISLCNPHY(wlc_hw->band)) + brcms_c_write_inits(wlc_hw, + ucode->d11lcn0bsinitvals24); + else + brcms_err(wlc_hw->d11core, + "%s: wl%d: unsupported phy in core rev %d\n", + __func__, wlc_hw->unit, + wlc_hw->corerev); + } else { + brcms_err(wlc_hw->d11core, + "%s: wl%d: unsupported corerev %d\n", + __func__, wlc_hw->unit, wlc_hw->corerev); + } + } +} + +static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v) +{ + struct bcma_device *core = wlc_hw->d11core; + u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m; + + bcma_awrite32(core, BCMA_IOCTL, ioctl | v); +} + +static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk) +{ + brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk); + + wlc_hw->phyclk = clk; + + if (OFF == clk) { /* clear gmode bit, put phy into reset */ + + brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE), + (SICF_PRST | SICF_FGC)); + udelay(1); + brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST); + udelay(1); + + } else { /* take phy out of reset */ + + brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC); + udelay(1); + brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0); + udelay(1); + + } +} + +/* low-level band switch utility routine */ +static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit) +{ + brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit, + bandunit); + + wlc_hw->band = wlc_hw->bandstate[bandunit]; + + /* + * BMAC_NOTE: + * until we eliminate need for wlc->band refs in low level code + */ + wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit]; + + /* set gmode core flag */ + if (wlc_hw->sbclk && !wlc_hw->noreset) { + u32 gmode = 0; + + if (bandunit == 0) + gmode = SICF_GMODE; + + brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode); + } +} + +/* switch to new band but leave it inactive */ +static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit) +{ + struct brcms_hardware *wlc_hw = wlc->hw; + u32 macintmask; + u32 macctrl; + + brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); + macctrl = bcma_read32(wlc_hw->d11core, + D11REGOFFS(maccontrol)); + WARN_ON((macctrl & MCTL_EN_MAC) != 0); + + /* disable interrupts */ + macintmask = brcms_intrsoff(wlc->wl); + + /* radio off */ + wlc_phy_switch_radio(wlc_hw->band->pi, OFF); + + brcms_b_core_phy_clk(wlc_hw, OFF); + + brcms_c_setxband(wlc_hw, bandunit); + + return macintmask; +} + +/* process an individual struct tx_status */ +static bool +brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs) +{ + struct sk_buff *p = NULL; + uint queue = NFIFO; + struct dma_pub *dma = NULL; + struct d11txh *txh = NULL; + struct scb *scb = NULL; + bool free_pdu; + int tx_rts, tx_frame_count, tx_rts_count; + uint totlen, supr_status; + bool lastframe; + struct ieee80211_hdr *h; + u16 mcl; + struct ieee80211_tx_info *tx_info; + struct ieee80211_tx_rate *txrate; + int i; + bool fatal = true; + + trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen, + txs->frameid, txs->status, txs->lasttxtime, + txs->sequence, txs->phyerr, txs->ackphyrxsh); + + /* discard intermediate indications for ucode with one legitimate case: + * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, + * but the subsequent tx of DATA failed. so it will start rts/cts + * from the beginning (resetting the rts transmission count) + */ + if (!(txs->status & TX_STATUS_AMPDU) + && (txs->status & TX_STATUS_INTERMEDIATE)) { + brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n"); + fatal = false; + goto out; + } + + queue = txs->frameid & TXFID_QUEUE_MASK; + if (queue >= NFIFO) { + brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue); + goto out; + } + + dma = wlc->hw->di[queue]; + + p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED); + if (p == NULL) { + brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n"); + goto out; + } + + txh = (struct d11txh *) (p->data); + mcl = le16_to_cpu(txh->MacTxControlLow); + + if (txs->phyerr) + brcms_dbg_tx(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n", + txs->phyerr, txh->MainRates); + + if (txs->frameid != le16_to_cpu(txh->TxFrameID)) { + brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n"); + goto out; + } + tx_info = IEEE80211_SKB_CB(p); + h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN); + + if (tx_info->rate_driver_data[0]) + scb = &wlc->pri_scb; + + if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { + brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs); + fatal = false; + goto out; + } + + /* + * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU + * frames; this traces them for the rest. + */ + trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh)); + + supr_status = txs->status & TX_STATUS_SUPR_MASK; + if (supr_status == TX_STATUS_SUPR_BADCH) { + unsigned xfts = le16_to_cpu(txh->XtraFrameTypes); + brcms_dbg_tx(wlc->hw->d11core, + "Pkt tx suppressed, dest chan %u, current %d\n", + (xfts >> XFTS_CHANNEL_SHIFT) & 0xff, + CHSPEC_CHANNEL(wlc->default_bss->chanspec)); + } + + tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS; + tx_frame_count = + (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT; + tx_rts_count = + (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT; + + lastframe = !ieee80211_has_morefrags(h->frame_control); + + if (!lastframe) { + brcms_err(wlc->hw->d11core, "Not last frame!\n"); + } else { + /* + * Set information to be consumed by Minstrel ht. + * + * The "fallback limit" is the number of tx attempts a given + * MPDU is sent at the "primary" rate. Tx attempts beyond that + * limit are sent at the "secondary" rate. + * A 'short frame' does not exceed RTS treshold. + */ + u16 sfbl, /* Short Frame Rate Fallback Limit */ + lfbl, /* Long Frame Rate Fallback Limit */ + fbl; + + if (queue < IEEE80211_NUM_ACS) { + sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], + EDCF_SFB); + lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], + EDCF_LFB); + } else { + sfbl = wlc->SFBL; + lfbl = wlc->LFBL; + } + + txrate = tx_info->status.rates; + if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) + fbl = lfbl; + else + fbl = sfbl; + + ieee80211_tx_info_clear_status(tx_info); + + if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) { + /* + * rate selection requested a fallback rate + * and we used it + */ + txrate[0].count = fbl; + txrate[1].count = tx_frame_count - fbl; + } else { + /* + * rate selection did not request fallback rate, or + * we didn't need it + */ + txrate[0].count = tx_frame_count; + /* + * rc80211_minstrel.c:minstrel_tx_status() expects + * unused rates to be marked with idx = -1 + */ + txrate[1].idx = -1; + txrate[1].count = 0; + } + + /* clear the rest of the rates */ + for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) { + txrate[i].idx = -1; + txrate[i].count = 0; + } + + if (txs->status & TX_STATUS_ACK_RCV) + tx_info->flags |= IEEE80211_TX_STAT_ACK; + } + + totlen = p->len; + free_pdu = true; + + if (lastframe) { + /* remove PLCP & Broadcom tx descriptor header */ + skb_pull(p, D11_PHY_HDR_LEN); + skb_pull(p, D11_TXH_LEN); + ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p); + } else { + brcms_err(wlc->hw->d11core, + "%s: Not last frame => not calling tx_status\n", + __func__); + } + + fatal = false; + + out: + if (fatal) { + if (txh) + trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, + sizeof(*txh)); + brcmu_pkt_buf_free_skb(p); + } + + if (dma && queue < NFIFO) { + u16 ac_queue = brcms_fifo_to_ac(queue); + if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO && + ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue)) + ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue); + dma_kick_tx(dma); + } + + return fatal; +} + +/* process tx completion events in BMAC + * Return true if more tx status need to be processed. false otherwise. + */ +static bool +brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal) +{ + struct bcma_device *core; + struct tx_status txstatus, *txs; + u32 s1, s2; + uint n = 0; + /* + * Param 'max_tx_num' indicates max. # tx status to process before + * break out. + */ + uint max_tx_num = bound ? TXSBND : -1; + + txs = &txstatus; + core = wlc_hw->d11core; + *fatal = false; + + while (n < max_tx_num) { + s1 = bcma_read32(core, D11REGOFFS(frmtxstatus)); + if (s1 == 0xffffffff) { + brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, + __func__); + *fatal = true; + return false; + } + /* only process when valid */ + if (!(s1 & TXS_V)) + break; + + s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2)); + txs->status = s1 & TXS_STATUS_MASK; + txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT; + txs->sequence = s2 & TXS_SEQ_MASK; + txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT; + txs->lasttxtime = 0; + + *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs); + if (*fatal == true) + return false; + n++; + } + + return n >= max_tx_num; +} + +static void brcms_c_tbtt(struct brcms_c_info *wlc) +{ + if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC) + /* + * DirFrmQ is now valid...defer setting until end + * of ATIM window + */ + wlc->qvalid |= MCMD_DIRFRMQVAL; +} + +/* set initial host flags value */ +static void +brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init) +{ + struct brcms_hardware *wlc_hw = wlc->hw; + + memset(mhfs, 0, MHFMAX * sizeof(u16)); + + mhfs[MHF2] |= mhf2_init; + + /* prohibit use of slowclock on multifunction boards */ + if (wlc_hw->boardflags & BFL_NOPLLDOWN) + mhfs[MHF1] |= MHF1_FORCEFASTCLK; + + if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) { + mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR; + mhfs[MHF1] |= MHF1_IQSWAP_WAR; + } +} + +static uint +dmareg(uint direction, uint fifonum) +{ + if (direction == DMA_TX) + return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt); + return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv); +} + +static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme) +{ + uint i; + char name[8]; + /* + * ucode host flag 2 needed for pio mode, independent of band and fifo + */ + u16 pio_mhf2 = 0; + struct brcms_hardware *wlc_hw = wlc->hw; + uint unit = wlc_hw->unit; + + /* name and offsets for dma_attach */ + snprintf(name, sizeof(name), "wl%d", unit); + + if (wlc_hw->di[0] == NULL) { /* Init FIFOs */ + int dma_attach_err = 0; + + /* + * FIFO 0 + * TX: TX_AC_BK_FIFO (TX AC Background data packets) + * RX: RX_FIFO (RX data packets) + */ + wlc_hw->di[0] = dma_attach(name, wlc, + (wme ? dmareg(DMA_TX, 0) : 0), + dmareg(DMA_RX, 0), + (wme ? NTXD : 0), NRXD, + RXBUFSZ, -1, NRXBUFPOST, + BRCMS_HWRXOFF); + dma_attach_err |= (NULL == wlc_hw->di[0]); + + /* + * FIFO 1 + * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets) + * (legacy) TX_DATA_FIFO (TX data packets) + * RX: UNUSED + */ + wlc_hw->di[1] = dma_attach(name, wlc, + dmareg(DMA_TX, 1), 0, + NTXD, 0, 0, -1, 0, 0); + dma_attach_err |= (NULL == wlc_hw->di[1]); + + /* + * FIFO 2 + * TX: TX_AC_VI_FIFO (TX AC Video data packets) + * RX: UNUSED + */ + wlc_hw->di[2] = dma_attach(name, wlc, + dmareg(DMA_TX, 2), 0, + NTXD, 0, 0, -1, 0, 0); + dma_attach_err |= (NULL == wlc_hw->di[2]); + /* + * FIFO 3 + * TX: TX_AC_VO_FIFO (TX AC Voice data packets) + * (legacy) TX_CTL_FIFO (TX control & mgmt packets) + */ + wlc_hw->di[3] = dma_attach(name, wlc, + dmareg(DMA_TX, 3), + 0, NTXD, 0, 0, -1, + 0, 0); + dma_attach_err |= (NULL == wlc_hw->di[3]); +/* Cleaner to leave this as if with AP defined */ + + if (dma_attach_err) { + brcms_err(wlc_hw->d11core, + "wl%d: wlc_attach: dma_attach failed\n", + unit); + return false; + } + + /* get poi |