diff options
Diffstat (limited to 'drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h')
-rw-r--r-- | drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h new file mode 100644 index 000000000000..07d2a9000102 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_STLB_REGS_H_ +#define ASIC_REG_STLB_REGS_H_ + +/* + ***************************************** + * STLB (Prototype: STLB) + ***************************************** + */ + +#define mmSTLB_CACHE_INV 0xC12010 + +#define mmSTLB_CACHE_INV_BASE_39_8 0xC12014 + +#define mmSTLB_CACHE_INV_BASE_49_40 0xC12018 + +#define mmSTLB_STLB_FEATURE_EN 0xC1201C + +#define mmSTLB_STLB_AXI_CACHE 0xC12020 + +#define mmSTLB_HOP_CONFIGURATION 0xC12024 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32 0xC12028 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0 0xC1202C + +#define mmSTLB_LINK_LIST 0xC12030 + +#define mmSTLB_INV_ALL_START 0xC12034 + +#define mmSTLB_INV_ALL_SET 0xC12038 + +#define mmSTLB_INV_PS 0xC1203C + +#define mmSTLB_INV_CONSUMER_INDEX 0xC12040 + +#define mmSTLB_INV_HIT_COUNT 0xC12044 + +#define mmSTLB_INV_SET 0xC12048 + +#define mmSTLB_SRAM_INIT 0xC1204C + +#define mmSTLB_MEM_CACHE_INVALIDATION 0xC12050 + +#define mmSTLB_MEM_CACHE_INV_STATUS 0xC12054 + +#define mmSTLB_MEM_CACHE_BASE_38_7 0xC12058 + +#define mmSTLB_MEM_CACHE_BASE_49_39 0xC1205C + +#define mmSTLB_MEM_CACHE_CONFIG 0xC12060 + +#define mmSTLB_SET_THRESHOLD_HOP4 0xC12064 + +#define mmSTLB_SET_THRESHOLD_HOP3 0xC12068 + +#define mmSTLB_SET_THRESHOLD_HOP2 0xC1206C + +#define mmSTLB_SET_THRESHOLD_HOP1 0xC12070 + +#define mmSTLB_SET_THRESHOLD_HOP0 0xC12074 + +#define mmSTLB_MULTI_HIT_INTERRUPT_CLR 0xC12078 + +#define mmSTLB_MULTI_HIT_INTERRUPT_MASK 0xC1207C + +#define mmSTLB_MEM_L0_CACHE_CFG 0xC12080 + +#define mmSTLB_MEM_READ_ARPROT 0xC12084 + +#endif /* ASIC_REG_STLB_REGS_H_ */ |