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path: root/drivers/media/platform/ti-vpe/vpe_regs.h
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Diffstat (limited to 'drivers/media/platform/ti-vpe/vpe_regs.h')
-rw-r--r--drivers/media/platform/ti-vpe/vpe_regs.h187
1 files changed, 0 insertions, 187 deletions
diff --git a/drivers/media/platform/ti-vpe/vpe_regs.h b/drivers/media/platform/ti-vpe/vpe_regs.h
index ed214e828398..74283d79eae1 100644
--- a/drivers/media/platform/ti-vpe/vpe_regs.h
+++ b/drivers/media/platform/ti-vpe/vpe_regs.h
@@ -306,191 +306,4 @@
#define VPE_FMD_FRAME_DIFF_MASK 0x000fffff
#define VPE_FMD_FRAME_DIFF_SHIFT 0
-/* VPE scaler regs */
-#define VPE_SC_MP_SC0 0x0700
-#define VPE_INTERLACE_O (1 << 0)
-#define VPE_LINEAR (1 << 1)
-#define VPE_SC_BYPASS (1 << 2)
-#define VPE_INVT_FID (1 << 3)
-#define VPE_USE_RAV (1 << 4)
-#define VPE_ENABLE_EV (1 << 5)
-#define VPE_AUTO_HS (1 << 6)
-#define VPE_DCM_2X (1 << 7)
-#define VPE_DCM_4X (1 << 8)
-#define VPE_HP_BYPASS (1 << 9)
-#define VPE_INTERLACE_I (1 << 10)
-#define VPE_ENABLE_SIN2_VER_INTP (1 << 11)
-#define VPE_Y_PK_EN (1 << 14)
-#define VPE_TRIM (1 << 15)
-#define VPE_SELFGEN_FID (1 << 16)
-
-#define VPE_SC_MP_SC1 0x0704
-#define VPE_ROW_ACC_INC_MASK 0x07ffffff
-#define VPE_ROW_ACC_INC_SHIFT 0
-
-#define VPE_SC_MP_SC2 0x0708
-#define VPE_ROW_ACC_OFFSET_MASK 0x0fffffff
-#define VPE_ROW_ACC_OFFSET_SHIFT 0
-
-#define VPE_SC_MP_SC3 0x070c
-#define VPE_ROW_ACC_OFFSET_B_MASK 0x0fffffff
-#define VPE_ROW_ACC_OFFSET_B_SHIFT 0
-
-#define VPE_SC_MP_SC4 0x0710
-#define VPE_TAR_H_MASK 0x07ff
-#define VPE_TAR_H_SHIFT 0
-#define VPE_TAR_W_MASK 0x07ff
-#define VPE_TAR_W_SHIFT 12
-#define VPE_LIN_ACC_INC_U_MASK 0x07
-#define VPE_LIN_ACC_INC_U_SHIFT 24
-#define VPE_NLIN_ACC_INIT_U_MASK 0x07
-#define VPE_NLIN_ACC_INIT_U_SHIFT 28
-
-#define VPE_SC_MP_SC5 0x0714
-#define VPE_SRC_H_MASK 0x07ff
-#define VPE_SRC_H_SHIFT 0
-#define VPE_SRC_W_MASK 0x07ff
-#define VPE_SRC_W_SHIFT 12
-#define VPE_NLIN_ACC_INC_U_MASK 0x07
-#define VPE_NLIN_ACC_INC_U_SHIFT 24
-
-#define VPE_SC_MP_SC6 0x0718
-#define VPE_ROW_ACC_INIT_RAV_MASK 0x03ff
-#define VPE_ROW_ACC_INIT_RAV_SHIFT 0
-#define VPE_ROW_ACC_INIT_RAV_B_MASK 0x03ff
-#define VPE_ROW_ACC_INIT_RAV_B_SHIFT 10
-
-#define VPE_SC_MP_SC8 0x0720
-#define VPE_NLIN_LEFT_MASK 0x07ff
-#define VPE_NLIN_LEFT_SHIFT 0
-#define VPE_NLIN_RIGHT_MASK 0x07ff
-#define VPE_NLIN_RIGHT_SHIFT 12
-
-#define VPE_SC_MP_SC9 0x0724
-#define VPE_LIN_ACC_INC VPE_SC_MP_SC9
-
-#define VPE_SC_MP_SC10 0x0728
-#define VPE_NLIN_ACC_INIT VPE_SC_MP_SC10
-
-#define VPE_SC_MP_SC11 0x072c
-#define VPE_NLIN_ACC_INC VPE_SC_MP_SC11
-
-#define VPE_SC_MP_SC12 0x0730
-#define VPE_COL_ACC_OFFSET_MASK 0x01ffffff
-#define VPE_COL_ACC_OFFSET_SHIFT 0
-
-#define VPE_SC_MP_SC13 0x0734
-#define VPE_SC_FACTOR_RAV_MASK 0x03ff
-#define VPE_SC_FACTOR_RAV_SHIFT 0
-#define VPE_CHROMA_INTP_THR_MASK 0x03ff
-#define VPE_CHROMA_INTP_THR_SHIFT 12
-#define VPE_DELTA_CHROMA_THR_MASK 0x0f
-#define VPE_DELTA_CHROMA_THR_SHIFT 24
-
-#define VPE_SC_MP_SC17 0x0744
-#define VPE_EV_THR_MASK 0x03ff
-#define VPE_EV_THR_SHIFT 12
-#define VPE_DELTA_LUMA_THR_MASK 0x0f
-#define VPE_DELTA_LUMA_THR_SHIFT 24
-#define VPE_DELTA_EV_THR_MASK 0x0f
-#define VPE_DELTA_EV_THR_SHIFT 28
-
-#define VPE_SC_MP_SC18 0x0748
-#define VPE_HS_FACTOR_MASK 0x03ff
-#define VPE_HS_FACTOR_SHIFT 0
-#define VPE_CONF_DEFAULT_MASK 0x01ff
-#define VPE_CONF_DEFAULT_SHIFT 16
-
-#define VPE_SC_MP_SC19 0x074c
-#define VPE_HPF_COEFF0_MASK 0xff
-#define VPE_HPF_COEFF0_SHIFT 0
-#define VPE_HPF_COEFF1_MASK 0xff
-#define VPE_HPF_COEFF1_SHIFT 8
-#define VPE_HPF_COEFF2_MASK 0xff
-#define VPE_HPF_COEFF2_SHIFT 16
-#define VPE_HPF_COEFF3_MASK 0xff
-#define VPE_HPF_COEFF3_SHIFT 23
-
-#define VPE_SC_MP_SC20 0x0750
-#define VPE_HPF_COEFF4_MASK 0xff
-#define VPE_HPF_COEFF4_SHIFT 0
-#define VPE_HPF_COEFF5_MASK 0xff
-#define VPE_HPF_COEFF5_SHIFT 8
-#define VPE_HPF_NORM_SHIFT_MASK 0x07
-#define VPE_HPF_NORM_SHIFT_SHIFT 16
-#define VPE_NL_LIMIT_MASK 0x1ff
-#define VPE_NL_LIMIT_SHIFT 20
-
-#define VPE_SC_MP_SC21 0x0754
-#define VPE_NL_LO_THR_MASK 0x01ff
-#define VPE_NL_LO_THR_SHIFT 0
-#define VPE_NL_LO_SLOPE_MASK 0xff
-#define VPE_NL_LO_SLOPE_SHIFT 16
-
-#define VPE_SC_MP_SC22 0x0758
-#define VPE_NL_HI_THR_MASK 0x01ff
-#define VPE_NL_HI_THR_SHIFT 0
-#define VPE_NL_HI_SLOPE_SH_MASK 0x07
-#define VPE_NL_HI_SLOPE_SH_SHIFT 16
-
-#define VPE_SC_MP_SC23 0x075c
-#define VPE_GRADIENT_THR_MASK 0x07ff
-#define VPE_GRADIENT_THR_SHIFT 0
-#define VPE_GRADIENT_THR_RANGE_MASK 0x0f
-#define VPE_GRADIENT_THR_RANGE_SHIFT 12
-#define VPE_MIN_GY_THR_MASK 0xff
-#define VPE_MIN_GY_THR_SHIFT 16
-#define VPE_MIN_GY_THR_RANGE_MASK 0x0f
-#define VPE_MIN_GY_THR_RANGE_SHIFT 28
-
-#define VPE_SC_MP_SC24 0x0760
-#define VPE_ORG_H_MASK 0x07ff
-#define VPE_ORG_H_SHIFT 0
-#define VPE_ORG_W_MASK 0x07ff
-#define VPE_ORG_W_SHIFT 16
-
-#define VPE_SC_MP_SC25 0x0764
-#define VPE_OFF_H_MASK 0x07ff
-#define VPE_OFF_H_SHIFT 0
-#define VPE_OFF_W_MASK 0x07ff
-#define VPE_OFF_W_SHIFT 16
-
-/* VPE color space converter regs */
-#define VPE_CSC_CSC00 0x5700
-#define VPE_CSC_A0_MASK 0x1fff
-#define VPE_CSC_A0_SHIFT 0
-#define VPE_CSC_B0_MASK 0x1fff
-#define VPE_CSC_B0_SHIFT 16
-
-#define VPE_CSC_CSC01 0x5704
-#define VPE_CSC_C0_MASK 0x1fff
-#define VPE_CSC_C0_SHIFT 0
-#define VPE_CSC_A1_MASK 0x1fff
-#define VPE_CSC_A1_SHIFT 16
-
-#define VPE_CSC_CSC02 0x5708
-#define VPE_CSC_B1_MASK 0x1fff
-#define VPE_CSC_B1_SHIFT 0
-#define VPE_CSC_C1_MASK 0x1fff
-#define VPE_CSC_C1_SHIFT 16
-
-#define VPE_CSC_CSC03 0x570c
-#define VPE_CSC_A2_MASK 0x1fff
-#define VPE_CSC_A2_SHIFT 0
-#define VPE_CSC_B2_MASK 0x1fff
-#define VPE_CSC_B2_SHIFT 16
-
-#define VPE_CSC_CSC04 0x5710
-#define VPE_CSC_C2_MASK 0x1fff
-#define VPE_CSC_C2_SHIFT 0
-#define VPE_CSC_D0_MASK 0x0fff
-#define VPE_CSC_D0_SHIFT 16
-
-#define VPE_CSC_CSC05 0x5714
-#define VPE_CSC_D1_MASK 0x0fff
-#define VPE_CSC_D1_SHIFT 0
-#define VPE_CSC_D2_MASK 0x0fff
-#define VPE_CSC_D2_SHIFT 16
-#define VPE_CSC_BYPASS (1 << 28)
-
#endif