diff options
Diffstat (limited to 'drivers/media/dvb/frontends/drxd_hard.c')
| -rw-r--r-- | drivers/media/dvb/frontends/drxd_hard.c | 2992 |
1 files changed, 0 insertions, 2992 deletions
diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c deleted file mode 100644 index f380eb43e9d5..000000000000 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ /dev/null @@ -1,2992 +0,0 @@ -/* - * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1 - * - * Copyright (C) 2003-2007 Micronas - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/moduleparam.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/firmware.h> -#include <linux/i2c.h> -#include <asm/div64.h> - -#include "dvb_frontend.h" -#include "drxd.h" -#include "drxd_firm.h" - -#define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw" -#define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw" - -#define CHUNK_SIZE 48 - -#define DRX_I2C_RMW 0x10 -#define DRX_I2C_BROADCAST 0x20 -#define DRX_I2C_CLEARCRC 0x80 -#define DRX_I2C_SINGLE_MASTER 0xC0 -#define DRX_I2C_MODEFLAGS 0xC0 -#define DRX_I2C_FLAGS 0xF0 - -#ifndef SIZEOF_ARRAY -#define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0])) -#endif - -#define DEFAULT_LOCK_TIMEOUT 1100 - -#define DRX_CHANNEL_AUTO 0 -#define DRX_CHANNEL_HIGH 1 -#define DRX_CHANNEL_LOW 2 - -#define DRX_LOCK_MPEG 1 -#define DRX_LOCK_FEC 2 -#define DRX_LOCK_DEMOD 4 - -/****************************************************************************/ - -enum CSCDState { - CSCD_INIT = 0, - CSCD_SET, - CSCD_SAVED -}; - -enum CDrxdState { - DRXD_UNINITIALIZED = 0, - DRXD_STOPPED, - DRXD_STARTED -}; - -enum AGC_CTRL_MODE { - AGC_CTRL_AUTO = 0, - AGC_CTRL_USER, - AGC_CTRL_OFF -}; - -enum OperationMode { - OM_Default, - OM_DVBT_Diversity_Front, - OM_DVBT_Diversity_End -}; - -struct SCfgAgc { - enum AGC_CTRL_MODE ctrlMode; - u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ - u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */ - u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ - u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ - u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */ - - u16 R1; - u16 R2; - u16 R3; -}; - -struct SNoiseCal { - int cpOpt; - short cpNexpOfs; - short tdCal2k; - short tdCal8k; -}; - -enum app_env { - APPENV_STATIC = 0, - APPENV_PORTABLE = 1, - APPENV_MOBILE = 2 -}; - -enum EIFFilter { - IFFILTER_SAW = 0, - IFFILTER_DISCRETE = 1 -}; - -struct drxd_state { - struct dvb_frontend frontend; - struct dvb_frontend_ops ops; - struct dtv_frontend_properties props; - - const struct firmware *fw; - struct device *dev; - - struct i2c_adapter *i2c; - void *priv; - struct drxd_config config; - - int i2c_access; - int init_done; - struct mutex mutex; - - u8 chip_adr; - u16 hi_cfg_timing_div; - u16 hi_cfg_bridge_delay; - u16 hi_cfg_wakeup_key; - u16 hi_cfg_ctrl; - - u16 intermediate_freq; - u16 osc_clock_freq; - - enum CSCDState cscd_state; - enum CDrxdState drxd_state; - - u16 sys_clock_freq; - s16 osc_clock_deviation; - u16 expected_sys_clock_freq; - - u16 insert_rs_byte; - u16 enable_parallel; - - int operation_mode; - - struct SCfgAgc if_agc_cfg; - struct SCfgAgc rf_agc_cfg; - - struct SNoiseCal noise_cal; - - u32 fe_fs_add_incr; - u32 org_fe_fs_add_incr; - u16 current_fe_if_incr; - - u16 m_FeAgRegAgPwd; - u16 m_FeAgRegAgAgcSio; - - u16 m_EcOcRegOcModeLop; - u16 m_EcOcRegSncSncLvl; - u8 *m_InitAtomicRead; - u8 *m_HiI2cPatch; - - u8 *m_ResetCEFR; - u8 *m_InitFE_1; - u8 *m_InitFE_2; - u8 *m_InitCP; - u8 *m_InitCE; - u8 *m_InitEQ; - u8 *m_InitSC; - u8 *m_InitEC; - u8 *m_ResetECRAM; - u8 *m_InitDiversityFront; - u8 *m_InitDiversityEnd; - u8 *m_DisableDiversity; - u8 *m_StartDiversityFront; - u8 *m_StartDiversityEnd; - - u8 *m_DiversityDelay8MHZ; - u8 *m_DiversityDelay6MHZ; - - u8 *microcode; - u32 microcode_length; - - int type_A; - int PGA; - int diversity; - int tuner_mirrors; - - enum app_env app_env_default; - enum app_env app_env_diversity; - -}; - -/****************************************************************************/ -/* I2C **********************************************************************/ -/****************************************************************************/ - -static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len) -{ - struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len }; - - if (i2c_transfer(adap, &msg, 1) != 1) - return -1; - return 0; -} - -static int i2c_read(struct i2c_adapter *adap, - u8 adr, u8 *msg, int len, u8 *answ, int alen) -{ - struct i2c_msg msgs[2] = { - { - .addr = adr, .flags = 0, - .buf = msg, .len = len - }, { - .addr = adr, .flags = I2C_M_RD, - .buf = answ, .len = alen - } - }; - if (i2c_transfer(adap, msgs, 2) != 2) - return -1; - return 0; -} - -static inline u32 MulDiv32(u32 a, u32 b, u32 c) -{ - u64 tmp64; - - tmp64 = (u64)a * (u64)b; - do_div(tmp64, c); - - return (u32) tmp64; -} - -static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) -{ - u8 adr = state->config.demod_address; - u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, - flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff - }; - u8 mm2[2]; - if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) - return -1; - if (data) - *data = mm2[0] | (mm2[1] << 8); - return mm2[0] | (mm2[1] << 8); -} - -static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) -{ - u8 adr = state->config.demod_address; - u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, - flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff - }; - u8 mm2[4]; - - if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) - return -1; - if (data) - *data = - mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24); - return 0; -} - -static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) -{ - u8 adr = state->config.demod_address; - u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff, - flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, - data & 0xff, (data >> 8) & 0xff - }; - - if (i2c_write(state->i2c, adr, mm, 6) < 0) - return -1; - return 0; -} - -static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) -{ - u8 adr = state->config.demod_address; - u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff, - flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, - data & 0xff, (data >> 8) & 0xff, - (data >> 16) & 0xff, (data >> 24) & 0xff - }; - - if (i2c_write(state->i2c, adr, mm, 8) < 0) - return -1; - return 0; -} - -static int write_chunk(struct drxd_state *state, - u32 reg, u8 *data, u32 len, u8 flags) -{ - u8 adr = state->config.demod_address; - u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff, - flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff - }; - int i; - - for (i = 0; i < len; i++) - mm[4 + i] = data[i]; - if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { - printk(KERN_ERR "error in write_chunk\n"); - return -1; - } - return 0; -} - -static int WriteBlock(struct drxd_state *state, - u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags) -{ - while (BlockSize > 0) { - u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize; - - if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0) - return -1; - pBlock += Chunk; - Address += (Chunk >> 1); - BlockSize -= Chunk; - } - return 0; -} - -static int WriteTable(struct drxd_state *state, u8 * pTable) -{ - int status = 0; - - if (pTable == NULL) - return 0; - - while (!status) { - u16 Length; - u32 Address = pTable[0] | (pTable[1] << 8) | - (pTable[2] << 16) | (pTable[3] << 24); - - if (Address == 0xFFFFFFFF) - break; - pTable += sizeof(u32); - - Length = pTable[0] | (pTable[1] << 8); - pTable += sizeof(u16); - if (!Length) - break; - status = WriteBlock(state, Address, Length * 2, pTable, 0); - pTable += (Length * 2); - } - return status; -} - -/****************************************************************************/ -/****************************************************************************/ -/****************************************************************************/ - -static int ResetCEFR(struct drxd_state *state) -{ - return WriteTable(state, state->m_ResetCEFR); -} - -static int InitCP(struct drxd_state *state) -{ - return WriteTable(state, state->m_InitCP); -} - -static int InitCE(struct drxd_state *state) -{ - int status; - enum app_env AppEnv = state->app_env_default; - - do { - status = WriteTable(state, state->m_InitCE); - if (status < 0) - break; - - if (state->operation_mode == OM_DVBT_Diversity_Front || - state->operation_mode == OM_DVBT_Diversity_End) { - AppEnv = state->app_env_diversity; - } - if (AppEnv == APPENV_STATIC) { - status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); - if (status < 0) - break; - } else if (AppEnv == APPENV_PORTABLE) { - status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); - if (status < 0) - break; - } else if (AppEnv == APPENV_MOBILE && state->type_A) { - status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); - if (status < 0) - break; - } else if (AppEnv == APPENV_MOBILE && !state->type_A) { - status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); - if (status < 0) - break; - } - - /* start ce */ - status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); - if (status < 0) - break; - } while (0); - return status; -} - -static int StopOC(struct drxd_state *state) -{ - int status = 0; - u16 ocSyncLvl = 0; - u16 ocModeLop = state->m_EcOcRegOcModeLop; - u16 dtoIncLop = 0; - u16 dtoIncHip = 0; - - do { - /* Store output configuration */ - status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); - if (status < 0) - break; - /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */ - state->m_EcOcRegSncSncLvl = ocSyncLvl; - /* m_EcOcRegOcModeLop = ocModeLop; */ - - /* Flush FIFO (byte-boundary) at fixed rate */ - status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); - if (status < 0) - break; - status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); - if (status < 0) - break; - status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); - if (status < 0) - break; - status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); - if (status < 0) - break; - ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M); - ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC; - status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); - if (status < 0) - break; - status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); - if (status < 0) - break; - - msleep(1); - /* Output pins to '0' */ - status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); - if (status < 0) - break; - - /* Force the OC out of sync */ - ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M); - status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); - if (status < 0) - break; - ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M); - ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE; - ocModeLop |= 0x2; /* Magically-out-of-sync */ - status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); - if (status < 0) - break; - status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); - if (status < 0) - break; - status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); - if (status < 0) - break; - } while (0); - - return status; -} - -static int StartOC(struct drxd_state *state) -{ - int status = 0; - - do { - /* Stop OC */ - status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); - if (status < 0) - break; - - /* Restore output configuration */ - status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); - if (status < 0) - break; - status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); - if (status < 0) - break; - - /* Output pins active again */ - status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); - if (status < 0) - break; - - /* Start OC */ - status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); - if (status < 0) - break; - } while (0); - return status; -} - -static int InitEQ(struct drxd_state *state) -{ - return WriteTable(state, state->m_InitEQ); -} - -static int InitEC(struct drxd_state *state) -{ - return WriteTable(state, state->m_InitEC); -} - -static int InitSC(struct drxd_state *state) -{ - return WriteTable(state, state->m_InitSC); -} - -static int InitAtomicRead(struct drxd_state *state) -{ - return WriteTable(state, state->m_InitAtomicRead); -} - -static int CorrectSysClockDeviation(struct drxd_state *state); - -static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) -{ - u16 ScRaRamLock = 0; - const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M | - SC_RA_RAM_LOCK_FEC__M | - SC_RA_RAM_LOCK_DEMOD__M); - const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M | - SC_RA_RAM_LOCK_DEMOD__M); - const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M; - - int status; - - *pLockStatus = 0; - - status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); - if (status < 0) { - printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); - return status; - } - - if (state->drxd_state != DRXD_STARTED) - return 0; - - if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { - *pLockStatus |= DRX_LOCK_MPEG; - CorrectSysClockDeviation(state); - } - - if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) - *pLockStatus |= DRX_LOCK_FEC; - - if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) - *pLockStatus |= DRX_LOCK_DEMOD; - return 0; -} - -/****************************************************************************/ - -static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) -{ - int status; - - if (cfg->outputLevel > DRXD_FE_CTRL_MAX) - return -1; - - if (cfg->ctrlMode == AGC_CTRL_USER) { - do { - u16 FeAgRegPm1AgcWri; - u16 FeAgRegAgModeLop; - - status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); - if (status < 0) - break; - FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); - FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC; - status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); - if (status < 0) - break; - - FeAgRegPm1AgcWri = (u16) (cfg->outputLevel & - FE_AG_REG_PM1_AGC_WRI__M); - status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); - if (status < 0) - break; - } while (0); - } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { - if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) || - ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) || - ((cfg->speed) > DRXD_FE_CTRL_MAX) || - ((cfg->settleLevel) > DRXD_FE_CTRL_MAX) - ) - return -1; - do { - u16 FeAgRegAgModeLop; - u16 FeAgRegEgcSetLvl; - u16 slope, offset; - - /* == Mode == */ - - status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); - if (status < 0) - break; - FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); - FeAgRegAgModeLop |= - FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; - status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); - if (status < 0) - break; - - /* == Settle level == */ - - FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) & - FE_AG_REG_EGC_SET_LVL__M); - status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); - if (status < 0) - break; - - /* == Min/Max == */ - - slope = (u16) ((cfg->maxOutputLevel - - cfg->minOutputLevel) / 2); - offset = (u16) ((cfg->maxOutputLevel + - cfg->minOutputLevel) / 2 - 511); - - status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); - if (status < 0) - break; - status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); - if (status < 0) - break; - - /* == Speed == */ - { - const u16 maxRur = 8; - const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 }; - const u16 fastIncrDecLUT[] = { 14, 15, 15, 16, - 17, 18, 18, 19, - 20, 21, 22, 23, - 24, 26, 27, 28, - 29, 31 - }; - - u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) / - (maxRur + 1); - u16 fineSpeed = (u16) (cfg->speed - - ((cfg->speed / - fineSteps) * - fineSteps)); - u16 invRurCount = (u16) (cfg->speed / - fineSteps); - u16 rurCount; - if (invRurCount > maxRur) { - rurCount = 0; - fineSpeed += fineSteps; - } else { - rurCount = maxRur - invRurCount; - } - - /* - fastInc = default * - (2^(fineSpeed/fineSteps)) - => range[default...2*default> - slowInc = default * - (2^(fineSpeed/fineSteps)) - */ - { - u16 fastIncrDec = - fastIncrDecLUT[fineSpeed / - ((fineSteps / - (14 + 1)) + 1)]; - u16 slowIncrDec = - slowIncrDecLUT[fineSpeed / - (fineSteps / - (3 + 1))]; - - status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); - if (status < 0) - break; - status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); - if (status < 0) - break; - status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); - if (status < 0) - break; - status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); - if (status < 0) - break; - status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); - if (status < 0) - break; - } - } - } while (0); - - } else { - /* No OFF mode for IF control */ - return -1; - } - return status; -} - -static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) -{ - int status = 0; - - if (cfg->outputLevel > DRXD_FE_CTRL_MAX) - return -1; - - if (cfg->ctrlMode == AGC_CTRL_USER) { - do { - u16 AgModeLop = 0; - u16 level = (cfg->outputLevel); - - if (level == DRXD_FE_CTRL_MAX) - level++; - - status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); - if (status < 0) - break; - - /*==== Mode ====*/ - - /* Powerdown PD2, WRI source */ - state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); - state->m_FeAgRegAgPwd |= - FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; - status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); - if (status < 0) - break; - - status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); - if (status < 0) - break; - AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | - FE_AG_REG_AG_MODE_LOP_MODE_E__M)); - AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | - FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); - status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); - if (status < 0) - break; - - /* enable AGC2 pin */ - { - u16 FeAgRegAgAgcSio = 0; - status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); - if (status < 0) - break; - FeAgRegAgAgcSio &= - ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); - FeAgRegAgAgcSio |= - FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; - status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); - if (status < 0) - break; - } - - } while (0); - } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { - u16 AgModeLop = 0; - - do { - u16 level; - /* Automatic control */ - /* Powerup PD2, AGC2 as output, TGC source */ - (state->m_FeAgRegAgPwd) &= - ~(FE_AG_REG_AG_PWD_PWD_PD2__M); - (state->m_FeAgRegAgPwd) |= - FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; - status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); - if (status < 0) - break; - - status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); - if (status < 0) - break; - AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | - FE_AG_REG_AG_MODE_LOP_MODE_E__M)); - AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | - FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC); - status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); - if (status < 0) - break; - /* Settle level */ - level = (((cfg->settleLevel) >> 4) & - FE_AG_REG_TGC_SET_LVL__M); - status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); - if (status < 0) - break; - - /* Min/max: don't care */ - - /* Speed: TODO */ - - /* enable AGC2 pin */ - { - u16 FeAgRegAgAgcSio = 0; - status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); - if (status < 0) - break; - FeAgRegAgAgcSio &= - ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); - FeAgRegAgAgcSio |= - FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; - status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); - if (status < 0) - break; - } - - } while (0); - } else { - u16 AgModeLop = 0; - - do { - /* No RF AGC control */ - /* Powerdown PD2, AGC2 as output, WRI source */ - (state->m_FeAgRegAgPwd) &= - ~(FE_AG_REG_AG_PWD_PWD_PD2__M); - (state->m_FeAgRegAgPwd) |= - FE_AG_REG_AG_PWD_PWD_PD2_ENABLE; - status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); - if (status < 0) - break; - - status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); - if (status < 0) - break; - AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | - FE_AG_REG_AG_MODE_LOP_MODE_E__M)); - AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | - FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); - status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); - if (status < 0) - break; - - /* set FeAgRegAgAgcSio AGC2 (RF) as input */ - { - u16 FeAgRegAgAgcSio = 0; - status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); - if (status < 0) - break; - FeAgRegAgAgcSio &= - ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); - FeAgRegAgAgcSio |= - FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT; - status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); - if (status < 0) - break; - } - } while (0); - } - return status; -} - -static int ReadIFAgc(struct drxd_state *state, u32 * pValue) -{ - int status = 0; - - *pValue = 0; - if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { - u16 Value; - status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); - Value &= FE_AG_REG_GC1_AGC_DAT__M; - if (status >= 0) { - /* 3.3V - | - R1 - | - Vin - R3 - * -- Vout - | - R2 - | - GND - */ - u32 R1 = state->if_agc_cfg.R1; - u32 R2 = state->if_agc_cfg.R2; - u32 R3 = state->if_agc_cfg.R3; - - u32 Vmax, Rpar, Vmin, Vout; - - if (R2 == 0 && (R1 == 0 || R3 == 0)) - return 0; - - Vmax = (3300 * R2) / (R1 + R2); - Rpar = (R2 * R3) / (R3 + R2); - Vmin = (3300 * Rpar) / (R1 + Rpar); - Vout = Vmin + ((Vmax - Vmin) * Value) / 1024; - - *pValue = Vout; - } - } - return status; -} - -static int load_firmware(struct drxd_state *state, const char *fw_name) -{ - const struct firmware *fw; - - if (request_firmware(&fw, fw_name, state->dev) < 0) { - printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name); - return -EIO; - } - - state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); - if (state->microcode == NULL) { - release_firmware(fw); - printk(KERN_ERR "drxd: firmware load failure: no memory\n"); - return -ENOMEM; - } - - state->microcode_length = fw->size; - release_firmware(fw); - return 0; -} - -static int DownloadMicrocode(struct drxd_state *state, - const u8 *pMCImage, u32 Length) -{ - u8 *pSrc; - u32 Address; - u16 nBlocks; - u16 BlockSize; - u32 offset = 0; - int i, status = 0; - - pSrc = (u8 *) pMCImage; - /* We're not using Flags */ - /* Flags = (pSrc[0] << 8) | pSrc[1]; */ - pSrc += sizeof(u16); - offset += sizeof(u16); - nBlocks = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); - offset += sizeof(u16); - - for (i = 0; i < nBlocks; i++) { - Address = (pSrc[0] << 24) | (pSrc[1] << 16) | - (pSrc[2] << 8) | pSrc[3]; - pSrc += sizeof(u32); - offset += sizeof(u32); - - BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); - pSrc += sizeof(u16); - offset += sizeof(u16); - - /* We're not using Flags */ - /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */ - pSrc += sizeof(u16); - offset += sizeof(u16); - - /* We're not using BlockCRC */ - /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */ - pSrc += sizeof(u16); - offset += sizeof(u16); - - status = WriteBlock(state, Address, BlockSize, - pSrc, DRX_I2C_CLEARCRC); - if (status < 0) - break; - pSrc += BlockSize; - offset += BlockSize; - } - - return status; -} - -static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) -{ - u32 nrRetries = 0; - u16 waitCmd; - int status; - - status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); - if (status < 0) - return status; - - do { - nrRetries += 1; - if (nrRetries > DRXD_MAX_RETRIES) { - status = -1; - break; - }; - status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); - } while (waitCmd != 0); - - if (status >= 0) - status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); - return status; -} - -static int HI_CfgCommand(struct drxd_state *state) -{ - int status = 0; - - mutex_lock(&state->mutex); - Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); - Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); - Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); - Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); - Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); - - Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); - - if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == - HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) - status = Write16(state, HI_RA_RAM_SRV_CMD__A, - HI_RA_RAM_SRV_CMD_CONFIG, 0); - else - status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0); - mutex_unlock(&state->mutex); - return status; -} - -static int InitHI(struct drxd_state *state) -{ - state->hi_cfg_wakeup_key = (state->chip_adr); - /* port/bridge/power down ctrl */ - state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; - return HI_CfgCommand(state); -} - -static int HI_ResetCommand(struct drxd_state *state) -{ - int status; - - mutex_lock(&state->mutex); - status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, - HI_RA_RAM_SRV_RST_KEY_ACT, 0); - if (status == 0) - status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0); - mutex_unlock(&state->mutex); - msleep(1); - return status; -} - -static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) -{ - state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); - if (bEnableBridge) - state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; - else - state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; - - return HI_CfgCommand(state); -} - -#define HI_TR_WRITE 0x9 -#define HI_TR_READ 0xA -#define HI_TR_READ_WRITE 0xB -#define HI_TR_BROADCAST 0x4 - -#if 0 -static int AtomicReadBlock(struct drxd_state *state, - u32 Addr, u16 DataSize, u8 *pData, u8 Flags) -{ - int status; - int i = 0; - - /* Parameter check */ - if ((!pData) || ((DataSize & 1) != 0)) - return -1; - - mutex_lock(&state->mutex); - - do { - /* Instruct HI to read n bytes */ - /* TODO use proper names forthese egisters */ - status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0); - if (status < 0) - break; - status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0); - if (status < 0) - break; - status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0); - if (status < 0) - break; - status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0); - if (status < 0) - break; - status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0); - if (status < 0) - break; - - status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0); - if (status < 0) - break; - - } while (0); - - if (status >= 0) { - for (i = 0; i < (DataSize / 2); i += 1) { - u16 word; - - status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i), - &word, 0); - if (status < 0) - break; - pData[2 * i] = (u8) (word & 0xFF); - pData[(2 * i) + 1] = (u8) (word >> 8); - } - } - mutex_unlock(&state->mutex); - return status; -} - -static int AtomicReadReg32(struct drxd_state *state, - u32 Addr, u32 *pData, u8 Flags) -{ - u8 buf[sizeof(u32)]; - int status; - - if (!pData) - return -1; - status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags); - *pData = (((u32) buf[0]) << 0) + - (((u32) buf[1]) << 8) + - (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); - return status; -} -#endif - -static int StopAllProcessors(struct drxd_state *state) -{ - return Write16(state, HI_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST); -} - -static int EnableAndResetMB(struct drxd_state *state) -{ - if (state->type_A) { - /* disable? monitor bus observe @ EC_OC */ - Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000); - } - - /* do inverse broadcast, followed by explicit write to HI */ - Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST); - Write16(state, HI_COMM_MB__A, 0x0000, 0x0000); - return 0; -} - -static int InitCC(struct drxd_state *state) -{ - if (state->osc_clock_freq == 0 || - state->osc_clock_freq > 20000 || - (state->osc_clock_freq % 4000) != 0) { - printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); - return -1; - } - - Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); - Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | - CC_REG_PLL_MODE_PUMP_CUR_12, 0); - Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0); - Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); - Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); - - return 0; -} - -static int ResetECOD(struct drxd_state *state) -{ - int status = 0; - - if (state->type_A) - status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); - else - status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); - - if (!(status < 0)) - status = WriteTable(state, state->m_ResetECRAM); - if (!(status < 0)) - status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); - return status; -} - -/* Configure PGA switch */ - -static int SetCfgPga(struct drxd_state *state, int pgaSwitch) -{ - int status; - u16 AgModeLop = 0; - u16 AgModeHip = 0; - do { - if (pgaSwitch) { - /* PGA on */ - /* fine gain */ - status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); - if (status < 0) - break; - AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); - AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC; - status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); - if (status < 0) - break; - - /* coarse gain */ - status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); - if (status < 0) - break; - AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); - AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC; - status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); 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