diff options
Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 113 |
1 files changed, 64 insertions, 49 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index cd3d23d2c6a2..3f39e020f74e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> +#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> #include <dt-bindings/reset/amlogic,meson-g12a-reset.h> / { @@ -98,8 +99,8 @@ compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000 - 0x0 0xff634540 0x0 0x8>; + reg = <0x0 0xff3f0000 0x0 0x10000>, + <0x0 0xff634540 0x0 0x8>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; clocks = <&clkc CLKID_ETH>, @@ -1406,6 +1407,53 @@ clocks = <&xtal>; clock-names = "xtal"; }; + + pwrc: power-controller { + compatible = "amlogic,meson-g12a-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&rti>; + resets = <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_VCBUS>, + <&reset RESET_BT656>, + <&reset RESET_RDMA>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC>, + <&reset RESET_VDI6>, + <&reset RESET_VENCL>, + <&reset RESET_VID_LOCK>; + reset-names = "viu", "venc", "vcbus", "bt656", + "rdma", "venci", "vencp", "vdac", + "vdi6", "vencl", "vid_lock"; + clocks = <&clkc CLKID_VPU>, + <&clkc CLKID_VAPB>; + clock-names = "vpu", "vapb"; + /* + * VPU clocking is provided by two identical clock paths + * VPU_0 and VPU_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + * Same for VAPB but with a final gate after the glitch free mux. + */ + assigned-clocks = <&clkc CLKID_VPU_0_SEL>, + <&clkc CLKID_VPU_0>, + <&clkc CLKID_VPU>, /* Glitch free mux */ + <&clkc CLKID_VAPB_0_SEL>, + <&clkc CLKID_VAPB_0>, + <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, /* Do Nothing */ + <&clkc CLKID_VPU_0>, + <&clkc CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc CLKID_VAPB_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <666666666>, + <0>, /* Do Nothing */ + <0>, /* Do Nothing */ + <250000000>, + <0>; /* Do Nothing */ + }; }; }; @@ -1434,6 +1482,7 @@ compatible = "amlogic,g12a-audio-clkc"; reg = <0x0 0x0 0x0 0xb4>; #clock-cells = <1>; + #reset-cells = <1>; clocks = <&clkc CLKID_AUDIO>, <&clkc CLKID_MPLL0>, @@ -1542,6 +1591,7 @@ "amlogic,axg-tdmin"; reg = <0x0 0x300 0x0 0x40>; sound-name-prefix = "TDMIN_A"; + resets = <&clkc_audio AUD_RESET_TDMIN_A>; clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, @@ -1557,6 +1607,7 @@ "amlogic,axg-tdmin"; reg = <0x0 0x340 0x0 0x40>; sound-name-prefix = "TDMIN_B"; + resets = <&clkc_audio AUD_RESET_TDMIN_B>; clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, @@ -1572,6 +1623,7 @@ "amlogic,axg-tdmin"; reg = <0x0 0x380 0x0 0x40>; sound-name-prefix = "TDMIN_C"; + resets = <&clkc_audio AUD_RESET_TDMIN_C>; clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, @@ -1587,6 +1639,7 @@ "amlogic,axg-tdmin"; reg = <0x0 0x3c0 0x0 0x40>; sound-name-prefix = "TDMIN_LB"; + resets = <&clkc_audio AUD_RESET_TDMIN_LB>; clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, @@ -1626,6 +1679,7 @@ compatible = "amlogic,g12a-tdmout"; reg = <0x0 0x500 0x0 0x40>; sound-name-prefix = "TDMOUT_A"; + resets = <&clkc_audio AUD_RESET_TDMOUT_A>; clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, @@ -1640,6 +1694,7 @@ compatible = "amlogic,g12a-tdmout"; reg = <0x0 0x540 0x0 0x40>; sound-name-prefix = "TDMOUT_B"; + resets = <&clkc_audio AUD_RESET_TDMOUT_B>; clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, @@ -1654,6 +1709,7 @@ compatible = "amlogic,g12a-tdmout"; reg = <0x0 0x580 0x0 0x40>; sound-name-prefix = "TDMOUT_C"; + resets = <&clkc_audio AUD_RESET_TDMOUT_C>; clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, @@ -1753,50 +1809,6 @@ clock-names = "xtal", "mpeg-clk"; }; - pwrc_vpu: power-controller-vpu { - compatible = "amlogic,meson-g12a-pwrc-vpu"; - #power-domain-cells = <0>; - amlogic,hhi-sysctrl = <&hhi>; - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ - }; - ao_pinctrl: pinctrl@14 { compatible = "amlogic,meson-g12a-aobus-pinctrl"; #address-cells = <2>; @@ -2045,6 +2057,11 @@ }; }; + vrtc: rtc@0a8 { + compatible = "amlogic,meson-vrtc"; + reg = <0x0 0x000a8 0x0 0x4>; + }; + cec_AO: cec@100 { compatible = "amlogic,meson-gx-ao-cec"; reg = <0x0 0x00100 0x0 0x14>; @@ -2144,7 +2161,6 @@ #address-cells = <1>; #size-cells = <0>; amlogic,canvas = <&canvas>; - power-domains = <&pwrc_vpu>; /* CVBS VDAC output port */ cvbs_vdac_port: port@0 { @@ -2182,8 +2198,7 @@ ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; reset: reset-controller@1004 { - compatible = "amlogic,meson-g12a-reset", - "amlogic,meson-axg-reset"; + compatible = "amlogic,meson-axg-reset"; reg = <0x0 0x1004 0x0 0x9c>; #reset-cells = <1>; }; |