diff options
Diffstat (limited to 'arch/arm/mach-mxs')
-rw-r--r-- | arch/arm/mach-mxs/Makefile | 4 | ||||
-rw-r--r-- | arch/arm/mach-mxs/icoll.c | 125 | ||||
-rw-r--r-- | arch/arm/mach-mxs/include/mach/common.h | 29 | ||||
-rw-r--r-- | arch/arm/mach-mxs/include/mach/debug-macro.S | 9 | ||||
-rw-r--r-- | arch/arm/mach-mxs/include/mach/digctl.h | 22 | ||||
-rw-r--r-- | arch/arm/mach-mxs/include/mach/hardware.h | 23 | ||||
-rw-r--r-- | arch/arm/mach-mxs/include/mach/mx23.h | 169 | ||||
-rw-r--r-- | arch/arm/mach-mxs/include/mach/mx28.h | 225 | ||||
-rw-r--r-- | arch/arm/mach-mxs/include/mach/mxs.h | 117 | ||||
-rw-r--r-- | arch/arm/mach-mxs/mach-mxs.c | 185 | ||||
-rw-r--r-- | arch/arm/mach-mxs/mm.c | 52 | ||||
-rw-r--r-- | arch/arm/mach-mxs/ocotp.c | 93 | ||||
-rw-r--r-- | arch/arm/mach-mxs/system.c | 139 | ||||
-rw-r--r-- | arch/arm/mach-mxs/timer.c | 306 |
14 files changed, 159 insertions, 1339 deletions
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 3d3c8a973062..80db7269760e 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -1,6 +1,2 @@ -# Common support -obj-y := icoll.o ocotp.o system.o timer.o mm.o - obj-$(CONFIG_PM) += pm.o - obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c deleted file mode 100644 index e26eeba46598..000000000000 --- a/arch/arm/mach-mxs/icoll.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_irq.h> -#include <asm/exception.h> -#include <mach/mxs.h> -#include <mach/common.h> - -#define HW_ICOLL_VECTOR 0x0000 -#define HW_ICOLL_LEVELACK 0x0010 -#define HW_ICOLL_CTRL 0x0020 -#define HW_ICOLL_STAT_OFFSET 0x0070 -#define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10) -#define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10) -#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 -#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 - -#define ICOLL_NUM_IRQS 128 - -static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR); -static struct irq_domain *icoll_domain; - -static void icoll_ack_irq(struct irq_data *d) -{ - /* - * The Interrupt Collector is able to prioritize irqs. - * Currently only level 0 is used. So acking can use - * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally. - */ - __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, - icoll_base + HW_ICOLL_LEVELACK); -} - -static void icoll_mask_irq(struct irq_data *d) -{ - __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, - icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq)); -} - -static void icoll_unmask_irq(struct irq_data *d) -{ - __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, - icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq)); -} - -static struct irq_chip mxs_icoll_chip = { - .irq_ack = icoll_ack_irq, - .irq_mask = icoll_mask_irq, - .irq_unmask = icoll_unmask_irq, -}; - -asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) -{ - u32 irqnr; - - do { - irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET); - if (irqnr != 0x7f) { - __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR); - irqnr = irq_find_mapping(icoll_domain, irqnr); - handle_IRQ(irqnr, regs); - continue; - } - break; - } while (1); -} - -static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq, - irq_hw_number_t hw) -{ - irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq); - set_irq_flags(virq, IRQF_VALID); - - return 0; -} - -static struct irq_domain_ops icoll_irq_domain_ops = { - .map = icoll_irq_domain_map, - .xlate = irq_domain_xlate_onecell, -}; - -static void __init icoll_of_init(struct device_node *np, - struct device_node *interrupt_parent) -{ - /* - * Interrupt Collector reset, which initializes the priority - * for each irq to level 0. - */ - mxs_reset_block(icoll_base + HW_ICOLL_CTRL); - - icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS, - &icoll_irq_domain_ops, NULL); - WARN_ON(!icoll_domain); -} - -static const struct of_device_id icoll_of_match[] __initconst = { - {.compatible = "fsl,icoll", .data = icoll_of_init}, - { /* sentinel */ } -}; - -void __init icoll_init_irq(void) -{ - of_irq_init(icoll_of_match); -} diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h deleted file mode 100644 index be5a9c93cb2a..000000000000 --- a/arch/arm/mach-mxs/include/mach/common.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_MXS_COMMON_H__ -#define __MACH_MXS_COMMON_H__ - -extern const u32 *mxs_get_ocotp(void); -extern int mxs_reset_block(void __iomem *); -extern void mxs_timer_init(void); -extern void mxs_restart(char, const char *); -extern int mxs_saif_clkmux_select(unsigned int clkmux); - -extern int mx23_clocks_init(void); -extern void mx23_map_io(void); - -extern int mx28_clocks_init(void); -extern void mx28_map_io(void); - -extern void icoll_init_irq(void); -extern void icoll_handle_irq(struct pt_regs *); - -#endif /* __MACH_MXS_COMMON_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S index 90c6b7836ad3..d86951551ca1 100644 --- a/arch/arm/mach-mxs/include/mach/debug-macro.S +++ b/arch/arm/mach-mxs/include/mach/debug-macro.S @@ -11,16 +11,13 @@ * */ -#include <mach/mx23.h> -#include <mach/mx28.h> - #ifdef CONFIG_DEBUG_IMX23_UART -#define UART_PADDR MX23_DUART_BASE_ADDR +#define UART_PADDR 0x80070000 #elif defined (CONFIG_DEBUG_IMX28_UART) -#define UART_PADDR MX28_DUART_BASE_ADDR +#define UART_PADDR 0x80074000 #endif -#define UART_VADDR MXS_IO_ADDRESS(UART_PADDR) +#define UART_VADDR 0xfe100000 .macro addruart, rp, rv, tmp ldr \rp, =UART_PADDR @ physical diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h deleted file mode 100644 index 17964066303f..000000000000 --- a/arch/arm/mach-mxs/include/mach/digctl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_DIGCTL_H__ -#define __MACH_DIGCTL_H__ - -/* MXS DIGCTL SAIF CLKMUX */ -#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0 -#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1 -#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 -#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 - -#define HW_DIGCTL_CTRL 0x0 -#define BP_DIGCTL_CTRL_SAIF_CLKMUX 10 -#define BM_DIGCTL_CTRL_SAIF_CLKMUX (0x3 << 10) -#define HW_DIGCTL_CHIPID 0x310 -#endif diff --git a/arch/arm/mach-mxs/include/mach/hardware.h b/arch/arm/mach-mxs/include/mach/hardware.h deleted file mode 100644 index 4c0e8a64d8c7..000000000000 --- a/arch/arm/mach-mxs/include/mach/hardware.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_MXS_HARDWARE_H__ -#define __MACH_MXS_HARDWARE_H__ - -#endif /* __MACH_MXS_HARDWARE_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h deleted file mode 100644 index 599094bc99de..000000000000 --- a/arch/arm/mach-mxs/include/mach/mx23.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef __MACH_MX23_H__ -#define __MACH_MX23_H__ - -#include <mach/mxs.h> - -/* - * OCRAM - */ -#define MX23_OCRAM_BASE_ADDR 0x00000000 -#define MX23_OCRAM_SIZE SZ_32K - -/* - * IO - */ -#define MX23_IO_BASE_ADDR 0x80000000 -#define MX23_IO_SIZE SZ_1M - -#define MX23_ICOLL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x000000) -#define MX23_APBH_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x004000) -#define MX23_BCH_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00a000) -#define MX23_GPMI_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00c000) -#define MX23_SSP1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x010000) -#define MX23_PINCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x018000) -#define MX23_DIGCTL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x01c000) -#define MX23_ETM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x020000) -#define MX23_APBX_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x024000) -#define MX23_DCP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x028000) -#define MX23_PXP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02a000) -#define MX23_OCOTP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02c000) -#define MX23_AXI_AHB0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02e000) -#define MX23_LCDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x030000) -#define MX23_SSP2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x034000) -#define MX23_TVENC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x038000) -#define MX23_CLKCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x040000) -#define MX23_SAIF0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x042000) -#define MX23_POWER_BASE_ADDR (MX23_IO_BASE_ADDR + 0x044000) -#define MX23_SAIF1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x046000) -#define MX23_AUDIOOUT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x048000) -#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000) -#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000) -#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000) -#define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000) -#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000) -#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000) -#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000) -#define MX23_AUART1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06c000) -#define MX23_AUART2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06e000) -#define MX23_DUART_BASE_ADDR (MX23_IO_BASE_ADDR + 0x070000) -#define MX23_USBPHY_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07c000) -#define MX23_USBCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x080000) -#define MX23_DRAM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x0e0000) - -#define MX23_IO_P2V(x) MXS_IO_P2V(x) -#define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x)) - -/* - * IRQ - */ -#define MX23_INT_DUART 0 -#define MX23_INT_COMMS_RX 1 -#define MX23_INT_COMMS_TX 1 -#define MX23_INT_SSP2_ERROR 2 -#define MX23_INT_VDD5V 3 -#define MX23_INT_HEADPHONE_SHORT 4 -#define MX23_INT_DAC_DMA 5 -#define MX23_INT_DAC_ERROR 6 -#define MX23_INT_ADC_DMA 7 -#define MX23_INT_ADC_ERROR 8 -#define MX23_INT_SPDIF_DMA 9 -#define MX23_INT_SAIF2_DMA 9 -#define MX23_INT_SPDIF_ERROR 10 -#define MX23_INT_SAIF1_IRQ 10 -#define MX23_INT_SAIF2_IRQ 10 -#define MX23_INT_USB_CTRL 11 -#define MX23_INT_USB_WAKEUP 12 -#define MX23_INT_GPMI_DMA 13 -#define MX23_INT_SSP1_DMA 14 -#define MX23_INT_SSP1_ERROR 15 -#define MX23_INT_GPIO0 16 -#define MX23_INT_GPIO1 17 -#define MX23_INT_GPIO2 18 -#define MX23_INT_SAIF1_DMA 19 -#define MX23_INT_SSP2_DMA 20 -#define MX23_INT_ECC8_IRQ 21 -#define MX23_INT_RTC_ALARM 22 -#define MX23_INT_AUART1_TX_DMA 23 -#define MX23_INT_AUART1 24 -#define MX23_INT_AUART1_RX_DMA 25 -#define MX23_INT_I2C_DMA 26 -#define MX23_INT_I2C_ERROR 27 -#define MX23_INT_TIMER0 28 -#define MX23_INT_TIMER1 29 -#define MX23_INT_TIMER2 30 -#define MX23_INT_TIMER3 31 -#define MX23_INT_BATT_BRNOUT 32 -#define MX23_INT_VDDD_BRNOUT 33 -#define MX23_INT_VDDIO_BRNOUT 34 -#define MX23_INT_VDD18_BRNOUT 35 -#define MX23_INT_TOUCH_DETECT 36 -#define MX23_INT_LRADC_CH0 37 -#define MX23_INT_LRADC_CH1 38 -#define MX23_INT_LRADC_CH2 39 -#define MX23_INT_LRADC_CH3 40 -#define MX23_INT_LRADC_CH4 41 -#define MX23_INT_LRADC_CH5 42 -#define MX23_INT_LRADC_CH6 43 -#define MX23_INT_LRADC_CH7 44 -#define MX23_INT_LCDIF_DMA 45 -#define MX23_INT_LCDIF_ERROR 46 -#define MX23_INT_DIGCTL_DEBUG_TRAP 47 -#define MX23_INT_RTC_1MSEC 48 -#define MX23_INT_DRI_DMA 49 -#define MX23_INT_DRI_ATTENTION 50 -#define MX23_INT_GPMI_ATTENTION 51 -#define MX23_INT_IR 52 -#define MX23_INT_DCP_VMI 53 -#define MX23_INT_DCP 54 -#define MX23_INT_BCH 56 -#define MX23_INT_PXP 57 -#define MX23_INT_AUART2_TX_DMA 58 -#define MX23_INT_AUART2 59 -#define MX23_INT_AUART2_RX_DMA 60 -#define MX23_INT_VDAC_DETECT 61 -#define MX23_INT_VDD5V_DROOP 64 -#define MX23_INT_DCDC4P2_BO 65 - -/* - * APBH DMA - */ -#define MX23_DMA_SSP1 1 -#define MX23_DMA_SSP2 2 -#define MX23_DMA_GPMI0 4 -#define MX23_DMA_GPMI1 5 -#define MX23_DMA_GPMI2 6 -#define MX23_DMA_GPMI3 7 - -/* - * APBX DMA - */ -#define MX23_DMA_ADC 0 -#define MX23_DMA_DAC 1 -#define MX23_DMA_SPDIF 2 -#define MX23_DMA_I2C 3 -#define MX23_DMA_SAIF0 4 -#define MX23_DMA_UART0_RX 6 -#define MX23_DMA_UART0_TX 7 -#define MX23_DMA_UART1_RX 8 -#define MX23_DMA_UART1_TX 9 -#define MX23_DMA_SAIF1 10 - -#endif /* __MACH_MX23_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h deleted file mode 100644 index 30c7990f3c01..000000000000 --- a/arch/arm/mach-mxs/include/mach/mx28.h +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef __MACH_MX28_H__ -#define __MACH_MX28_H__ - -#include <mach/mxs.h> - -/* - * OCRAM - */ -#define MX28_OCRAM_BASE_ADDR 0x00000000 -#define MX28_OCRAM_SIZE SZ_128K - -/* - * IO - */ -#define MX28_IO_BASE_ADDR 0x80000000 -#define MX28_IO_SIZE SZ_1M - -#define MX28_ICOLL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x000000) -#define MX28_HSADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x002000) -#define MX28_APBH_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x004000) -#define MX28_PERFMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x006000) -#define MX28_BCH_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00a000) -#define MX28_GPMI_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00c000) -#define MX28_SSP0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x010000) -#define MX28_SSP1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x012000) -#define MX28_SSP2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x014000) -#define MX28_SSP3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x016000) -#define MX28_PINCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x018000) -#define MX28_DIGCTL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x01c000) -#define MX28_ETM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x022000) -#define MX28_APBX_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x024000) -#define MX28_DCP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x028000) -#define MX28_PXP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02a000) -#define MX28_OCOTP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02c000) -#define MX28_AXI_AHB0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02e000) -#define MX28_LCDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x030000) -#define MX28_CAN0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x032000) -#define MX28_CAN1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x034000) -#define MX28_SIMDBG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c000) -#define MX28_SIMGPMISEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c200) -#define MX28_SIMSSPSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c300) -#define MX28_SIMMEMSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c400) -#define MX28_GPIOMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c500) -#define MX28_SIMENET_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c700) -#define MX28_ARMJTAG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c800) -#define MX28_CLKCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x040000) -#define MX28_SAIF0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x042000) -#define MX28_POWER_BASE_ADDR (MX28_IO_BASE_ADDR + 0x044000) -#define MX28_SAIF1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x046000) -#define MX28_LRADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x050000) -#define MX28_SPDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x054000) -#define MX28_RTC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x056000) -#define MX28_I2C0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x058000) -#define MX28_I2C1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x05a000) -#define MX28_PWM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x064000) -#define MX28_TIMROT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x068000) -#define MX28_AUART0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06a000) -#define MX28_AUART1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06c000) -#define MX28_AUART2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06e000) -#define MX28_AUART3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x070000) -#define MX28_AUART4_BASE_ADDR (MX28_IO_BASE_ADDR + 0x072000) -#define MX28_DUART_BASE_ADDR (MX28_IO_BASE_ADDR + 0x074000) -#define MX28_USBPHY0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07C000) -#define MX28_USBPHY1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07e000) -#define MX28_USBCTRL0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x080000) -#define MX28_USBCTRL1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x090000) -#define MX28_DFLPT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0c0000) -#define MX28_DRAM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0e0000) -#define MX28_ENET_MAC0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f0000) -#define MX28_ENET_MAC1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f4000) - -#define MX28_IO_P2V(x) MXS_IO_P2V(x) -#define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x)) - -/* - * IRQ - */ -#define MX28_INT_BATT_BRNOUT 0 -#define MX28_INT_VDDD_BRNOUT 1 -#define MX28_INT_VDDIO_BRNOUT 2 -#define MX28_INT_VDDA_BRNOUT 3 -#define MX28_INT_VDD5V_DROOP 4 -#define MX28_INT_DCDC4P2_BRNOUT 5 -#define MX28_INT_VDD5V 6 -#define MX28_INT_CAN0 8 -#define MX28_INT_CAN1 9 -#define MX28_INT_LRADC_TOUCH 10 -#define MX28_INT_HSADC 13 -#define MX28_INT_LRADC_THRESH0 14 -#define MX28_INT_LRADC_THRESH1 15 -#define MX28_INT_LRADC_CH0 16 -#define MX28_INT_LRADC_CH1 17 -#define MX28_INT_LRADC_CH2 18 -#define MX28_INT_LRADC_CH3 19 -#define MX28_INT_LRADC_CH4 20 -#define MX28_INT_LRADC_CH5 21 -#define MX28_INT_LRADC_CH6 22 -#define MX28_INT_LRADC_CH7 23 -#define MX28_INT_LRADC_BUTTON0 24 -#define MX28_INT_LRADC_BUTTON1 25 -#define MX28_INT_PERFMON 27 -#define MX28_INT_RTC_1MSEC 28 -#define MX28_INT_RTC_ALARM 29 -#define MX28_INT_COMMS 31 -#define MX28_INT_EMI_ERR 32 -#define MX28_INT_LCDIF 38 -#define MX28_INT_PXP 39 -#define MX28_INT_BCH 41 -#define MX28_INT_GPMI 42 -#define MX28_INT_SPDIF_ERROR 45 -#define MX28_INT_DUART 47 -#define MX28_INT_TIMER0 48 -#define MX28_INT_TIMER1 49 -#define MX28_INT_TIMER2 50 -#define MX28_INT_TIMER3 51 -#define MX28_INT_DCP_VMI 52 -#define MX28_INT_DCP 53 -#define MX28_INT_DCP_SECURE 54 -#define MX28_INT_SAIF1 58 -#define MX28_INT_SAIF0 59 -#define MX28_INT_SPDIF_DMA 66 -#define MX28_INT_I2C0_DMA 68 -#define MX28_INT_I2C1_DMA 69 -#define MX28_INT_AUART0_RX_DMA 70 -#define MX28_INT_AUART0_TX_DMA 71 -#define MX28_INT_AUART1_RX_DMA 72 -#define MX28_INT_AUART1_TX_DMA 73 -#define MX28_INT_AUART2_RX_DMA 74 -#define MX28_INT_AUART2_TX_DMA 75 -#define MX28_INT_AUART3_RX_DMA 76 -#define MX28_INT_AUART3_TX_DMA 77 -#define MX28_INT_AUART4_RX_DMA 78 -#define MX28_INT_AUART4_TX_DMA 79 -#define MX28_INT_SAIF0_DMA 80 -#define MX28_INT_SAIF1_DMA 81 -#define MX28_INT_SSP0_DMA 82 -#define MX28_INT_SSP1_DMA 83 -#define MX28_INT_SSP2_DMA 84 -#define MX28_INT_SSP3_DMA 85 -#define MX28_INT_LCDIF_DMA 86 -#define MX28_INT_HSADC_DMA 87 -#define MX28_INT_GPMI_DMA 88 -#define MX28_INT_DIGCTL_DEBUG_TRAP 89 -#define MX28_INT_USB1 92 -#define MX28_INT_USB0 93 -#define MX28_INT_USB1_WAKEUP 94 -#define MX28_INT_USB0_WAKEUP 95 -#define MX28_INT_SSP0_ERROR 96 -#define MX28_INT_SSP1_ERROR 97 -#define MX28_INT_SSP2_ERROR 98 -#define MX28_INT_SSP3_ERROR 99 -#define MX28_INT_ENET_SWI 100 -#define MX28_INT_ENET_MAC0 101 -#define MX28_INT_ENET_MAC1 102 -#define MX28_INT_ENET_MAC0_1588 103 -#define MX28_INT_ENET_MAC1_1588 104 -#define MX28_INT_I2C1_ERROR 110 -#define MX28_INT_I2C0_ERROR 111 -#define MX28_INT_AUART0 112 -#define MX28_INT_AUART1 113 -#define MX28_INT_AUART2 114 -#define MX28_INT_AUART3 115 -#define MX28_INT_AUART4 116 -#define MX28_INT_GPIO4 123 -#define MX28_INT_GPIO3 124 -#define MX28_INT_GPIO2 125 -#define MX28_INT_GPIO1 126 -#define MX28_INT_GPIO0 127 - -/* - * APBH DMA - */ -#define MX28_DMA_SSP0 0 -#define MX28_DMA_SSP1 1 -#define MX28_DMA_SSP2 2 -#define MX28_DMA_SSP3 3 -#define MX28_DMA_GPMI0 4 -#define MX28_DMA_GPMI1 5 -#define MX28_DMA_GPMI2 6 -#define MX28_DMA_GPMI3 7 -#define MX28_DMA_GPMI4 8 -#define MX28_DMA_GPMI5 9 -#define MX28_DMA_GPMI6 10 -#define MX28_DMA_GPMI7 11 -#define MX28_DMA_HSADC 12 -#define MX28_DMA_LCDIF 13 - -/* - * APBX DMA - */ -#define MX28_DMA_AUART4_RX 0 -#define MX28_DMA_AUART4_TX 1 -#define MX28_DMA_SPDIF_TX 2 -#define MX28_DMA_SAIF0 4 -#define MX28_DMA_SAIF1 5 -#define MX28_DMA_I2C0 6 -#define MX28_DMA_I2C1 7 -#define MX28_DMA_AUART0_RX 8 -#define MX28_DMA_AUART0_TX 9 -#define MX28_DMA_AUART1_RX 10 -#define MX28_DMA_AUART1_TX 11 -#define MX28_DMA_AUART2_RX 12 -#define MX28_DMA_AUART2_TX 13 -#define MX28_DMA_AUART3_RX 14 -#define MX28_DMA_AUART3_TX 15 - -#endif /* __MACH_MX28_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h deleted file mode 100644 index 7d4fb6d0afda..000000000000 --- a/arch/arm/mach-mxs/include/mach/mxs.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef __MACH_MXS_H__ -#define __MACH_MXS_H__ - -#ifndef __ASSEMBLER__ -#include <linux/io.h> -#endif -#include <asm/mach-types.h> -#include <mach/digctl.h> -#include <mach/hardware.h> - -/* - * IO addresses common to MXS-based - */ -#define MXS_IO_BASE_ADDR 0x80000000 -#define MXS_IO_SIZE SZ_1M - -#define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000) -#define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000) -#define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000) -#define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000) -#define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000) -#define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000) -#define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000) -#define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000) -#define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000) -#define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000) -#define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000) -#define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000) -#define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000) -#define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000) -#define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000) -#define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000) -#define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000) -#define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000) -#define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000) -#define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000) -#define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000) -#define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000) -#define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000) -#define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000) - -/* - * It maps the whole address space to [0xf4000000, 0xf50fffff]. - * - * OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000 - * IO 0x80000000+0x100000 -> 0xf5000000+0x100000 - */ -#define MXS_IO_P2V(x) (0xf4000000 + \ - (((x) & 0x80000000) >> 7) + \ - (((x) & 0x000fffff))) - -#define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x)) - -#define mxs_map_entry(soc, name, _type) { \ - .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ - .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ - .length = soc ## _ ## name ## _SIZE, \ - .type = _type, \ -} - -#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) - -#define MXS_SET_ADDR 0x4 -#define MXS_CLR_ADDR 0x8 -#define MXS_TOG_ADDR 0xc - -#ifndef __ASSEMBLER__ -static inline void __mxs_setl(u32 mask, void __iomem *reg) -{ - __raw_writel(mask, reg + MXS_SET_ADDR); -} - -static inline void __mxs_clrl(u32 mask, void __iomem *reg) -{ - __raw_writel(mask, reg + MXS_CLR_ADDR); -} - -static inline void __mxs_togl(u32 mask, void __iomem *reg) -{ - __raw_writel(mask, reg + MXS_TOG_ADDR); -} - -/* - * MXS CPU types - */ -#define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID) - -static inline int cpu_is_mx23(void) -{ - return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780); -} - -static inline int cpu_is_mx28(void) -{ - return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800); -} -#endif - -#endif /* __MACH_MXS_H__ */ diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index e7b781d3788f..16870bf853b8 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -11,22 +11,53 @@ */ #include <linux/clk.h> +#include <linux/clk/mxs.h> #include <linux/clkdev.h> +#include <linux/clocksource.h> #include <linux/can/platform/flexcan.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/gpio.h> #include <linux/init.h> +#include <linux/irqchip.h> +#include <linux/irqchip/mxs.h> #include <linux/micrel_phy.h> #include <linux/mxsfb.h> +#include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/phy.h> #include <linux/pinctrl/consumer.h> #include <asm/mach/arch.h> +#include <asm/mach/map.h> #include <asm/mach/time.h> -#include <mach/common.h> -#include <mach/digctl.h> -#include <mach/mxs.h> +#include <asm/system_misc.h> + +/* MXS DIGCTL SAIF CLKMUX */ +#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0 +#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1 +#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 +#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 + +#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) + +#define MXS_SET_ADDR 0x4 +#define MXS_CLR_ADDR 0x8 +#define MXS_TOG_ADDR 0xc + +static inline void __mxs_setl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_SET_ADDR); +} + +static inline void __mxs_clrl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_CLR_ADDR); +} + +static inline void __mxs_togl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_TOG_ADDR); +} static struct fb_videomode mx23evk_video_modes[] = { { @@ -165,14 +196,80 @@ static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { { /* sentinel */ } }; -static void __init imx23_timer_init(void) -{ - mx23_clocks_init(); -} +#define OCOTP_WORD_OFFSET 0x20 +#define OCOTP_WORD_COUNT 0x20 + +#define BM_OCOTP_CTRL_BUSY (1 << 8) +#define BM_OCOTP_CTRL_ERROR (1 << 9) +#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12) -static void __init imx28_timer_init(void) +static DEFINE_MUTEX(ocotp_mutex); +static u32 ocotp_words[OCOTP_WORD_COUNT]; + +static const u32 *mxs_get_ocotp(void) { - mx28_clocks_init(); + struct device_node *np; + void __iomem *ocotp_base; + int timeout = 0x400; + size_t i; + static int once; + + if (once) + return ocotp_words; + + np = of_find_compatible_node(NULL, NULL, "fsl,ocotp"); + ocotp_base = of_iomap(np, 0); + WARN_ON(!ocotp_base); + + mutex_lock(&ocotp_mutex); + + /* + * clk_enable(hbus_clk) for ocotp can be skipped + * as it must be on when system is running. + */ + + /* try to clear ERROR bit */ + __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base); + + /* check both BUSY and ERROR cleared */ + while ((__raw_readl(ocotp_base) & + (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout) + cpu_relax(); + + if (unlikely(!timeout)) + goto error_unlock; + + /* open OCOTP banks for read */ + __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); + + /* approximately wait 32 hclk cycles */ + udelay(1); + + /* poll BUSY bit becoming cleared */ + timeout = 0x400; + while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout) + cpu_relax(); + + if (unlikely(!timeout)) + goto error_unlock; + + for (i = 0; i < OCOTP_WORD_COUNT; i++) + ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET + + i * 0x10); + + /* close banks for power saving */ + __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); + + once = 1; + + mutex_unlock(&ocotp_mutex); + + return ocotp_words; + +error_unlock: + mutex_unlock(&ocotp_mutex); + pr_err("%s: timeout in reading OCOTP\n", __func__); + return NULL; } enum mac_oui { @@ -454,32 +551,62 @@ static void __init mxs_machine_init(void) imx28_evk_post_init(); } -static const char *imx23_dt_compat[] __initdata = { - "fsl,imx23", - NULL, -}; +#define MX23_CLKCTRL_RESET_OFFSET 0x120 +#define MX28_CLKCTRL_RESET_OFFSET 0x1e0 +#define MXS_CLKCTRL_RESET_CHIP (1 << 1) + +/* + * Reset the system. It is called by machine_restart(). + */ +static void mxs_restart(char mode, const char *cmd) +{ + struct device_node *np; + void __iomem *reset_addr; + + np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); + reset_addr = of_iomap(np, 0); + if (!reset_addr) + goto soft; + + if (of_device_is_compatible(np, "fsl,imx23-clkctrl")) + reset_addr += MX23_CLKCTRL_RESET_OFFSET; + else + reset_addr += MX28_CLKCTRL_RESET_OFFSET; -static const char *imx28_dt_compat[] __initdata = { + /* reset the chip */ + __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr); + + pr_err("Failed to assert the chip reset\n"); + + /* Delay to allow the serial port to show the message */ + mdelay(50); + +soft: + /* We'll take a jump through zero as a poor second */ + soft_restart(0); +} + +static void __init mxs_timer_init(void) +{ + if (of_machine_is_compatible("fsl,imx23")) + mx23_clocks_init(); + else + mx28_clocks_init(); + clocksource_of_init(); +}< |