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-rw-r--r--arch/arm/boot/dts/omap5.dtsi139
1 files changed, 139 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e527083746..5db33f481a33 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,9 +33,21 @@
cpus {
cpu@0 {
compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /* 14th PPI IRQ, active low level-sensitive */
+ interrupts = <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
};
cpu@1 {
compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /* 14th PPI IRQ, active low level-sensitive */
+ interrupts = <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
};
};
@@ -145,6 +157,41 @@
#interrupt-cells = <1>;
};
+ i2c1: i2c@48070000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ };
+
+ i2c2: i2c@48072000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ };
+
+ i2c3: i2c@48060000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ };
+
+ i2c4: i2c@4807A000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c4";
+ };
+
+ i2c5: i2c@4807C000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c5";
+ };
+
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart1";
@@ -180,5 +227,97 @@
ti,hwmods = "uart6";
clock-frequency = <48000000>;
};
+
+ mmc1: mmc@4809c000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ };
+
+ mmc2: mmc@480b4000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc2";
+ ti,needs-special-reset;
+ };
+
+ mmc3: mmc@480ad000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc3";
+ ti,needs-special-reset;
+ };
+
+ mmc4: mmc@480d1000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc4";
+ ti,needs-special-reset;
+ };
+
+ mmc5: mmc@480d5000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc5";
+ ti,needs-special-reset;
+ };
+
+ keypad: keypad@4ae1c000 {
+ compatible = "ti,omap4-keypad";
+ ti,hwmods = "kbd";
+ };
+
+ mcpdm: mcpdm@40132000 {
+ compatible = "ti,omap4-mcpdm";
+ reg = <0x40132000 0x7f>, /* MPU private access */
+ <0x49032000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 112 0x4>;
+ interrupt-parent = <&gic>;
+ ti,hwmods = "mcpdm";
+ };
+
+ dmic: dmic@4012e000 {
+ compatible = "ti,omap4-dmic";
+ reg = <0x4012e000 0x7f>, /* MPU private access */
+ <0x4902e000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 114 0x4>;
+ interrupt-parent = <&gic>;
+ ti,hwmods = "dmic";
+ };
+
+ mcbsp1: mcbsp@40122000 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x40122000 0xff>, /* MPU private access */
+ <0x49022000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 17 0x4>;
+ interrupt-names = "common";
+ interrupt-parent = <&gic>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp1";
+ };
+
+ mcbsp2: mcbsp@40124000 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x40124000 0xff>, /* MPU private access */
+ <0x49024000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 22 0x4>;
+ interrupt-names = "common";
+ interrupt-parent = <&gic>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp2";
+ };
+
+ mcbsp3: mcbsp@40126000 {
+ compatible = "ti,omap4-mcbsp";
+ reg = <0x40126000 0xff>, /* MPU private access */
+ <0x49026000 0xff>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <0 23 0x4>;
+ interrupt-names = "common";
+ interrupt-parent = <&gic>;
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp3";
+ };
};
};