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-rw-r--r--Documentation/devicetree/bindings/mfd/aspeed-lpc.txt21
1 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
index 69aadee00d5f..34dd89087cff 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -176,3 +176,24 @@ lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
+
+LPC reset control
+-----------------
+
+The UARTs present in the ASPEED SoC can have their resets tied to the reset
+state of the LPC bus. Some systems may chose to modify this configuration.
+
+Required properties:
+
+ - compatible: "aspeed,ast2500-lpc-reset" or
+ "aspeed,ast2400-lpc-reset"
+ - reg: offset and length of the IP in the LHC memory region
+ - #reset-controller indicates the number of reset cells expected
+
+Example:
+
+lpc_reset: reset-controller@18 {
+ compatible = "aspeed,ast2500-lpc-reset";
+ reg = <0x18 0x4>;
+ #reset-cells = <1>;
+};