diff options
| -rw-r--r-- | Documentation/devicetree/bindings/gpio/gpio-atlas7.txt | 50 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt | 109 | ||||
| -rw-r--r-- | drivers/pinctrl/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/sirf/Makefile | 1 | ||||
| -rw-r--r-- | drivers/pinctrl/sirf/pinctrl-atlas7.c | 4639 |
5 files changed, 4801 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt b/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt new file mode 100644 index 000000000000..d7e123fc90b5 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt @@ -0,0 +1,50 @@ +CSR SiRFatlas7 GPIO controller bindings + +Required properties: +- compatible : "sirf,atlas7-gpio" +- reg : Address range of the pinctrl registers +- interrupts : Interrupts used by every GPIO group +- gpio-banks : How many gpio banks on this controller +- gpio-controller : Indicates this device is a GPIO controller +- interrupt-controller : Marks the device node as an interrupt controller + +The GPIO controller also acts as an interrupt controller. It uses the default +two cells specifier as described in Documentation/devicetree/bindings/ +interrupt-controller/interrupts.txt. + +Example: + + gpio_0: gpio_mediam@17040000 { + compatible = "sirf,atlas7-gpio"; + reg = <0x17040000 0x1000>; + interrupts = <0 13 0>, <0 14 0>; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + + gpio-controller; + interrupt-controller; + + gpio-banks = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 32 0 0>; + gpio-ranges-group-names = "lvds_gpio_grp", + "uart_nand_gpio_grp"; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + gpios = <&gpio_1 15 0>; + ... + }; + + led2 { + gpios = <&gpio_2 34 0>; + ... + }; + }; + +Please refer to gpio.txt in this directory for details of the common +gpio properties used by devices. diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt new file mode 100644 index 000000000000..eecf028ff485 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt @@ -0,0 +1,109 @@ +CSR SiRFatlas7 pinmux controller + +Required properties: +- compatible : "sirf,atlas7-ioc" +- reg : Address range of the pinctrl registers + +For example, pinctrl might have properties like the following: + pinctrl: ioc@18880000 { + compatible = "sirf,atlas7-ioc"; + reg = <0x18880000 0x1000>; + + a_ac97_pmx: ac97@0 { + ac97 { + groups = "audio_ac97_grp"; + function = "audio_ac97"; + }; + }; + + ... + + sd2_pmx: sd2@0 { + sd2 { + groups = "sd2_grp0"; + function = "sd2"; + }; + }; + + ... + + + sample0_cfg: sample0@0 { + sample0 { + pins = "ldd_0", "ldd_1"; + bias-pull-up; + }; + }; + + sample1_cfg: sample1@0 { + sample1 { + pins = "ldd_2", "ldd_3"; + input-schmitt-enable; + }; + }; + + sample2_cfg: sample2@0 { + sample2 { + groups = "uart4_nopause_grp"; + bias-pull-down; + }; + }; + + sample3_cfg: sample3@0 { + sample3 { + pins = "ldd_4", "ldd_5"; + drive-strength = <2>; + }; + }; + }; + +Please refer to pinctrl-bindings.txt in this directory for details of the common +pinctrl bindings used by client devices. + +SiRFatlas7's pinmux nodes act as a container for an abitrary number of subnodes. +Each of these subnodes represents some desired configuration for a group of pins. + +Required subnode-properties: +- groups : An array of strings. Each string contains the name of a group. +- function: A string containing the name of the function to mux to the + group. + + Valid values for group and function names can be found from looking at the + group and function arrays in driver files: + drivers/pinctrl/pinctrl-sirf.c + +For example, pinctrl might have subnodes like the following: + sd0_pmx: sd0@0 { + sd0 { + groups = "sd0_grp"; + function = "sd0"; + }; + }; + + sd1_pmx0: sd1@0 { + sd1 { + groups = "sd1_grp0"; + function = "sd1_m0"; + }; + }; + + sd1_pmx1: sd1@1 { + sd1 { + groups = "sd1_grp1"; + function = "sd1_m1"; + }; + }; + +For a specific board, if it wants to use sd1, +it can add the following to its board-specific .dts file. +sd1: sd@0x12340000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pmx0>; +} + +or + +sd1: sd@0x12340000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pmx1>; +} diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 542a12a17991..100d9ac2ae1f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -132,6 +132,8 @@ config PINCTRL_SIRF bool "CSR SiRFprimaII pin controller driver" depends on ARCH_SIRF select PINMUX + select PINCONF + select GENERIC_PINCONF select GPIOLIB_IRQCHIP config PINCTRL_PISTACHIO diff --git a/drivers/pinctrl/sirf/Makefile b/drivers/pinctrl/sirf/Makefile index 3ffc475ce40c..fd58e0bacb2a 100644 --- a/drivers/pinctrl/sirf/Makefile +++ b/drivers/pinctrl/sirf/Makefile @@ -3,3 +3,4 @@ obj-y += pinctrl-sirf.o obj-y += pinctrl-prima2.o obj-y += pinctrl-atlas6.o +obj-y += pinctrl-atlas7.o diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c new file mode 100644 index 000000000000..046251aaf156 --- /dev/null +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -0,0 +1,4639 @@ +/* + * pinctrl pads, groups, functions for CSR SiRFatlasVII + * + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/bitops.h> +#include <linux/irq.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/of_irq.h> +#include <linux/of_gpio.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/gpio.h> + +/* Definition of Pad&Mux Properties */ +#define N 0 + +/* The Bank contains input-disable regisgers */ +#define BANK_DS 0 + +/* Clear Register offset */ +#define CLR_REG(r) ((r) + 0x04) + +/* Definition of multiple function select register */ +#define FUNC_CLEAR_MASK 0x7 +#define FUNC_GPIO 0 +#define FUNC_ANALOGUE 0x8 +#define ANA_CLEAR_MASK 0x1 + +/* The Atlas7's Pad Type List */ +enum altas7_pad_type { + PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */ + PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */ + PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */ + PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */ + PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */ + PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */ + PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */ + PAD_T_AD, /* PRDWUWHW08SCDG_HZ */ +}; + +/* Raw value of Driver-Strength Bits */ +#define DS3 BIT(3) +#define DS2 BIT(2) +#define DS1 BIT(1) +#define DS0 BIT(0) +#define DSZ 0 + +/* Drive-Strength Intermediate Values */ +#define DS_NULL -1 +#define DS_1BIT_IM_VAL DS0 +#define DS_1BIT_MASK 0x1 +#define DS_2BIT_IM_VAL (DS1 | DS0) +#define DS_2BIT_MASK 0x3 +#define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0) +#define DS_4BIT_MASK 0xf + +/* The Drive-Strength of 4WE Pad DS1 0 CO */ +#define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */ +#define DS_4WE_2 (DS1) /* 1 0 2 */ +#define DS_4WE_1 (DS0) /* 0 1 1 */ +#define DS_4WE_0 (DSZ) /* 0 0 0 */ + +/* The Drive-Strength of 16st Pad DS3 2 1 0 CO */ +#define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */ +#define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */ +#define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */ +#define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */ +#define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */ +#define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */ +#define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */ +#define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */ +#define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */ +#define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */ +#define DS_16ST_5 (DS2) /* 0 1 0 0 4 */ +#define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */ +#define DS_16ST_3 (DS1) /* 0 0 1 0 2 */ +#define DS_16ST_2 (DS0) /* 0 0 0 1 1 */ +#define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */ +#define DS_16ST_0 (DS3) /* 1 0 0 0 8 */ + +/* The Drive-Strength of M31 Pad DS0 CO */ +#define DS_M31_0 (DSZ) /* 0 0 */ +#define DS_M31_1 (DS0) /* 1 1 */ + +/* Raw values of Pull Option Bits */ +#define PUN BIT(1) +#define PD BIT(0) +#define PE BIT(0) +#define PZ 0 + +/* Definition of Pull Types */ +#define PULL_UP 0 +#define HIGH_HYSTERESIS 1 +#define HIGH_Z 2 +#define PULL_DOWN 3 +#define PULL_DISABLE 4 +#define PULL_ENABLE 5 +#define PULL_UNKNOWN -1 + +/* Pull Options for 4WE Pad PUN PD CO */ +#define P4WE_PULL_MASK 0x3 +#define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */ +#define P4WE_HIGH_Z (PUN) /* 1 0 2 */ +#define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */ +#define P4WE_PULL_UP (PZ) /* 0 0 0 */ + +/* Pull Options for 16ST Pad PUN PD CO */ +#define P16ST_PULL_MASK 0x3 +#define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */ +#define P16ST_HIGH_Z (PUN) /* 1 0 2 */ +#define P16ST_PULL_UP (PZ) /* 0 0 0 */ + +/* Pull Options for M31 Pad PE */ +#define PM31_PULL_MASK 0x1 +#define PM31_PULL_ENABLED (PE) /* 1 */ +#define PM31_PULL_DISABLED (PZ) /* 0 */ + +/* Pull Options for A/D Pad PUN PD CO */ +#define PANGD_PULL_MASK 0x3 +#define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */ +#define PANGD_HIGH_Z (PUN) /* 1 0 2 */ +#define PANGD_PULL_UP (PZ) /* 0 0 0 */ + +/* Definition of Input Disable */ +#define DI_MASK 0x1 +#define DI_DISABLE 0x1 +#define DI_ENABLE 0x0 + +/* Definition of Input Disable Value */ +#define DIV_MASK 0x1 +#define DIV_DISABLE 0x1 +#define DIV_ENABLE 0x0 + +struct dt_params { + const char *property; + int value; +}; + +/** + * struct atlas7_pad_conf - Atlas7 Pad Configuration + * @id The ID of this Pad. + * @type: The type of this Pad. + * @mux_reg: The mux register offset. + * This register contains the mux. + * @pupd_reg: The pull-up/down register offset. + * @drvstr_reg: The drive-strength register offset. + * @ad_ctrl_reg: The Analogue/Digital Control register. + * + * @mux_bit: The start bit of mux register. + * @pupd_bit: The start bit of pull-up/down register. + * @drvstr_bit: The start bit of drive-strength register. + * @ad_ctrl_bit: The start bit of analogue/digital register. + */ +struct atlas7_pad_config { + const u32 id; + u32 type; + u32 mux_reg; + u32 pupd_reg; + u32 drvstr_reg; + u32 ad_ctrl_reg; + /* bits in register */ + u8 mux_bit; + u8 pupd_bit; + u8 drvstr_bit; + u8 ad_ctrl_bit; +}; + +#define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \ + { \ + .id = pad, \ + .type = t, \ + .mux_reg = mr, \ + .pupd_reg = pr, \ + .drvstr_reg = dsr, \ + .ad_ctrl_reg = adr, \ + .mux_bit = mb, \ + .pupd_bit = pb, \ + .drvstr_bit = dsb, \ + .ad_ctrl_bit = adb, \ + } + +/** + * struct atlas7_pad_mux - Atlas7 mux + * @bank: The bank of this pad's registers on. + * @pin : The ID of this Pad. + * @func: The mux func on this Pad. + * @dinput_reg: The Input-Disable register offset. + * @dinput_bit: The start bit of Input-Disable register. + * @dinput_val_reg: The Input-Disable-value register offset. + * This register is used to set the value of this pad + * if this pad was disabled. + * @dinput_val_bit: The start bit of Input-Disable Value register. + */ +struct atlas7_pad_mux { + u32 bank; + u32 pin; + u32 func; + u32 dinput_reg; + u32 dinput_bit; + u32 dinput_val_reg; + u32 dinput_val_bit; +}; + +#define MUX(b, pad, f, dr, db, dvr, dvb) \ + { \ + .bank = b, \ + .pin = pad, \ + .func = f, \ + .dinput_reg = dr, \ + .dinput_bit = db, \ + .dinput_val_reg = dvr, \ + .dinput_val_bit = dvb, \ + } + +struct atlas7_grp_mux { + unsigned int group; + unsigned int pad_mux_count; + const struct atlas7_pad_mux *pad_mux_list; +}; + + /** + * struct sirfsoc_pin_group - describes a SiRFprimaII pin group + * @name: the name of this specific pin group + * @pins: an array of discrete physical pins used in this group, taken + * from the driver-local pin enumeration space + * @num_pins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + */ +struct atlas7_pin_group { + const char *name; + const unsigned int *pins; + const unsigned num_pins; +}; + +#define GROUP(n, p) \ + { \ + .name = n, \ + .pins = p, \ + .num_pins = ARRAY_SIZE(p), \ + } + +struct atlas7_pmx_func { + const char *name; + const char * const *groups; + const unsigned num_groups; + const struct atlas7_grp_mux *grpmux; +}; + +#define FUNCTION(n, g, m) \ + { \ + .name = n, \ + .groups = g, \ + .num_groups = ARRAY_SIZE(g), \ + .grpmux = m, \ + } + +struct atlas7_pinctrl_data { + struct pinctrl_pin_desc *pads; + int pads_cnt; + struct atlas7_pin_group *grps; + int grps_cnt; + struct atlas7_pmx_func *funcs; + int funcs_cnt; + struct atlas7_pad_config *confs; + int confs_cnt; +}; + +/* Platform info of atlas7 pinctrl */ +#define ATLAS7_PINCTRL_REG_BANKS 2 +#define ATLAS7_PINCTRL_BANK_0_PINS 18 + +/** + * Atlas7 GPIO Chip + */ + +#define NGPIO_OF_BANK 32 +#define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK) + +/* Registers of GPIO Controllers */ +#define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b)) +#define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i)) +#define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C) + +/* Definition bits of GPIO Control Registers */ +#define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0) +#define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1) +#define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2) +#define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3) +#define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4) +#define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5) +#define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6) +#define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7) + +struct atlas7_gpio_bank { + struct pinctrl_dev *pctldev; + int id; + int irq; + void __iomem *base; + unsigned int gpio_offset; + unsigned int ngpio; + const unsigned int *gpio_pins; +}; + +struct atlas7_gpio_chip { + const char *name; + void __iomem *reg; + struct clk *clk; + int nbank; + spinlock_t lock; + struct gpio_chip chip; + struct atlas7_gpio_bank banks[0]; +}; + +static inline struct atlas7_gpio_chip *to_atlas7_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct atlas7_gpio_chip, chip); +} + +/** + * @dev: a pointer back to containing device + * @virtbase: the offset to the controller in virtual memory + */ +struct atlas7_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + struct pinctrl_desc pctl_desc; + struct atlas7_pinctrl_data *pctl_data; + void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS]; +}; + +/* + * Pad list for the pinmux subsystem + * refer to A7DA IO Summary - CS-314158-DD-4E.xls + */ + +/*Pads in IOC RTC & TOP */ +static const struct pinctrl_pin_desc atlas7_ioc_pads[] = { + /* RTC PADs */ + PINCTRL_PIN(0, "rtc_gpio_0"), + PINCTRL_PIN(1, "rtc_gpio_1"), + PINCTRL_PIN(2, "rtc_gpio_2"), + PINCTRL_PIN(3, "rtc_gpio_3"), + PINCTRL_PIN(4, "low_bat_ind_b"), + PINCTRL_PIN(5, "on_key_b"), + PINCTRL_PIN(6, "ext_on"), + PINCTRL_PIN(7, "mem_on"), + PINCTRL_PIN(8, "core_on"), + PINCTRL_PIN(9, "io_on"), + PINCTRL_PIN(10, "can0_tx"), + PINCTRL_PIN(11, "can0_rx"), + PINCTRL_PIN(12, "spi0_clk"), + PINCTRL_PIN(13, "spi0_cs_b"), + PINCTRL_PIN(14, "spi0_io_0"), + PINCTRL_PIN(15, "spi0_io_1"), + PINCTRL_PIN(16, "spi0_io_2"), + PINCTRL_PIN(17, "spi0_io_3"), + + /* TOP PADs */ + PINCTRL_PIN(18, "spi1_en"), + PINCTRL_PIN(19, "spi1_clk"), + PINCTRL_PIN(20, "spi1_din"), + PINCTRL_PIN(21, "spi1_dout"), + PINCTRL_PIN(22, "trg_spi_clk"), + PINCTRL_PIN(23, "trg_spi_di"), + PINCTRL_PIN(24, "trg_spi_do"), + PINCTRL_PIN(25, "trg_spi_cs_b"), + PINCTRL_PIN(26, "trg_acq_d1"), + PINCTRL_PIN(27, "trg_irq_b"), + PINCTRL_PIN(28, "trg_acq_d0"), + PINCTRL_PIN(29, "trg_acq_clk"), + PINCTRL_PIN(30, "trg_shutdown_b_out"), + PINCTRL_PIN(31, "sdio2_clk"), + PINCTRL_PIN(32, "sdio2_cmd"), + PINCTRL_PIN(33, "sdio2_dat_0"), + PINCTRL_PIN(34, "sdio2_dat_1"), + PINCTRL_PIN(35, "sdio2_dat_2"), + PINCTRL_PIN(36, "sdio2_dat_3"), + PINCTRL_PIN(37, "df_ad_7"), + PINCTRL_PIN(38, "df_ad_6"), + PINCTRL_PIN(39, "df_ad_5"), + PINCTRL_PIN(40, "df_ad_4"), + PINCTRL_PIN(41, "df_ad_3"), + PINCTRL_PIN(42, "df_ad_2"), + PINCTRL_PIN(43, "df_ad_1"), + PINCTRL_PIN(44, "df_ad_0"), + PINCTRL_PIN(45, "df_dqs"), + PINCTRL_PIN(46, "df_cle"), + PINCTRL_PIN(47, "df_ale"), + PINCTRL_PIN(48, "df_we_b"), + PINCTRL_PIN(49, "df_re_b"), + PINCTRL_PIN(50, "df_ry_by"), + PINCTRL_PIN(51, "df_cs_b_1"), + PINCTRL_PIN(52, "df_cs_b_0"), + PINCTRL_PIN(53, "l_pclk"), + PINCTRL_PIN(54, "l_lck"), + PINCTRL_PIN(55, "l_fck"), + PINCTRL_PIN(56, "l_de"), + PINCTRL_PIN(57, "ldd_0"), + PINCTRL_PIN(58, "ldd_1"), + PINCTRL_PIN(59, "ldd_2"), + PINCTRL_PIN(60, "ldd_3"), + PINCTRL_PIN(61, "ldd_4"), + PINCTRL_PIN(62, "ldd_5"), + PINCTRL_PIN(63, "ldd_6"), + PINCTRL_PIN(64, "ldd_7"), + PINCTRL_PIN(65, "ldd_8"), + PINCTRL_PIN(66, "ldd_9"), + PINCTRL_PIN(67, "ldd_10"), + PINCTRL_PIN(68, "ldd_11"), + PINCTRL_PIN(69, "ldd_12"), + PINCTRL_PIN(70, "ldd_13"), + PINCTRL_PIN(71, "ldd_14"), + PINCTRL_PIN(72, "ldd_15"), + PINCTRL_PIN(73, "lcd_gpio_20"), + PINCTRL_PIN(74, "vip_0"), + PINCTRL_PIN(75, "vip_1"), + PINCTRL_PIN(76, "vip_2"), + PINCTRL_PIN(77, "vip_3"), + PINCTRL_PIN(78, "vip_4"), + PINCTRL_PIN(79, "vip_5"), + PINCTRL_PIN(80, "vip_6"), + PINCTRL_PIN(81, "vip_7"), + PINCTRL_PIN(82, "vip_pxclk"), + PINCTRL_PIN(83, "vip_hsync"), + PINCTRL_PIN(84, "vip_vsync"), + PINCTRL_PIN(85, "sdio3_clk"), + PINCTRL_PIN(86, "sdio3_cmd"), + PINCTRL_PIN(87, "sdio3_dat_0"), + PINCTRL_PIN(88, "sdio3_dat_1"), + PINCTRL_PIN(89, "sdio3_dat_2"), + PINCTRL_PIN(90, "sdio3_dat_3"), + PINCTRL_PIN(91, "sdio5_clk"), + PINCTRL_PIN(92, "sdio5_cmd"), + PINCTRL_PIN(93, "sdio5_dat_0"), + PINCTRL_PIN(94, "sdio5_dat_1"), + PINCTRL_PIN(95, "sdio5_dat_2"), + PINCTRL_PIN(96, "sdio5_dat_3"), + PINCTRL_PIN(97, "rgmii_txd_0"), + PINCTRL_PIN(98, "rgmii_txd_1"), + PINCTRL_PIN(99, "rgmii_txd_2"), + PINCTRL_PIN(100, "rgmii_txd_3"), + PINCTRL_PIN(101, "rgmii_txclk"), + PINCTRL_PIN(102, "rgmii_tx_ctl"), + PINCTRL_PIN(103, "rgmii_rxd_0"), + PINCTRL_PIN(104, "rgmii_rxd_1"), + PINCTRL_PIN(105, "rgmii_rxd_2"), + PINCTRL_PIN(106, "rgmii_rxd_3"), + PINCTRL_PIN(107, "rgmii_rx_clk"), + PINCTRL_PIN(108, "rgmii_rxc_ctl"), + PINCTRL_PIN(109, "rgmii_mdio"), + PINCTRL_PIN(110, "rgmii_mdc"), + PINCTRL_PIN(111, "rgmii_intr_n"), + PINCTRL_PIN(112, "i2s_mclk"), + PINCTRL_PIN(113, "i2s_bclk"), + PINCTRL_PIN(114, "i2s_ws"), + PINCTRL_PIN(115, "i2s_dout0"), + PINCTRL_PIN(116, "i2s_dout1"), + PINCTRL_PIN(117, "i2s_dout2"), + PINCTRL_PIN(118, "i2s_din"), + PINCTRL_PIN(119, "gpio_0"), + PINCTRL_PIN(120, "gpio_1"), + PINCTRL_PIN(121, "gpio_2"), + PINCTRL_PIN(122, "gpio_3"), + PINCTRL_PIN(123, "gpio_4"), + PINCTRL_PIN(124, "gpio_5"), + PINCTRL_PIN(125, "gpio_6"), + PINCTRL_PIN(126, "gpio_7"), + PINCTRL_PIN(127, "sda_0"), + PINCTRL_PIN(128, "scl_0"), + PINCTRL_PIN(129, "coex_pio_0"), + PINCTRL_PIN(130, "coex_pio_1"), + PINCTRL_PIN(131, "coex_pio_2"), + PINCTRL_PIN(132, "coex_pio_3"), + PINCTRL_PIN(133, "uart0_tx"), + PINCTRL_PIN(134, "uart0_rx"), + PINCTRL_PIN(135, "uart1_tx"), + PINCTRL_PIN(136, "uart1_rx"), + PINCTRL_PIN(137, "uart3_tx"), + PINCTRL_PIN(138, "uart3_rx"), + PINCTRL_PIN(139, "uart4_tx"), + PINCTRL_PIN(140, "uart4_rx"), + PINCTRL_PIN(141, "usp0_clk"), + PINCTRL_PIN(142, "usp0_tx"), + PINCTRL_PIN(143, "usp0_rx"), + PINCTRL_PIN(144, "usp0_fs"), + PINCTRL_PIN(145, "usp1_clk"), + PINCTRL_PIN(146, "usp1_tx"), + PINCTRL_PIN(147, "usp1_rx"), + PINCTRL_PIN(148, "usp1_fs"), + PINCTRL_PIN(149, "lvds_tx0d4p"), + PINCTRL_PIN(150, "lvds_tx0d4n"), + PINCTRL_PIN(151, "lvds_tx0d3p"), + PINCTRL_PIN(152, "lvds_tx0d3n"), + PINCTRL_PIN(153, "lvds_tx0d2p"), + PINCTRL_PIN(154, "lvds_tx0d2n"), + PINCTRL_PIN(155, "lvds_tx0d1p"), + PINCTRL_PIN(156, "lvds_tx0d1n"), + PINCTRL_PIN(157, "lvds_tx0d0p"), + PINCTRL_PIN(158, "lvds_tx0d0n"), +}; + +struct atlas7_pad_config atlas7_ioc_pad_confs[] = { + /* The Configuration of IOC_RTC Pads */ + PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0), + PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0), + PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0), + PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0), + PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0), + PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0), + PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0), + PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0), + PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0), + PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0), + PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0), + PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0), + PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0), + PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0), + PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0), + PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0), + PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0), + PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0), + /* The Configuration of IOC_TOP Pads */ + PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0), + PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0), + PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0), + PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0), + PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0), + PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0), + PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0), + PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0), + PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0), + PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0), + PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0), + PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0), + PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0), + PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0), + PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0), + PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0), + PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0), + PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0), + PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0), + PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0), + PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0), + PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0), + PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0), + PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0), + PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0), + PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0), + PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0), + PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0), + PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0), + PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0), + PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0), + PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0), + PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0), + PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0), + PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0), + PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0), + PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0), + PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0), + PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0), + PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0), + PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0), + PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0), + PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0), + PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0), + PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0), + PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0), + PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0), + PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0), + PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0), + PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0), + PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0), + PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0), + PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0), + PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0), + PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0), + PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0), + PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0), + PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0), + PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0), + PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0), + PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0), + PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0), + PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0), + PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0), + PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0), + PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0), + PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0), + PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0), + PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0), + PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0), + PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0), + PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0), + PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0), + PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0), + PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0), + PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0), + PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0), + PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0), + PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0), + PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0), + PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0), + PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0), + PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0), + PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0), + PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0), + PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0), + PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0), + PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0), + PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0), + PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0), + PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0), + PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0), + PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0), + PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0), + PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0), + PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0), + PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0), + PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0), + PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0), + PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0), + PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0), + PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0), + PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0), + PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0), + PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0), + PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0), + PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0), + PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0), + PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0), + PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0), + PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0), + PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0), + PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0), + PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0), + PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0), + PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0), + PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0), + PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0), + PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0), + PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0), + PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0), + PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0), + PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0), + PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0), + PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0), + PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0), + PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0), + PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0), + PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0), + PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0), + PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0), + PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0), + PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1), + PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2), + PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3), + PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4), + PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5), + PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6), + PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7), + PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8), + PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9), +}; + +/* pin list of each pin group */ +static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124, + 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, }; +static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80, + 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, }; +static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36, + 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94, + 95, 96, 112, 113, 114, 115, 116, 117, 118, }; +static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102, + 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21, + 141, 142, 143, 144, 145, 146, 147, 148, }; +static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154, + 151, 152, 149, 150, }; +static const unsigned int uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, 39, + 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, 136, + 137, 138, 139, 140, }; +static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13, + 14, 15, 16, 17, }; +static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, }; +static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41, + 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118, + 115, 49, 50, 142, 143, 80, }; +static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113, + 114, }; +static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, }; +static const unsigned int audio_i2s_extclk_pins[] = { 112, }; +static const unsigned int audio_uart0_pins[] = { 143, 142, 141, 144, }; +static const unsigned int audio_uart1_pins[] = { 147, 146, 145, 148, }; +static const unsigned int audio_uart2_pins0[] = { 20, 21, 19, 18, }; +static const unsigned int audio_uart2_pins1[] = { 109, 110, 101, 111, }; +static const unsigned int c_can_trnsvr_pins[] = { 1, }; +static const unsigned int c0_can_pins0[] = { 11, 10, }; +static const unsigned int c0_can_pins1[] = { 2, 3, }; +static const unsigned int c1_can_pins0[] = { 138, 137, }; +static const unsigned int c1_can_pins1[] = { 147, 146, }; +static const unsigned int c1_can_pins2[] = { 2, 3, }; +static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68, + 69, 70, 71, }; +static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, }; +static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, }; +static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, }; +static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, }; +static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47, + 49, 50, 54, 55, 56, }; +static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, }; +static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, }; +static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75, + 76, 77, }; +static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, }; +static const unsigned int clkc_pins0[] = { 30, 47, }; +static const unsigned int clkc_pins1[] = { 78, 54, }; +static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, }; +static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, }; +static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, }; +static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, }; +static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, }; +static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78, + 79, 80, 81, 83, 84, 73, 55, 56, }; +static const unsigned int cvbs_dbg_test_pins0[] = { 57, }; +static const unsigned int cvbs_dbg_test_pins1[] = { 58, }; +static const unsigned int cvbs_dbg_test_pins2[] = { 59, }; +static const unsigned int cvbs_dbg_test_pins3[] = { 60, }; +static const unsigned int cvbs_dbg_test_pins4[] = { 61, }; +static const unsigned int cvbs_dbg_test_pins5[] = { 62, }; +static const unsigned int cvbs_dbg_test_pins6[] = { 63, }; +static const unsigned int cvbs_dbg_test_pins7[] = { 64, }; +static const unsigned int cvbs_dbg_test_pins8[] = { 65, }; +static const unsigned int cvbs_dbg_test_pins9[] = { 66, }; +static const unsigned int cvbs_dbg_test_pins10[] = { 67, }; +static const unsigned int cvbs_dbg_test_pins11[] = { 68, }; +static const unsigned int cvbs_dbg_test_pins12[] = { 69, }; +static const unsigned int cvbs_dbg_test_pins13[] = { 70, }; +static const unsigned int cvbs_dbg_test_pins14[] = { 71, }; +static const unsigned int cvbs_dbg_test_pins15[] = { 72, }; +static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125, + 120, }; +static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, }; +static const unsigned int gn_gnss_eclk_pins[] = { 113, }; +static const unsigned int gn_gnss_irq1_pins0[] = { 112, }; +static const unsigned int gn_gnss_irq2_pins0[] = { 118, }; +static const unsigned int gn_gnss_tm_pins[] = { 115, }; +static const unsigned int gn_gnss_tsync_pins[] = { 114, }; +static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40, + 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, }; +static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, }; +static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, }; +static const unsigned int gn_trg_shutdown_pins0[] = { 30, }; +static const unsigned int gn_trg_shutdown_pins1[] = { 83, }; +static const unsigned int gn_trg_shutdown_pins2[] = { 117, }; +static const unsigned int gn_trg_shutdown_pins3[] = { 123, }; +static const unsigned int i2c0_pins[] = { 128, 127, }; +static const unsigned int i2c1_pins[] = { 126, 125, }; +static const unsigned int jtag_pins0[] = { 125, 4, 2, 0, 1, 3, }; +static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, }; +static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64, + 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80, + 81, 56, 53, }; +static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, }; +static const unsigned int ld_ldd_fck_pins[] = { 55, }; +static const unsigned int ld_ldd_lck_pins[] = { 54, }; +static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, }; +static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154, + 155, 156, 157, 158, }; +static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37, + 47, 46, 52, 51, 45, 49, 50, 48, 124, }; +static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38, + 37, 47, 46, 52, 51, 45, 49, 50, 48, }; +static const unsigned int ps_pins[] = { 120, 119, }; +static const unsigned int pwc_core_on_pins[] = { 8, }; +static const unsigned int pwc_ext_on_pins[] = { 6, }; +static const unsigned int pwc_gpio3_clk_pins[] = { 3, }; +static const unsigned int pwc_io_on_pins[] = { 9, }; +static const unsigned int pwc_lowbatt_b_pins0[] = { 4, }; +static const unsigned int pwc_mem_on_pins[] = { 7, }; +static const unsigned int pwc_on_key_b_pins0[] = { 5, }; +static const unsigned int pwc_wakeup_src0_pins[] = { 0, }; +static const unsigned int pwc_wakeup_src1_pins[] = { 1, }; +static const unsigned int pwc_wakeup_src2_pins[] = { 2, }; +stat |