diff options
80 files changed, 347 insertions, 270 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index f728ac2b298a..ebb6c6f30c56 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -824,7 +824,7 @@ ARM/CIRRUS LOGIC CLPS711X ARM ARCHITECTURE M: Alexander Shiyan <shc_work@mail.ru> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Odd Fixes -F: arch/arm/mach-clps711x/ +N: clps711x ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE M: Hartley Sweeten <hsweeten@visionengravers.com> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b4ac5de6dec..79bea0b34d1f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -423,6 +423,7 @@ config ARCH_EFM32 bool "Energy Micro efm32" depends on !MMU select ARCH_REQUIRE_GPIOLIB + select AUTO_ZRELADDR select ARM_NVIC # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged, # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO @@ -698,6 +699,7 @@ config ARCH_RPC select ARCH_MAY_HAVE_PC_FDC select ARCH_SPARSEMEM_ENABLE select ARCH_USES_GETTIMEOFFSET + select CPU_SA110 select FIQ select HAVE_IDE select HAVE_PATA_PLATFORM @@ -732,6 +734,7 @@ config ARCH_S3C24XX bool "Samsung S3C24XX SoCs" select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB + select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select GENERIC_CLOCKEVENTS @@ -754,6 +757,7 @@ config ARCH_S3C64XX select ARCH_REQUIRE_GPIOLIB select ARM_AMBA select ARM_VIC + select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select COMMON_CLK @@ -765,7 +769,7 @@ config ARCH_S3C64XX select HAVE_TCM select NO_IOPORT select PLAT_SAMSUNG - select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS if PM select S3C_DEV_NAND select S3C_GPIO_TRACK select SAMSUNG_ATAGS @@ -776,6 +780,7 @@ config ARCH_S3C64XX config ARCH_S5P64X0 bool "Samsung S5P6440 S5P6450" + select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select CPU_V6 @@ -794,6 +799,7 @@ config ARCH_S5P64X0 config ARCH_S5PC100 bool "Samsung S5PC100" select ARCH_REQUIRE_GPIOLIB + select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select CPU_V7 @@ -813,6 +819,7 @@ config ARCH_S5PV210 select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_SPARSEMEM_ENABLE + select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select CPU_V7 @@ -886,6 +893,12 @@ menu "Multiple platform selection" comment "CPU Core family selection" +config ARCH_MULTI_V4 + bool "ARMv4 based platforms (FA526)" + depends on !ARCH_MULTI_V6_V7 + select ARCH_MULTI_V4_V5 + select CPU_FA526 + config ARCH_MULTI_V4T bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" depends on !ARCH_MULTI_V6_V7 diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 6d95d3df33c7..79087ccf64bc 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -448,7 +448,7 @@ ti,hwmods = "usb_otg_hs"; status = "disabled"; - usb_ctrl_mod: control@44e10000 { + usb_ctrl_mod: control@44e10620 { compatible = "ti,am335x-usb-ctrl-module"; reg = <0x44e10620 0x10 0x44e10648 0x4>; @@ -551,7 +551,7 @@ "tx14", "tx15"; }; - cppi41dma: dma-controller@07402000 { + cppi41dma: dma-controller@47402000 { compatible = "ti,am3359-cppi41"; reg = <0x47400000 0x1000 0x47402000 0x1000 diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index b42e658876e5..457112d659ea 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -287,6 +287,7 @@ regulator-name = "vdd_g3d"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-always-on; regulator-boot-on; op_mode = <1>; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index d3f8a6e8ca20..69409f7e05dc 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -275,6 +275,8 @@ gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; ti,no-idle-on-init; + clocks = <&l3_div_ck>; + clock-names = "fck"; }; uart1: serial@4806a000 { diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index a72813a9663e..7a16647c76f4 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -302,6 +302,8 @@ gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; }; i2c1: i2c@48070000 { diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 73aecfb57ccb..eb54353975bc 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -715,7 +715,6 @@ nvidia,pins = "drive_sdio1"; nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; nvidia,pull-down-strength = <36>; nvidia,pull-up-strength = <20>; nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; @@ -725,7 +724,6 @@ nvidia,pins = "drive_sdio3"; nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; nvidia,pull-down-strength = <22>; nvidia,pull-up-strength = <36>; nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index c6dcef513e5d..0b54743c2621 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -138,14 +138,9 @@ nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0", - "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; + nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; @@ -423,7 +418,6 @@ nvidia,pins = "drive_sdio1"; nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; nvidia,pull-down-strength = <32>; nvidia,pull-up-strength = <42>; nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; @@ -433,7 +427,6 @@ nvidia,pins = "drive_sdio3"; nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; nvidia,pull-down-strength = <20>; nvidia,pull-up-strength = <36>; nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index ab2f7378352c..932b932c8856 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -198,3 +198,5 @@ CONFIG_DEBUG_ERRORS=y # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set CONFIG_CRC_T10DIF=m +CONFIG_GPIO_PCA953X=y +CONFIG_KEYBOARD_GPIO_POLLED=y diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index dbe1f1c47bb0..4ce7b70ea901 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -94,7 +94,7 @@ CONFIG_FONT_7x14=y CONFIG_LOGO=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_S5P=y +CONFIG_USB_EHCI_EXYNOS=y CONFIG_USB_STORAGE=y CONFIG_USB_DWC3=y CONFIG_USB_PHY=y diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 22a3b9b5d4a1..4157aec4e307 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -74,6 +74,7 @@ struct secondary_data { }; extern struct secondary_data secondary_data; extern volatile int pen_release; +extern void secondary_startup(void); extern int __cpu_disable(void); diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S index f98763f0bc17..3bc80599c022 100644 --- a/arch/arm/include/debug/tegra.S +++ b/arch/arm/include/debug/tegra.S @@ -53,8 +53,7 @@ #define checkuart(rp, rv, lhu, bit, uart) \ /* Load address of CLK_RST register */ \ - movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \ - movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \ + ldr rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \ /* Load value from CLK_RST register */ \ ldr rp, [rp, #0] ; \ /* Test UART's reset bit */ \ @@ -62,8 +61,7 @@ /* If set, can't use UART; jump to save no UART */ \ bne 90f ; \ /* Load address of CLK_OUT_ENB register */ \ - movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \ - movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \ + ldr rp, =TEGRA_CLK_OUT_ENB_##lhu ; \ /* Load value from CLK_OUT_ENB register */ \ ldr rp, [rp, #0] ; \ /* Test UART's clock enable bit */ \ @@ -71,8 +69,7 @@ /* If clear, can't use UART; jump to save no UART */ \ beq 90f ; \ /* Passed all tests, load address of UART registers */ \ - movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \ - movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \ + ldr rp, =TEGRA_UART##uart##_BASE ; \ /* Jump to save UART address */ \ b 91f @@ -90,15 +87,16 @@ #ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA /* Check ODMDATA */ -10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff - movt \rp, #TEGRA_PMC_SCRATCH20 >> 16 +10: ldr \rp, =TEGRA_PMC_SCRATCH20 ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20 - ubfx \rv, \rp, #18, #2 @ 19:18 are console type + lsr \rv, \rp, #18 @ 19:18 are console type + and \rv, \rv, #3 cmp \rv, #2 @ 2 and 3 mean DCC, UART beq 11f @ some boards swap the meaning cmp \rv, #3 @ so accept either bne 90f -11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID +11: lsr \rv, \rp, #15 @ 17:15 are UART ID + and \rv, #7 cmp \rv, #0 @ UART 0? beq 20f cmp \rv, #1 @ UART 1? diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 4f0e800e7e71..9968f208b7df 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -57,6 +57,7 @@ config SOC_SAMA5 select GENERIC_CLOCKEVENTS select MULTI_IRQ_HANDLER select SPARSE_IRQ + select USE_OF menu "Atmel AT91 System-on-Chip" @@ -64,11 +65,22 @@ choice prompt "Core type" +config ARCH_AT91X40 + bool "ARM7 AT91X40" + depends on !MMU + select CPU_ARM7TDMI + select ARCH_USES_GETTIMEOFFSET + select MULTI_IRQ_HANDLER + select SPARSE_IRQ + + help + Select this if you are using one of Atmel's AT91X40 SoC. + config SOC_SAM_V4_V5 - bool "ARM7/ARM9" + bool "ARM9 AT91SAM9/AT91RM9200" help - Select this if you are using one of Atmel's AT91SAM9, AT91RM9200 - or AT91X40 SoC. + Select this if you are using one of Atmel's AT91SAM9 or + AT91RM9200 SoC. config SOC_SAM_V7 bool "Cortex A5" @@ -179,9 +191,12 @@ config SOC_AT91SAM9N12 Select this if you are using Atmel's AT91SAM9N12 SoC. # ---------------------------------------------------------- +endif # SOC_SAM_V4_V5 + +if SOC_SAM_V4_V5 || ARCH_AT91X40 source arch/arm/mach-at91/Kconfig.non_dt -endif # SOC_SAM_V4_V5 +endif comment "Generic Board Type" diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt index 1f73e9b527da..44ace320d2e1 100644 --- a/arch/arm/mach-at91/Kconfig.non_dt +++ b/arch/arm/mach-at91/Kconfig.non_dt @@ -5,6 +5,7 @@ config HAVE_AT91_DATAFLASH_CARD choice prompt "Atmel AT91 Processor Devices for non DT boards" + depends on !ARCH_AT91X40 config ARCH_AT91_NONE bool "None" @@ -39,13 +40,6 @@ config ARCH_AT91SAM9G45 select SOC_AT91SAM9G45 select AT91_USE_OLD_CLK -config ARCH_AT91X40 - bool "AT91x40" - depends on !MMU - select ARCH_USES_GETTIMEOFFSET - select MULTI_IRQ_HANDLER - select SPARSE_IRQ - endchoice config ARCH_AT91SAM9G20 diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index eda8d1679d40..1630ae64d3fb 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -1255,12 +1255,8 @@ void __init at91_add_device_cf(struct at91_cf_data *data) at91_set_A_periph(AT91_PIN_PC10, 0); /* CFRNW */ at91_set_A_periph(AT91_PIN_PC15, 1); /* NWAIT */ - if (data->flags & AT91_CF_TRUE_IDE) -#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) + if (IS_ENABLED(CONFIG_PATA_AT91) && (data->flags & AT91_CF_TRUE_IDE)) pdev->name = "pata_at91"; -#else -#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91" -#endif else pdev->name = "at91_cf"; diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index b26156bf15db..826315af6d11 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -36,6 +36,7 @@ void sam9_smc_write_mode(int id, int cs, { sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config); } +EXPORT_SYMBOL_GPL(sam9_smc_write_mode); static void sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config *config) @@ -69,6 +70,7 @@ void sam9_smc_configure(int id, int cs, { sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); } +EXPORT_SYMBOL_GPL(sam9_smc_configure); static void sam9_smc_cs_read_mode(void __iomem *base, struct sam9_smc_config *config) @@ -84,6 +86,7 @@ void sam9_smc_read_mode(int id, int cs, { sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config); } +EXPORT_SYMBOL_GPL(sam9_smc_read_mode); static void sam9_smc_cs_read(void __iomem *base, struct sam9_smc_config *config) diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index f7ca97b7291e..f7a07a58ebb6 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -351,7 +351,7 @@ void __init at91_ioremap_matrix(u32 base_addr) panic("Impossible to ioremap at91_matrix_base\n"); } -#if defined(CONFIG_OF) +#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40) static struct of_device_id rstc_ids[] = { { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart }, { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart }, diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c index f8d71a89644a..5f831133178f 100644 --- a/arch/arm/mach-clps711x/board-autcpu12.c +++ b/arch/arm/mach-clps711x/board-autcpu12.c @@ -73,7 +73,7 @@ #define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */ #define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2) #define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3) -#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3) +#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 4) /* LCD contrast digital potentiometer */ #define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0) diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index ce096d678aa4..d863d8729ed |