diff options
| -rw-r--r-- | Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 54 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 57 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt | 50 | ||||
| -rw-r--r-- | drivers/mailbox/Kconfig | 16 | ||||
| -rw-r--r-- | drivers/mailbox/Makefile | 4 | ||||
| -rw-r--r-- | drivers/mailbox/imx-mailbox.c | 358 | ||||
| -rw-r--r-- | drivers/mailbox/mailbox-xgene-slimpro.c | 6 | ||||
| -rw-r--r-- | drivers/mailbox/mtk-cmdq-mailbox.c | 571 | ||||
| -rw-r--r-- | drivers/mailbox/omap-mailbox.c | 31 | ||||
| -rw-r--r-- | drivers/mailbox/ti-msgmgr.c | 353 | ||||
| -rw-r--r-- | include/dt-bindings/gce/mt8173-gce.h | 44 | ||||
| -rw-r--r-- | include/linux/mailbox/mtk-cmdq-mailbox.h | 77 | ||||
| -rw-r--r-- | include/linux/omap-mailbox.h | 5 |
13 files changed, 1536 insertions, 90 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt new file mode 100644 index 000000000000..f3cf77eb5ab4 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -0,0 +1,54 @@ +NXP i.MX Messaging Unit (MU) +-------------------------------------------------------------------- + +The Messaging Unit module enables two processors within the SoC to +communicate and coordinate by passing messages (e.g. data, status +and control) through the MU interface. The MU also provides the ability +for one processor to signal the other processor using interrupts. + +Because the MU manages the messaging between processors, the MU uses +different clocks (from each side of the different peripheral buses). +Therefore, the MU must synchronize the accesses from one side to the +other. The MU accomplishes synchronization using two sets of matching +registers (Processor A-facing, Processor B-facing). + +Messaging Unit Device Node: +============================= + +Required properties: +------------------- +- compatible : should be "fsl,<chip>-mu", the supported chips include + imx6sx, imx7s, imx8qxp, imx8qm. + The "fsl,imx6sx-mu" compatible is seen as generic and should + be included together with SoC specific compatible. +- reg : Should contain the registers location and length +- interrupts : Interrupt number. The interrupt specifier format depends + on the interrupt controller parent. +- #mbox-cells: Must be 2. + <&phandle type channel> + phandle : Label name of controller + type : Channel type + channel : Channel number + + This MU support 4 type of unidirectional channels, each type + has 4 channels. A total of 16 channels. Following types are + supported: + 0 - TX channel with 32bit transmit register and IRQ transmit + acknowledgment support. + 1 - RX channel with 32bit receive register and IRQ support + 2 - TX doorbell channel. Without own register and no ACK support. + 3 - RX doorbell channel. + +Optional properties: +------------------- +- clocks : phandle to the input clock. +- fsl,mu-side-b : Should be set for side B MU. + +Examples: +-------- +lsio_mu0: mailbox@5d1b0000 { + compatible = "fsl,imx8qxp-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; +}; diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt new file mode 100644 index 000000000000..7d72b21c9e94 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -0,0 +1,57 @@ +MediaTek GCE +=============== + +The Global Command Engine (GCE) is used to help read/write registers with +critical time limitation, such as updating display configuration during the +vblank. The GCE can be used to implement the Command Queue (CMDQ) driver. + +CMDQ driver uses mailbox framework for communication. Please refer to +mailbox.txt for generic information about mailbox device-tree bindings. + +Required properties: +- compatible: Must be "mediatek,mt8173-gce" +- reg: Address range of the GCE unit +- interrupts: The interrupt signal from the GCE block +- clock: Clocks according to the common clock binding +- clock-names: Must be "gce" to stand for GCE clock +- #mbox-cells: Should be 3. + <&phandle channel priority atomic_exec> + phandle: Label name of a gce node. + channel: Channel of mailbox. Be equal to the thread id of GCE. + priority: Priority of GCE thread. + atomic_exec: GCE processing continuous packets of commands in atomic + way. + +Required properties for a client device: +- mboxes: Client use mailbox to communicate with GCE, it should have this + property and list of phandle, mailbox specifiers. +- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding + to the register address. + +Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as +sub-system ids, thread priority, event ids. + +Example: + + gce: gce@10212000 { + compatible = "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + thread-num = CMDQ_THR_MAX_COUNT; + #mbox-cells = <3>; + }; + +Example for a client device: + + mmsys: clock-controller@14000000 { + compatible = "mediatek,mt8173-mmsys"; + mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>, + <&gce 1 CMDQ_THR_PRIO_LOWEST 1>; + mediatek,gce-subsys = <SUBSYS_1400XXXX>; + mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF + CMDQ_EVENT_MUTEX1_STREAM_EOF>; + + ... + }; diff --git a/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt b/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt new file mode 100644 index 000000000000..6c9c7daf0f5c --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt @@ -0,0 +1,50 @@ +Texas Instruments' Secure Proxy +======================================== + +The Texas Instruments' secure proxy is a mailbox controller that has +configurable queues selectable at SoC(System on Chip) integration. The +Message manager is broken up into different address regions that are +called "threads" or "proxies" - each instance is unidirectional and is +instantiated at SoC integration level by system controller to indicate +receive or transmit path. + +Message Manager Device Node: +=========================== +Required properties: +-------------------- +- compatible: Shall be "ti,am654-secure-proxy" +- reg-names target_data - Map the proxy data region + rt - Map the realtime status region + scfg - Map the configuration region +- reg: Contains the register map per reg-names. +- #mbox-cells Shall be 1 and shall refer to the transfer path + called thread. +- interrupt-names: Contains interrupt names matching the rx transfer path + for a given SoC. Receive interrupts shall be of the + format: "rx_<PID>". +- interrupts: Contains the interrupt information corresponding to + interrupt-names property. + +Example(AM654): +------------ + + secure_proxy: mailbox@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x32c00000 0x0 0x100000>, + <0x0 0x32400000 0x0 0x100000>, + <0x0 0x32800000 0x0 0x100000>; + interrupt-names = "rx_011"; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + + dmsc: dmsc { + [...] + mbox-names = "rx", "tx"; + # RX Thread ID is 11 + # TX Thread ID is 13 + mboxes= <&secure_proxy 11>, + <&secure_proxy 13>; + [...] + }; diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index e63d29a95e76..841c005d8ebb 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -15,6 +15,12 @@ config ARM_MHU The controller has 3 mailbox channels, the last of which can be used in Secure mode only. +config IMX_MBOX + tristate "i.MX Mailbox" + depends on ARCH_MXC || COMPILE_TEST + help + Mailbox implementation for i.MX Messaging Unit (MU). + config PLATFORM_MHU tristate "Platform MHU Mailbox" depends on OF @@ -189,4 +195,14 @@ config STM32_IPCC Mailbox implementation for STMicroelectonics STM32 family chips with hardware for Inter-Processor Communication Controller (IPCC) between processors. Say Y here if you want to have this support. + +config MTK_CMDQ_MBOX + tristate "MediaTek CMDQ Mailbox Support" + depends on ARCH_MEDIATEK || COMPILE_TEST + select MTK_INFRACFG + help + Say yes here to add support for the MediaTek Command Queue (CMDQ) + mailbox driver. The CMDQ is used to help read/write registers with + critical time limitation, such as updating display configuration + during the vblank. endif diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 4d501bea7863..c818b5d011ae 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o obj-$(CONFIG_ARM_MHU) += arm_mhu.o +obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o + obj-$(CONFIG_PLATFORM_MHU) += platform_mhu.o obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o @@ -40,3 +42,5 @@ obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o + +obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c new file mode 100644 index 000000000000..363d35d5e49d --- /dev/null +++ b/drivers/mailbox/imx-mailbox.c @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> + */ + +#include <linux/clk.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mailbox_controller.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/slab.h> + +/* Transmit Register */ +#define IMX_MU_xTRn(x) (0x00 + 4 * (x)) +/* Receive Register */ +#define IMX_MU_xRRn(x) (0x10 + 4 * (x)) +/* Status Register */ +#define IMX_MU_xSR 0x20 +#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x))) +#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x))) +#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x))) +#define IMX_MU_xSR_BRDIP BIT(9) + +/* Control Register */ +#define IMX_MU_xCR 0x24 +/* General Purpose Interrupt Enable */ +#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x))) +/* Receive Interrupt Enable */ +#define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x))) +/* Transmit Interrupt Enable */ +#define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x))) +/* General Purpose Interrupt Request */ +#define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x))) + +#define IMX_MU_CHANS 16 +#define IMX_MU_CHAN_NAME_SIZE 20 + +enum imx_mu_chan_type { + IMX_MU_TYPE_TX, /* Tx */ + IMX_MU_TYPE_RX, /* Rx */ + IMX_MU_TYPE_TXDB, /* Tx doorbell */ + IMX_MU_TYPE_RXDB, /* Rx doorbell */ +}; + +struct imx_mu_con_priv { + unsigned int idx; + char irq_desc[IMX_MU_CHAN_NAME_SIZE]; + enum imx_mu_chan_type type; + struct mbox_chan *chan; + struct tasklet_struct txdb_tasklet; +}; + +struct imx_mu_priv { + struct device *dev; + void __iomem *base; + spinlock_t xcr_lock; /* control register lock */ + + struct mbox_controller mbox; + struct mbox_chan mbox_chans[IMX_MU_CHANS]; + + struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; + struct clk *clk; + int irq; + + bool side_b; +}; + +static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) +{ + return container_of(mbox, struct imx_mu_priv, mbox); +} + +static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs) +{ + iowrite32(val, priv->base + offs); +} + +static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) +{ + return ioread32(priv->base + offs); +} + +static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&priv->xcr_lock, flags); + val = imx_mu_read(priv, IMX_MU_xCR); + val &= ~clr; + val |= set; + imx_mu_write(priv, val, IMX_MU_xCR); + spin_unlock_irqrestore(&priv->xcr_lock, flags); + + return val; +} + +static void imx_mu_txdb_tasklet(unsigned long data) +{ + struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data; + + mbox_chan_txdone(cp->chan, 0); +} + +static irqreturn_t imx_mu_isr(int irq, void *p) +{ + struct mbox_chan *chan = p; + struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); + struct imx_mu_con_priv *cp = chan->con_priv; + u32 val, ctrl, dat; + + ctrl = imx_mu_read(priv, IMX_MU_xCR); + val = imx_mu_read(priv, IMX_MU_xSR); + + switch (cp->type) { + case IMX_MU_TYPE_TX: + val &= IMX_MU_xSR_TEn(cp->idx) & + (ctrl & IMX_MU_xCR_TIEn(cp->idx)); + break; + case IMX_MU_TYPE_RX: + val &= IMX_MU_xSR_RFn(cp->idx) & + (ctrl & IMX_MU_xCR_RIEn(cp->idx)); + break; + case IMX_MU_TYPE_RXDB: + val &= IMX_MU_xSR_GIPn(cp->idx) & + (ctrl & IMX_MU_xCR_GIEn(cp->idx)); + break; + default: + break; + } + + if (!val) + return IRQ_NONE; + + if (val == IMX_MU_xSR_TEn(cp->idx)) { + imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); + mbox_chan_txdone(chan, 0); + } else if (val == IMX_MU_xSR_RFn(cp->idx)) { + dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx)); + mbox_chan_received_data(chan, (void *)&dat); + } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { + imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR); + mbox_chan_received_data(chan, NULL); + } else { + dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); + return IRQ_NONE; + } + + return IRQ_HANDLED; +} + +static int imx_mu_send_data(struct mbox_chan *chan, void *data) +{ + struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); + struct imx_mu_con_priv *cp = chan->con_priv; + u32 *arg = data; + + switch (cp->type) { + case IMX_MU_TYPE_TX: + imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx)); + imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); + break; + case IMX_MU_TYPE_TXDB: + imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0); + tasklet_schedule(&cp->txdb_tasklet); + break; + default: + dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); + return -EINVAL; + } + + return 0; +} + +static int imx_mu_startup(struct mbox_chan *chan) +{ + struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); + struct imx_mu_con_priv *cp = chan->con_priv; + int ret; + + if (cp->type == IMX_MU_TYPE_TXDB) { + /* Tx doorbell don't have ACK support */ + tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet, + (unsigned long)cp); + return 0; + } + + ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED, cp->irq_desc, + chan); + if (ret) { + dev_err(priv->dev, + "Unable to acquire IRQ %d\n", priv->irq); + return ret; + } + + switch (cp->type) { + case IMX_MU_TYPE_RX: + imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0); + break; + case IMX_MU_TYPE_RXDB: + imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0); + break; + default: + break; + } + + return 0; +} + +static void imx_mu_shutdown(struct mbox_chan *chan) +{ + struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); + struct imx_mu_con_priv *cp = chan->con_priv; + + if (cp->type == IMX_MU_TYPE_TXDB) + tasklet_kill(&cp->txdb_tasklet); + + imx_mu_xcr_rmw(priv, 0, + IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx)); + + free_irq(priv->irq, chan); +} + +static const struct mbox_chan_ops imx_mu_ops = { + .send_data = imx_mu_send_data, + .startup = imx_mu_startup, + .shutdown = imx_mu_shutdown, +}; + +static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + u32 type, idx, chan; + + if (sp->args_count != 2) { + dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); + return ERR_PTR(-EINVAL); + } + + type = sp->args[0]; /* channel type */ + idx = sp->args[1]; /* index */ + chan = type * 4 + idx; + + if (chan >= mbox->num_chans) { + dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); + return ERR_PTR(-EINVAL); + } + + return &mbox->chans[chan]; +} + +static void imx_mu_init_generic(struct imx_mu_priv *priv) +{ + if (priv->side_b) + return; + + /* Set default MU configuration */ + imx_mu_write(priv, 0, IMX_MU_xCR); +} + +static int imx_mu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct resource *iomem; + struct imx_mu_priv *priv; + unsigned int i; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(&pdev->dev, iomem); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->irq = platform_get_irq(pdev, 0); + if (priv->irq < 0) + return priv->irq; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + if (PTR_ERR(priv->clk) != -ENOENT) + return PTR_ERR(priv->clk); + + priv->clk = NULL; + } + + ret = clk_prepare_enable(priv->clk); + if (ret) { + dev_err(dev, "Failed to enable clock\n"); + return ret; + } + + for (i = 0; i < IMX_MU_CHANS; i++) { + struct imx_mu_con_priv *cp = &priv->con_priv[i]; + + cp->idx = i % 4; + cp->type = i >> 2; + cp->chan = &priv->mbox_chans[i]; + priv->mbox_chans[i].con_priv = cp; + snprintf(cp->irq_desc, sizeof(cp->irq_desc), + "imx_mu_chan[%i-%i]", cp->type, cp->idx); + } + + priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); + + spin_lock_init(&priv->xcr_lock); + + priv->mbox.dev = dev; + priv->mbox.ops = &imx_mu_ops; + priv->mbox.chans = priv->mbox_chans; + priv->mbox.num_chans = IMX_MU_CHANS; + priv->mbox.of_xlate = imx_mu_xlate; + priv->mbox.txdone_irq = true; + + platform_set_drvdata(pdev, priv); + + imx_mu_init_generic(priv); + + return mbox_controller_register(&priv->mbox); +} + +static int imx_mu_remove(struct platform_device *pdev) +{ + struct imx_mu_priv *priv = platform_get_drvdata(pdev); + + mbox_controller_unregister(&priv->mbox); + clk_disable_unprepare(priv->clk); + + return 0; +} + +static const struct of_device_id imx_mu_dt_ids[] = { + { .compatible = "fsl,imx6sx-mu" }, + { }, +}; +MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); + +static struct platform_driver imx_mu_driver = { + .probe = imx_mu_probe, + .remove = imx_mu_remove, + .driver = { + .name = "imx_mu", + .of_match_table = imx_mu_dt_ids, + }, +}; +module_platform_driver(imx_mu_driver); + +MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); +MODULE_DESCRIPTION("Message Unit driver for i.MX"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mailbox/mailbox-xgene-slimpro.c b/drivers/mailbox/mailbox-xgene-slimpro.c index a7040163dd43..b8b2b3533f46 100644 --- a/drivers/mailbox/mailbox-xgene-slimpro.c +++ b/drivers/mailbox/mailbox-xgene-slimpro.c @@ -195,9 +195,9 @@ static int slimpro_mbox_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ctx); regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mb_base = devm_ioremap(&pdev->dev, regs->start, resource_size(regs)); - if (!mb_base) - return -ENOMEM; + mb_base = devm_ioremap_resource(&pdev->dev, regs); + if (IS_ERR(mb_base)) + return PTR_ERR(mb_base); /* Setup mailbox links */ for (i = 0; i < MBOX_CNT; i++) { diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c new file mode 100644 index 000000000000..aec46d5d3506 --- /dev/null +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2018 MediaTek Inc. + +#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/dma-mapping.h> +#include <linux/errno.h> +#include <linux/interrupt.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/mailbox_controller.h> +#include <linux/mailbox/mtk-cmdq-mailbox.h> +#include <linux/of_device.h> + +#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) +#define CMDQ_IRQ_MASK 0xffff +#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) + +#define CMDQ_CURR_IRQ_STATUS 0x10 +#define CMDQ_THR_SLOT_CYCLES 0x30 +#define CMDQ_THR_BASE 0x100 +#define CMDQ_THR_SIZE 0x80 +#define CMDQ_THR_WARM_RESET 0x00 +#define CMDQ_THR_ENABLE_TASK 0x04 +#define CMDQ_THR_SUSPEND_TASK 0x08 +#define CMDQ_THR_CURR_STATUS 0x0c +#define CMDQ_THR_IRQ_STATUS 0x10 +#define CMDQ_THR_IRQ_ENABLE 0x14 +#define CMDQ_THR_CURR_ADDR 0x20 +#define CMDQ_THR_END_ADDR 0x24 +#define CMDQ_THR_WAIT_TOKEN 0x30 +#define CMDQ_THR_PRIORITY 0x40 + +#define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 +#define CMDQ_THR_ENABLED 0x1 +#define CMDQ_THR_DISABLED 0x0 +#define CMDQ_THR_SUSPEND 0x1 +#define CMDQ_THR_RESUME 0x0 +#define CMDQ_THR_STATUS_SUSPENDED BIT(1) +#define CMDQ_THR_DO_WARM_RESET BIT(0) +#define CMDQ_THR_IRQ_DONE 0x1 +#define CMDQ_THR_IRQ_ERROR 0x12 +#define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE) +#define CMDQ_THR_IS_WAITING BIT(31) + +#define CMDQ_JUMP_BY_OFFSET 0x10000000 +#define CMDQ_JUMP_BY_PA 0x10000001 + +struct cmdq_thread { + struct mbox_chan *chan; + void __iomem *base; + struct list_head task_busy_list; + u32 priority; + bool atomic_exec; +}; + +struct cmdq_task { + struct cmdq *cmdq; + struct list_head list_entry; + dma_addr_t pa_base; + struct cmdq_thread *thread; + struct cmdq_pkt *pkt; /* the packet sent from mailbox client */ +}; + +struct cmdq { + struct mbox_controller mbox; + void __iomem *base; + u32 irq; + u32 thread_nr; + struct cmdq_thread *thread; + struct clk *clock; + bool suspended; +}; + +static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread) +{ + u32 status; + + writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK); + + /* If already disabled, treat as suspended successful. */ + if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) + return 0; + + if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS, + status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) { + dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n", + (u32)(thread->base - cmdq->base)); + return -EFAULT; + } + + return 0; +} + +static void cmdq_thread_resume(struct cmdq_thread *thread) +{ + writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK); +} + +static void cmdq_init(struct cmdq *cmdq) +{ + WARN_ON(clk_enable(cmdq->clock) < 0); + writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); + clk_disable(cmdq->clock); +} + +static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread) +{ + u32 warm_reset; + + writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET); + if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET, + warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET), + 0, 10)) { + dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n", + (u32)(thread->base - cmdq->base)); + return -EFAULT; + } + + return 0; +} + +static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread) +{ + cmdq_thread_reset(cmdq, thread); + writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK); +} + +/* notify GCE to re-fetch commands by setting GCE thread PC */ +static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread) +{ + writel(readl(thread->base + CMDQ_THR_CURR_ADDR), + thread->base + CMDQ_THR_CURR_ADDR); +} + +static void cmdq_task_insert_into_thread(struct cmdq_task *task) +{ + struct device *dev = task->cmdq->mbox.dev; + struct cmdq_thread *thread = task->thread; + struct cmdq_task *prev_task = list_last_entry( + &thread->task_busy_list, typeof(*task), list_entry); + u64 *prev_task_base = prev_task->pkt->va_base; + + /* let previous task jump to this task */ + dma_sync_single_for_cpu(dev, prev_task->pa_base, + prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); + prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] = + (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base; + dma_sync_single_for_device(dev, prev_task->pa_base, + prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); + + cmdq_thread_invalidate_fetched_data(thread); +} + +static bool cmdq_command_is_wfe(u64 cmd) +{ + u64 wfe_option = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE; + u64 wfe_op = (u64)(CMDQ_CODE_WFE << CMDQ_OP_CODE_SHIFT) << 32; + u64 wfe_mask = (u64)CMDQ_OP_CODE_MASK << 32 | 0xffffffff; + + return ((cmd & wfe_mask) == (wfe_op | wfe_option)); +} + +/* we assume tasks in the same display GCE thread are waiting the same event. */ +static void cmdq_task_remove_wfe(struct cmdq_task *task) +{ + struct device *dev = task->cmdq->mbox.dev; + u64 *base = task->pkt->va_base; + int i; + + dma_sync_single_for_cpu(dev, task->pa_base, task->pkt->cmd_buf_size, + DMA_TO_DEVICE); + for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++) + if (cmdq_command_is_wfe(base[i])) + base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 | + CMDQ_JUMP_PASS; + dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size, + DMA_TO_DEVICE); +} + +static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread) +{ + return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING; +} + +static void cmdq_thread_wait_end(struct cmdq_thread *thread, + unsigned long end_pa) +{ + struct device *dev = thread->chan->mbox->dev; + unsigned long curr_pa; + + if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_ADDR, + curr_pa, curr_pa == end_pa, 1, 20)) + dev_err(dev, "GCE thread cannot run to end.\n"); +} + +static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status sta) +{ + struct cmdq_task_cb *cb = &task->pkt->async_cb; + struct cmdq_cb_data data; + + WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL); + data.sta = sta; + data.data = cb->data; + cb->cb(data); + + list_del(&task->list_entry); +} + +static void cmdq_task_handle_error(struct cmdq_task *task) +{ + struct cmdq_thread *thread = task->thread; + struct cmdq_task *next_task; + + dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task); + WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0); + next_task = list_first_entry_or_null(&thread->task_busy_list, + struct cmdq_task, list_entry); + if (next_task) + writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR); + cmdq_thread_resume(thread); +} + +static void cmdq_thread_irq_handler(struct cmdq *cmdq, + struct cmdq_thread *thread) +{ + struct cmdq_task *task, *tmp, *curr_task = NULL; + u32 curr_pa, irq_flag, task_end_pa; + bool err; + + irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS); + writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS); + + /* + * When ISR call this function, another CPU core could run + * "release task" right before we acquire the spin lock, and thus + * reset / disable this GCE thread, so we need to check the enable + * bit of this GCE thread. + */ + if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) + return; + + if (irq_flag & CMDQ_THR_IRQ_ERROR) + err = true; + else if (irq_flag & CMDQ_THR_IRQ_DONE) + err = false; + else + return; + + curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR); + + list_for_each_entry_safe(task, tmp, &thread->task_busy_list, + list_entry) { + task_end_pa = task->pa_base + task->pkt->cmd_buf_size; + if (curr_pa >= task->pa_base && curr_pa < task_end_pa) + curr_task = task; + + if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) { + cmdq_task_exec_done(task, CMDQ_CB_NORMAL); + kfree(task); + } else if (err) { + cmdq_task_exec_done(task, CMDQ_CB_ERROR); + cmdq_task_handle_error(curr_task); + kfree(task); + } + + if (curr_task) + break; + } + + if (list_empty(&thread->task_busy_list)) { + cmdq_thread_disable(cmdq, thread); + clk_disable(cmdq->clock); + } +} + +static irqreturn_t cmdq_irq_handler(int irq, void *dev) +{ + struct cmdq *cmdq = dev; + unsigned long irq_status, flags = 0L; + int bit; + + irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK; + if (!(irq_status ^ CMDQ_IRQ_MASK)) + return IRQ_NONE; + + for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) { + struct cmdq_thread *thread = &cmdq->thread[bit]; + + spin_lock_irqsave(&thread->chan->lock, flags); + cmdq_thread_irq_handler(cmdq, thread); + spin_unlock_irqrestore(&thread->chan->lock, flags); + } + + return IRQ_HANDLED; +} + +static int cmdq_suspend(struct device *dev) +{ + struct cmdq *cmdq = dev_get_drvdata(dev); + struct cmdq_thread *thread; + int i; + bool task_running = false; + + cmdq->suspended = true; + + for (i = 0; i < cmdq->thread_nr; i++) { + thread = &cmdq->thread[i]; + if (!list_empty(&thread->task_busy_list)) { + task_running = true; + break; + } + } + + if (task_running) + dev_warn(dev, "exist running task(s) in suspend\n"); + + clk_unprepare(cmdq->clock); + + return 0; +} + +static int cmdq_resume(struct device *dev) +{ + struct cmdq *cmdq = dev_get_drvdata(dev); + + WARN_ON(clk_prepare(cmdq->clock) < 0); + cmdq->suspended = false; + return 0; +} + +static int cmdq_remove(struct platform_device *pdev) +{ + struct cmdq *cmdq = platform_get_drvdata(pdev); + + mbox_controller_unregister(&cmdq->mbox); + clk_unprepare(cmdq->clock); + + if (cmdq->mbox.chans) + devm_kfree(&pdev->dev, cmdq->mbox.chans); + + if (cmdq->thread) + devm_kfree(&pdev->dev, cmdq->thread); + + devm_kfree(&pdev->dev, cmdq); + + return 0; +} + +static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct cmdq_pkt *pkt = (struct cmdq_pkt *)data; + struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; + struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); + struct cmdq_task *task; + unsigned long curr_pa, end_pa; + + /* Client should not flush new tasks if suspended. */ + WARN_ON(cmdq->suspended); + + task = kzalloc(sizeof(*task), GFP_ATOMIC); + task->cmdq = cmdq; + INIT_LIST_HEAD(&task->list_entry); + task->pa_base = pkt->pa_base; + task->thread = thread; + task->pkt = pkt; + + if (list_empty(&thread->task_busy_list)) { + WARN_ON(clk_enable(cmdq->clock) < 0); + WARN_ON(cmdq_thread_reset(cmdq, thread) < 0); + + writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR); + writel(task->pa_base + pkt->cmd_buf_size, + thread->base + CMDQ_THR_END_ADDR); + writel(thread->priority, thread->base + CMDQ_THR_PRIORITY); + writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE); + writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK); + } else { + WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); + curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR); + end_pa = readl(thread->base + CMDQ_THR_END_ADDR); + + /* + * Atomic execution should remove the following wfe, i.e. only + * wait event at first task, and prevent to pause when running. + */ + if (thread->atomic_exec) { + /* GCE is executing if command is not WFE */ + if (!cmdq_thread_is_in_wfe(thread)) { + cmdq_thread_resume(thread); + cmdq_thread_wait_end(thread, end_pa); + WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); + /* set to this task directly */ + writel(task->pa_base, + thread->base + CMDQ_THR_CURR_ADDR); + } else { + cmdq_task_insert_into_thread(task); + cmdq_task_remove_wfe(task); + smp_mb(); /* modify jump before enable thread */ + } + } else { + /* check boundary */ + if (curr_pa == end_pa - CMDQ_INST_SIZE || + curr_pa == end_pa) { + /* set to this task directly */ + writel(task->pa_base, + thread->base + CMDQ_THR_CURR_ADDR); + } else { + cmdq_task_insert_into_thread(task); + smp_mb(); /* modify jump before enable thread */ + } + } + writel(task->pa_base + pkt->cmd_buf_size, + thread->base + CMDQ_THR_END_ADDR); + cmdq_thread_resume(thread); + } + list_move_tail(&task->list_entry, &thread->task_busy_list); + + return 0; +} + +static int cmdq_mbox_startup(struct mbox_chan *chan) +{ + return |