diff options
32 files changed, 1252 insertions, 418 deletions
diff --git a/Documentation/devicetree/bindings/eeprom/eeprom.txt b/Documentation/devicetree/bindings/eeprom/eeprom.txt index 4342c10de1bf..735bc94444bb 100644 --- a/Documentation/devicetree/bindings/eeprom/eeprom.txt +++ b/Documentation/devicetree/bindings/eeprom/eeprom.txt @@ -2,11 +2,22 @@ EEPROMs (I2C) Required properties: - - compatible : should be "<manufacturer>,<type>" - If there is no specific driver for <manufacturer>, a generic - driver based on <type> is selected. Possible types are: - 24c00, 24c01, 24c02, 24c04, 24c08, 24c16, 24c32, 24c64, - 24c128, 24c256, 24c512, 24c1024, spd + - compatible : should be "<manufacturer>,<type>", like these: + + "atmel,24c00", "atmel,24c01", "atmel,24c02", "atmel,24c04", + "atmel,24c08", "atmel,24c16", "atmel,24c32", "atmel,24c64", + "atmel,24c128", "atmel,24c256", "atmel,24c512", "atmel,24c1024" + + "catalyst,24c32" + + "ramtron,24c64" + + "renesas,r1ex24002" + + If there is no specific driver for <manufacturer>, a generic + driver based on <type> is selected. Possible types are: + "24c00", "24c01", "24c02", "24c04", "24c08", "24c16", "24c32", "24c64", + "24c128", "24c256", "24c512", "24c1024", "spd" - reg : the I2C address of the EEPROM diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt index 6e81dc153f3b..ef973a0343c7 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt @@ -3,7 +3,7 @@ I2C for Atmel platforms Required properties : - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c", "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c", - "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c" + "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c" - reg: physical base address of the controller and length of memory mapped region. - interrupts: interrupt number to the cpu. @@ -17,6 +17,8 @@ Optional properties: - dma-names: should contain "tx" and "rx". - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO capable I2C controllers. +- i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c" + and "atmel,sama5d2-i2c". - Child nodes conforming to i2c bus binding Examples : @@ -52,6 +54,7 @@ i2c0: i2c@f8034600 { #size-cells = <0>; clocks = <&flx0>; atmel,fifo-size = <16>; + i2c-sda-hold-time-ns = <336>; wm8731: wm8731@1a { compatible = "wm8731"; diff --git a/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt b/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt index d6f724efdcf2..aeceaceba3c5 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt @@ -2,7 +2,7 @@ Broadcom stb bsc iic master controller Required properties: -- compatible: should be "brcm,brcmstb-i2c" +- compatible: should be "brcm,brcmstb-i2c" or "brcm,brcmper-i2c" - clock-frequency: 32-bit decimal value of iic master clock freqency in Hz valid values are 375000, 390000, 187500, 200000 93750, 97500, 46875 and 50000 diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt index ea406eb20fa5..95e97223a71c 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt @@ -20,6 +20,10 @@ Optional properties: propoerty indicates the default frequency 100 kHz. - clocks: clock specifier. +- i2c-scl-falling-time-ns: see i2c.txt +- i2c-scl-internal-delay-ns: see i2c.txt +- i2c-scl-rising-time-ns: see i2c.txt + Examples : i2c0: i2c@e6508000 { diff --git a/Documentation/devicetree/bindings/i2c/i2c.txt b/Documentation/devicetree/bindings/i2c/i2c.txt index 8a99150ac3a7..c8d977ed847f 100644 --- a/Documentation/devicetree/bindings/i2c/i2c.txt +++ b/Documentation/devicetree/bindings/i2c/i2c.txt @@ -29,12 +29,38 @@ Optional properties These properties may not be supported by all drivers. However, if a driver wants to support one of the below features, it should adapt the bindings below. -- clock-frequency - frequency of bus clock in Hz. -- wakeup-source - device can be used as a wakeup source. +- clock-frequency + frequency of bus clock in Hz. -- interrupts - interrupts used by the device. -- interrupt-names - "irq" and "wakeup" names are recognized by I2C core, - other names are left to individual drivers. +- i2c-scl-falling-time-ns + Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C + specification. + +- i2c-scl-internal-delay-ns + Number of nanoseconds the IP core additionally needs to setup SCL. + +- i2c-scl-rising-time-ns + Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C + specification. + +- i2c-sda-falling-time-ns + Number of nanoseconds the SDA signal takes to fall; t(f) in the I2C + specification. + +- interrupts + interrupts used by the device. + +- interrupt-names + "irq" and "wakeup" names are recognized by I2C core, other names are + left to individual drivers. + +- multi-master + states that there is another master active on this bus. The OS can use + this information to adapt power management to keep the arbitration awake + all the time, for example. + +- wakeup-source + device can be used as a wakeup source. Binding may contain optional "interrupts" property, describing interrupts used by the device. I2C core will assign "irq" interrupt (or the very first diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index f6fec952d683..539874490492 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -22,21 +22,9 @@ adi,adxl345 Three-Axis Digital Accelerometer adi,adxl346 Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too) ams,iaq-core AMS iAQ-Core VOC Sensor at,24c08 i2c serial eeprom (24cxx) -atmel,24c00 i2c serial eeprom (24cxx) -atmel,24c01 i2c serial eeprom (24cxx) -atmel,24c02 i2c serial eeprom (24cxx) -atmel,24c04 i2c serial eeprom (24cxx) -atmel,24c16 i2c serial eeprom (24cxx) -atmel,24c32 i2c serial eeprom (24cxx) -atmel,24c64 i2c serial eeprom (24cxx) -atmel,24c128 i2c serial eeprom (24cxx) -atmel,24c256 i2c serial eeprom (24cxx) -atmel,24c512 i2c serial eeprom (24cxx) -atmel,24c1024 i2c serial eeprom (24cxx) atmel,at97sc3204t i2c trusted platform module (TPM) capella,cm32181 CM32181: Ambient Light Sensor capella,cm3232 CM3232: Ambient Light Sensor -catalyst,24c32 i2c serial eeprom cirrus,cs42l51 Cirrus Logic CS42L51 audio codec dallas,ds1307 64 x 8, Serial, I2C Real-Time Clock dallas,ds1338 I2C RTC with 56-Byte NV RAM @@ -50,11 +38,13 @@ dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O dallas,ds75 Digital Thermometer and Thermostat dlg,da9053 DA9053: flexible system level PMIC with multicore support dlg,da9063 DA9063: system PMIC for quad-core application processors +epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51 fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer +fsl,mpl3115 MPL3115: Absolute Digital Pressure Sensor fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface @@ -81,7 +71,6 @@ ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI an pericom,pt7c4338 Real-time Clock Module plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch pulsedlight,lidar-lite-v2 Pulsedlight LIDAR range-finding sensor -ramtron,24c64 i2c serial eeprom (24cxx) ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC diff --git a/drivers/i2c/algos/i2c-algo-bit.c b/drivers/i2c/algos/i2c-algo-bit.c index 899bede81b31..9d233bbde5e1 100644 --- a/drivers/i2c/algos/i2c-algo-bit.c +++ b/drivers/i2c/algos/i2c-algo-bit.c @@ -617,6 +617,10 @@ const struct i2c_algorithm i2c_bit_algo = { }; EXPORT_SYMBOL(i2c_bit_algo); +const struct i2c_adapter_quirks i2c_bit_quirk_no_clk_stretch = { + .flags = I2C_AQ_NO_CLK_STRETCH, +}; + /* * registering functions to load algorithms at runtime */ @@ -635,6 +639,8 @@ static int __i2c_bit_add_bus(struct i2c_adapter *adap, /* register new adapter to i2c module... */ adap->algo = &i2c_bit_algo; adap->retries = 3; + if (bit_adap->getscl == NULL) + adap->quirks = &i2c_bit_quirk_no_clk_stretch; ret = add_adapter(adap); if (ret < 0) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 7b0aa82ea38b..0299dfa746a3 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -516,7 +516,7 @@ config I2C_EFM32 config I2C_EG20T tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) I2C" - depends on PCI && (X86_32 || COMPILE_TEST) + depends on PCI && (X86_32 || MIPS || COMPILE_TEST) help This driver is for PCH(Platform controller Hub) I2C of EG20T which is an IOH(Input/Output Hub) for x86 embedded processor. @@ -532,6 +532,7 @@ config I2C_EG20T config I2C_EMEV2 tristate "EMMA Mobile series I2C adapter" depends on HAVE_CLK + select I2C_SLAVE help If you say yes to this option, support will be included for the I2C interface on the Renesas Electronics EM/EV family of processors. @@ -963,11 +964,11 @@ config I2C_XILINX will be called xilinx_i2c. config I2C_XLR - tristate "XLR I2C support" - depends on CPU_XLR + tristate "Netlogic XLR and Sigma Designs I2C support" + depends on CPU_XLR || ARCH_TANGOX help This driver enables support for the on-chip I2C interface of - the Netlogic XLR/XLS MIPS processors. + the Netlogic XLR/XLS MIPS processors and Sigma Designs SOCs. This driver can also be built as a module. If so, the module will be called i2c-xlr. diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c index 10835d1f559b..921d32bfcda8 100644 --- a/drivers/i2c/busses/i2c-at91.c +++ b/drivers/i2c/busses/i2c-at91.c @@ -64,6 +64,8 @@ #define AT91_TWI_IADR 0x000c /* Internal Address Register */ #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */ +#define AT91_TWI_CWGR_HOLD_MAX 0x1f +#define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24) #define AT91_TWI_SR 0x0020 /* Status Register */ #define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */ @@ -110,6 +112,7 @@ struct at91_twi_pdata { unsigned clk_offset; bool has_unre_flag; bool has_alt_cmd; + bool has_hold_field; struct at_dma_slave dma_slave; }; @@ -187,10 +190,11 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev) */ static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk) { - int ckdiv, cdiv, div; + int ckdiv, cdiv, div, hold = 0; struct at91_twi_pdata *pdata = dev->pdata; int offset = pdata->clk_offset; int max_ckdiv = pdata->clk_max_div; + u32 twd_hold_time_ns = 0; div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk), 2 * twi_clk) - offset); @@ -204,8 +208,33 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk) cdiv = 255; } - dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv; - dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv); + if (pdata->has_hold_field) { + of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns", + &twd_hold_time_ns); + + /* + * hold time = HOLD + 3 x T_peripheral_clock + * Use clk rate in kHz to prevent overflows when computing + * hold. + */ + hold = DIV_ROUND_UP(twd_hold_time_ns + * (clk_get_rate(dev->clk) / 1000), 1000000); + hold -= 3; + if (hold < 0) + hold = 0; + if (hold > AT91_TWI_CWGR_HOLD_MAX) { + dev_warn(dev->dev, + "HOLD field set to its maximum value (%d instead of %d)\n", + AT91_TWI_CWGR_HOLD_MAX, hold); + hold = AT91_TWI_CWGR_HOLD_MAX; + } + } + + dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv + | AT91_TWI_CWGR_HOLD(hold); + + dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n", + cdiv, ckdiv, hold, twd_hold_time_ns); } static void at91_twi_dma_cleanup(struct at91_twi_dev *dev) @@ -797,6 +826,7 @@ static struct at91_twi_pdata at91rm9200_config = { .clk_offset = 3, .has_unre_flag = true, .has_alt_cmd = false, + .has_hold_field = false, }; static struct at91_twi_pdata at91sam9261_config = { @@ -804,6 +834,7 @@ static struct at91_twi_pdata at91sam9261_config = { .clk_offset = 4, .has_unre_flag = false, .has_alt_cmd = false, + .has_hold_field = false, }; static struct at91_twi_pdata at91sam9260_config = { @@ -811,6 +842,7 @@ static struct at91_twi_pdata at91sam9260_config = { .clk_offset = 4, .has_unre_flag = false, .has_alt_cmd = false, + .has_hold_field = false, }; static struct at91_twi_pdata at91sam9g20_config = { @@ -818,6 +850,7 @@ static struct at91_twi_pdata at91sam9g20_config = { .clk_offset = 4, .has_unre_flag = false, .has_alt_cmd = false, + .has_hold_field = false, }; static struct at91_twi_pdata at91sam9g10_config = { @@ -825,6 +858,7 @@ static struct at91_twi_pdata at91sam9g10_config = { .clk_offset = 4, .has_unre_flag = false, .has_alt_cmd = false, + .has_hold_field = false, }; static const struct platform_device_id at91_twi_devtypes[] = { @@ -854,6 +888,15 @@ static struct at91_twi_pdata at91sam9x5_config = { .clk_offset = 4, .has_unre_flag = false, .has_alt_cmd = false, + .has_hold_field = false, +}; + +static struct at91_twi_pdata sama5d4_config = { + .clk_max_div = 7, + .clk_offset = 4, + .has_unre_flag = false, + .has_alt_cmd = false, + .has_hold_field = true, }; static struct at91_twi_pdata sama5d2_config = { @@ -861,6 +904,7 @@ static struct at91_twi_pdata sama5d2_config = { .clk_offset = 4, .has_unre_flag = true, .has_alt_cmd = true, + .has_hold_field = true, }; static const struct of_device_id atmel_twi_dt_ids[] = { @@ -883,6 +927,9 @@ static const struct of_device_id atmel_twi_dt_ids[] = { .compatible = "atmel,at91sam9x5-i2c", .data = &at91sam9x5_config, }, { + .compatible = "atmel,sama5d4-i2c", + .data = &sama5d4_config, + }, { .compatible = "atmel,sama5d2-i2c", .data = &sama5d2_config, }, { diff --git a/drivers/i2c/busses/i2c-bcm2835.c b/drivers/i2c/busses/i2c-bcm2835.c index 3032b89ac60b..818b051d25e6 100644 --- a/drivers/i2c/busses/i2c-bcm2835.c +++ b/drivers/i2c/busses/i2c-bcm2835.c @@ -222,6 +222,15 @@ static const struct i2c_algorithm bcm2835_i2c_algo = { .functionality = bcm2835_i2c_func, }; +/* + * This HW was reported to have problems with clock stretching: + * http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html + * https://www.raspberrypi.org/forums/viewtopic.php?p=146272 + */ +static const struct i2c_adapter_quirks bcm2835_i2c_quirks = { + .flags = I2C_AQ_NO_CLK_STRETCH, +}; + static int bcm2835_i2c_probe(struct platform_device *pdev) { struct bcm2835_i2c_dev *i2c_dev; @@ -293,6 +302,7 @@ static int bcm2835_i2c_probe(struct platform_device *pdev) adap->algo = &bcm2835_i2c_algo; adap->dev.parent = &pdev->dev; adap->dev.of_node = pdev->dev.of_node; + adap->quirks = &bcm2835_i2c_quirks; bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0); diff --git a/drivers/i2c/busses/i2c-brcmstb.c b/drivers/i2c/busses/i2c-brcmstb.c index 8e9637eea512..3711df1d4526 100644 --- a/drivers/i2c/busses/i2c-brcmstb.c +++ b/drivers/i2c/busses/i2c-brcmstb.c @@ -25,13 +25,16 @@ #include <linux/version.h> #define N_DATA_REGS 8 -#define N_DATA_BYTES (N_DATA_REGS * 4) -/* BSC count register field definitions */ -#define BSC_CNT_REG1_MASK 0x0000003f -#define BSC_CNT_REG1_SHIFT 0 -#define BSC_CNT_REG2_MASK 0x00000fc0 -#define BSC_CNT_REG2_SHIFT 6 +/* + * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register + * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per + * data register whereas STB SoCs use 4 byte per data register transfer, + * account for this difference in total count per transaction and mask to + * use. + */ +#define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0)) +#define BSC_CNT_REG1_SHIFT 0 /* BSC CTL register field definitions */ #define BSC_CTL_REG_DTF_MASK 0x00000003 @@ -41,7 +44,7 @@ #define BSC_CTL_REG_INT_EN_SHIFT 6 #define BSC_CTL_REG_DIV_CLK_MASK 0x00000080 -/* BSC_IIC_ENABLE r/w enable and interrupt field defintions */ +/* BSC_IIC_ENABLE r/w enable and interrupt field definitions */ #define BSC_IIC_EN_RESTART_MASK 0x00000040 #define BSC_IIC_EN_NOSTART_MASK 0x00000020 #define BSC_IIC_EN_NOSTOP_MASK 0x00000010 @@ -169,6 +172,7 @@ struct brcmstb_i2c_dev { struct completion done; bool is_suspended; u32 clk_freq_hz; + int data_regsz; }; /* register accessors for both be and le cpu arch */ @@ -186,6 +190,16 @@ struct brcmstb_i2c_dev { #define bsc_writel(_dev, _val, _reg) \ __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg)) +static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev) +{ + return (N_DATA_REGS * dev->data_regsz); +} + +static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev) +{ + return dev->data_regsz; +} + static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev, bool int_en) { @@ -323,14 +337,16 @@ static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev, u8 *buf, unsigned int len, struct i2c_msg *pmsg) { - int cnt, byte, rc; + int cnt, byte, i, rc; enum bsc_xfer_cmd cmd; u32 ctl_reg; struct bsc_regs *pi2creg = dev->bsc_regmap; int no_ack = pmsg->flags & I2C_M_IGNORE_NAK; + int data_regsz = brcmstb_i2c_get_data_regsz(dev); + int xfersz = brcmstb_i2c_get_xfersz(dev); /* see if the transaction needs to check NACK conditions */ - if (no_ack || len <= N_DATA_BYTES) { + if (no_ack || len <= xfersz) { cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK : CMD_WR_NOACK; pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK; @@ -348,20 +364,22 @@ static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev, pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK; /* set the read/write length */ - bsc_writel(dev, BSC_CNT_REG1_MASK & (len << BSC_CNT_REG1_SHIFT), - cnt_reg); + bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) & + (len << BSC_CNT_REG1_SHIFT), cnt_reg); /* Write data into data_in register */ + if (cmd == CMD_WR || cmd == CMD_WR_NOACK) { - for (cnt = 0; cnt < len; cnt += 4) { + for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) { u32 word = 0; - for (byte = 0; byte < 4; byte++) { - word >>= 8; + for (byte = 0; byte < data_regsz; byte++) { + word >>= BITS_PER_BYTE; if ((cnt + byte) < len) - word |= buf[cnt + byte] << 24; + word |= buf[cnt + byte] << + (BITS_PER_BYTE * (data_regsz - 1)); } - bsc_writel(dev, word, data_in[cnt >> 2]); + bsc_writel(dev, word, data_in[i]); } } @@ -373,14 +391,15 @@ static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev, return rc; } + /* Read data from data_out register */ if (cmd == CMD_RD || cmd == CMD_RD_NOACK) { - for (cnt = 0; cnt < len; cnt += 4) { - u32 data = bsc_readl(dev, data_out[cnt >> 2]); + for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) { + u32 data = bsc_readl(dev, data_out[i]); - for (byte = 0; byte < 4 && + for (byte = 0; byte < data_regsz && (byte + cnt) < len; byte++) { buf[cnt + byte] = data & 0xff; - data >>= 8; + data >>= BITS_PER_BYTE; } } } @@ -448,6 +467,7 @@ static int brcmstb_i2c_xfer(struct i2c_adapter *adapter, int bytes_to_xfer; u8 *tmp_buf; int len = 0; + int xfersz = brcmstb_i2c_get_xfersz(dev); if (dev->is_suspended) return -EBUSY; @@ -482,9 +502,9 @@ static int brcmstb_i2c_xfer(struct i2c_adapter *adapter, /* Perform data transfer */ while (len) { - bytes_to_xfer = min(len, N_DATA_BYTES); + bytes_to_xfer = min(len, xfersz); - if (len <= N_DATA_BYTES && i == (num - 1)) + if (len <= xfersz && i == (num - 1)) brcmstb_set_i2c_start_stop(dev, ~(COND_START_STOP)); @@ -542,8 +562,12 @@ static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev) static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev) { - /* 4 byte data register */ - dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK; + if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32)) + /* set 4 byte data in/out xfers */ + dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK; + else + dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK; + bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg); /* set bus speed */ brcmstb_i2c_set_bus_speed(dev); @@ -608,6 +632,13 @@ static int brcmstb_i2c_probe(struct platform_device *pdev) dev->clk_freq_hz = bsc_clk[0].hz; } + /* set the data in/out register size for compatible SoCs */ + if (of_device_is_compatible(dev->device->of_node, + "brcmstb,brcmper-i2c")) + dev->data_regsz = sizeof(u8); + else + dev->data_regsz = sizeof(u32); + brcmstb_i2c_set_bsc_reg_defaults(dev); /* Add the i2c adapter */ @@ -674,6 +705,7 @@ static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend, static const struct of_device_id brcmstb_i2c_of_match[] = { {.compatible = "brcm,brcmstb-i2c"}, + {.compatible = "brcm,brcmper-i2c"}, {}, }; MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match); diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c index 84deed6571bd..6b08d1607b7a 100644 --- a/drivers/i2c/busses/i2c-cadence.c +++ b/drivers/i2c/busses/i2c-cadence.c @@ -18,6 +18,7 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> +#include <linux/pm_runtime.h> /* Register offsets for the I2C device. */ #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */ @@ -96,6 +97,8 @@ CDNS_I2C_IXR_COMP) #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000) +/* timeout for pm runtime autosuspend */ +#define CNDS_I2C_PM_TIMEOUT 1000 /* ms */ #define CDNS_I2C_FIFO_DEPTH 16 /* FIFO depth at which the DATA interrupt occurs */ @@ -128,7 +131,6 @@ * @xfer_done: Transfer complete status * @p_send_buf: Pointer to transmit buffer * @p_recv_buf: Pointer to receive buffer - * @suspended: Flag holding the device's PM status * @send_count: Number of bytes still expected to send * @recv_count: Number of bytes still expected to receive * @curr_recv_count: Number of bytes to be received in current transfer @@ -141,6 +143,7 @@ * @quirks: flag for broken hold bit usage in r1p10 */ struct cdns_i2c { + struct device *dev; void __iomem *membase; struct i2c_adapter adap; struct i2c_msg *p_msg; @@ -148,7 +151,6 @@ struct cdns_i2c { struct completion xfer_done; unsigned char *p_send_buf; unsigned char *p_recv_buf; - u8 suspended; unsigned int send_count; unsigned int recv_count; unsigned int curr_recv_count; @@ -569,9 +571,14 @@ static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, struct cdns_i2c *id = adap->algo_data; bool hold_quirk; + ret = pm_runtime_get_sync(id->dev); + if (ret < 0) + return ret; /* Check if the bus is free */ - if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) - return -EAGAIN; + if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) { + ret = -EAGAIN; + goto out; + } hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT); /* @@ -590,7 +597,8 @@ static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, if (msgs[count].flags & I2C_M_RD) { dev_warn(adap->dev.parent, "Can't do repeated start after a receive message\n"); - return -EOPNOTSUPP; + ret = -EOPNOTSUPP; + goto out; } } id->bus_hold_flag = 1; @@ -608,20 +616,26 @@ static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, ret = cdns_i2c_process_msg(id, msgs, adap); if (ret) - return ret; + goto out; /* Report the other error interrupts to application */ if (id->err_status) { cdns_i2c_master_reset(adap); - if (id->err_status & CDNS_I2C_IXR_NACK) - return -ENXIO; - - return -EIO; + if (id->err_status & CDNS_I2C_IXR_NACK) { + ret = -ENXIO; + goto out; + } + ret = -EIO; + goto out; } } - return num; + ret = num; +out: + pm_runtime_mark_last_busy(id->dev); + pm_runtime_put_autosuspend(id->dev); + return ret; } /** @@ -760,7 +774,7 @@ static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long struct clk_notifier_data *ndata = data; struct cdns_i2c *id = to_cdns_i2c(nb); - if (id->suspended) + if (pm_runtime_suspended(id->dev)) return NOTIFY_OK; switch (event) { @@ -808,14 +822,12 @@ static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long * * Return: 0 always */ -static int __maybe_unused cdns_i2c_suspend(struct device *_dev) +static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) { - struct platform_device *pdev = container_of(_dev, - struct platform_device, dev); + struct platform_device *pdev = to_platform_device(dev); struct cdns_i2c *xi2c = platform_get_drvdata(pdev); clk_disable(xi2c->clk); - xi2c->suspended = 1; return 0; } @@ -828,26 +840,25 @@ static int __maybe_unused cdns_i2c_suspend(struct device *_dev) * * Return: 0 on success and error value on error */ -static int __maybe_unused cdns_i2c_resume(struct device *_dev) +static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) { - struct platform_device *pdev = container_of(_dev, - struct platform_device, dev); + struct platform_device *pdev = to_platform_device(dev); struct cdns_i2c *xi2c = platform_get_drvdata(pdev); int ret; ret = clk_enable(xi2c->clk); if (ret) { - dev_err(_dev, "Cannot enable clock.\n"); + dev_err(dev, "Cannot enable clock.\n"); return ret; } - xi2c->suspended = 0; - return 0; } -static SIMPLE_DEV_PM_OPS(cdns_i2c_dev_pm_ops, cdns_i2c_suspend, - cdns_i2c_resume); +static const struct dev_pm_ops cdns_i2c_dev_pm_ops = { + SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend, + cdns_i2c_runtime_resume, NULL) +}; static const struct cdns_platform_data r1p10_i2c_def = { .quirks = CDNS_I2C_BROKEN_HOLD_BIT, @@ -881,6 +892,7 @@ static int cdns_i2c_probe(struct platform_device *pdev) if (!id) return -ENOMEM; + id->dev = &pdev->dev; platform_set_drvdata(pdev, id); match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node); @@ -913,10 +925,14 @@ static int cdns_i2c_probe(struct platform_device *pdev) return PTR_ERR(id->clk); } ret = clk_prepare_enable(id->clk); - if (ret) { + if (ret) dev_err(&pdev->dev, "Unable to enable clock.\n"); - return ret; - } + + pm_runtime_enable(id->dev); + pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT); + pm_runtime_use_autosuspend(id->dev); + pm_runtime_set_active(id->dev); +</ |