diff options
-rw-r--r-- | drivers/scsi/qla2xxx/qla_dbg.h | 444 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_def.h | 652 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_fw.h | 760 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_inline.h | 2 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_mr.h | 8 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_nvme.h | 64 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_nx.h | 36 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_target.h | 232 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_tmpl.h | 2 |
9 files changed, 1100 insertions, 1100 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.h b/drivers/scsi/qla2xxx/qla_dbg.h index b106b6808d34..54ed020e6f75 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.h +++ b/drivers/scsi/qla2xxx/qla_dbg.h @@ -12,205 +12,205 @@ */ struct qla2300_fw_dump { - uint16_t hccr; - uint16_t pbiu_reg[8]; - uint16_t risc_host_reg[8]; - uint16_t mailbox_reg[32]; - uint16_t resp_dma_reg[32]; - uint16_t dma_reg[48]; - uint16_t risc_hdw_reg[16]; - uint16_t risc_gp0_reg[16]; - uint16_t risc_gp1_reg[16]; - uint16_t risc_gp2_reg[16]; - uint16_t risc_gp3_reg[16]; - uint16_t risc_gp4_reg[16]; - uint16_t risc_gp5_reg[16]; - uint16_t risc_gp6_reg[16]; - uint16_t risc_gp7_reg[16]; - uint16_t frame_buf_hdw_reg[64]; - uint16_t fpm_b0_reg[64]; - uint16_t fpm_b1_reg[64]; - uint16_t risc_ram[0xf800]; - uint16_t stack_ram[0x1000]; - uint16_t data_ram[1]; + __be16 hccr; + __be16 pbiu_reg[8]; + __be16 risc_host_reg[8]; + __be16 mailbox_reg[32]; + __be16 resp_dma_reg[32]; + __be16 dma_reg[48]; + __be16 risc_hdw_reg[16]; + __be16 risc_gp0_reg[16]; + __be16 risc_gp1_reg[16]; + __be16 risc_gp2_reg[16]; + __be16 risc_gp3_reg[16]; + __be16 risc_gp4_reg[16]; + __be16 risc_gp5_reg[16]; + __be16 risc_gp6_reg[16]; + __be16 risc_gp7_reg[16]; + __be16 frame_buf_hdw_reg[64]; + __be16 fpm_b0_reg[64]; + __be16 fpm_b1_reg[64]; + __be16 risc_ram[0xf800]; + __be16 stack_ram[0x1000]; + __be16 data_ram[1]; }; struct qla2100_fw_dump { - uint16_t hccr; - uint16_t pbiu_reg[8]; - uint16_t mailbox_reg[32]; - uint16_t dma_reg[48]; - uint16_t risc_hdw_reg[16]; - uint16_t risc_gp0_reg[16]; - uint16_t risc_gp1_reg[16]; - uint16_t risc_gp2_reg[16]; - uint16_t risc_gp3_reg[16]; - uint16_t risc_gp4_reg[16]; - uint16_t risc_gp5_reg[16]; - uint16_t risc_gp6_reg[16]; - uint16_t risc_gp7_reg[16]; - uint16_t frame_buf_hdw_reg[16]; - uint16_t fpm_b0_reg[64]; - uint16_t fpm_b1_reg[64]; - uint16_t risc_ram[0xf000]; + __be16 hccr; + __be16 pbiu_reg[8]; + __be16 mailbox_reg[32]; + __be16 dma_reg[48]; + __be16 risc_hdw_reg[16]; + __be16 risc_gp0_reg[16]; + __be16 risc_gp1_reg[16]; + __be16 risc_gp2_reg[16]; + __be16 risc_gp3_reg[16]; + __be16 risc_gp4_reg[16]; + __be16 risc_gp5_reg[16]; + __be16 risc_gp6_reg[16]; + __be16 risc_gp7_reg[16]; + __be16 frame_buf_hdw_reg[16]; + __be16 fpm_b0_reg[64]; + __be16 fpm_b1_reg[64]; + __be16 risc_ram[0xf000]; }; struct qla24xx_fw_dump { - uint32_t host_status; - uint32_t host_reg[32]; - uint32_t shadow_reg[7]; - uint16_t mailbox_reg[32]; - uint32_t xseq_gp_reg[128]; - uint32_t xseq_0_reg[16]; - uint32_t xseq_1_reg[16]; - uint32_t rseq_gp_reg[128]; - uint32_t rseq_0_reg[16]; - uint32_t rseq_1_reg[16]; - uint32_t rseq_2_reg[16]; - uint32_t cmd_dma_reg[16]; - uint32_t req0_dma_reg[15]; - uint32_t resp0_dma_reg[15]; - uint32_t req1_dma_reg[15]; - uint32_t xmt0_dma_reg[32]; - uint32_t xmt1_dma_reg[32]; - uint32_t xmt2_dma_reg[32]; - uint32_t xmt3_dma_reg[32]; - uint32_t xmt4_dma_reg[32]; - uint32_t xmt_data_dma_reg[16]; - uint32_t rcvt0_data_dma_reg[32]; - uint32_t rcvt1_data_dma_reg[32]; - uint32_t risc_gp_reg[128]; - uint32_t lmc_reg[112]; - uint32_t fpm_hdw_reg[192]; - uint32_t fb_hdw_reg[176]; - uint32_t code_ram[0x2000]; - uint32_t ext_mem[1]; + __be32 host_status; + __be32 host_reg[32]; + __be32 shadow_reg[7]; + __be16 mailbox_reg[32]; + __be32 xseq_gp_reg[128]; + __be32 xseq_0_reg[16]; + __be32 xseq_1_reg[16]; + __be32 rseq_gp_reg[128]; + __be32 rseq_0_reg[16]; + __be32 rseq_1_reg[16]; + __be32 rseq_2_reg[16]; + __be32 cmd_dma_reg[16]; + __be32 req0_dma_reg[15]; + __be32 resp0_dma_reg[15]; + __be32 req1_dma_reg[15]; + __be32 xmt0_dma_reg[32]; + __be32 xmt1_dma_reg[32]; + __be32 xmt2_dma_reg[32]; + __be32 xmt3_dma_reg[32]; + __be32 xmt4_dma_reg[32]; + __be32 xmt_data_dma_reg[16]; + __be32 rcvt0_data_dma_reg[32]; + __be32 rcvt1_data_dma_reg[32]; + __be32 risc_gp_reg[128]; + __be32 lmc_reg[112]; + __be32 fpm_hdw_reg[192]; + __be32 fb_hdw_reg[176]; + __be32 code_ram[0x2000]; + __be32 ext_mem[1]; }; struct qla25xx_fw_dump { - uint32_t host_status; - uint32_t host_risc_reg[32]; - uint32_t pcie_regs[4]; - uint32_t host_reg[32]; - uint32_t shadow_reg[11]; - uint32_t risc_io_reg; - uint16_t mailbox_reg[32]; - uint32_t xseq_gp_reg[128]; - uint32_t xseq_0_reg[48]; - uint32_t xseq_1_reg[16]; - uint32_t rseq_gp_reg[128]; - uint32_t rseq_0_reg[32]; - uint32_t rseq_1_reg[16]; - uint32_t rseq_2_reg[16]; - uint32_t aseq_gp_reg[128]; - uint32_t aseq_0_reg[32]; - uint32_t aseq_1_reg[16]; - uint32_t aseq_2_reg[16]; - uint32_t cmd_dma_reg[16]; - uint32_t req0_dma_reg[15]; - uint32_t resp0_dma_reg[15]; - uint32_t req1_dma_reg[15]; - uint32_t xmt0_dma_reg[32]; - uint32_t xmt1_dma_reg[32]; - uint32_t xmt2_dma_reg[32]; - uint32_t xmt3_dma_reg[32]; - uint32_t xmt4_dma_reg[32]; - uint32_t xmt_data_dma_reg[16]; - uint32_t rcvt0_data_dma_reg[32]; - uint32_t rcvt1_data_dma_reg[32]; - uint32_t risc_gp_reg[128]; - uint32_t lmc_reg[128]; - uint32_t fpm_hdw_reg[192]; - uint32_t fb_hdw_reg[192]; - uint32_t code_ram[0x2000]; - uint32_t ext_mem[1]; + __be32 host_status; + __be32 host_risc_reg[32]; + __be32 pcie_regs[4]; + __be32 host_reg[32]; + __be32 shadow_reg[11]; + __be32 risc_io_reg; + __be16 mailbox_reg[32]; + __be32 xseq_gp_reg[128]; + __be32 xseq_0_reg[48]; + __be32 xseq_1_reg[16]; + __be32 rseq_gp_reg[128]; + __be32 rseq_0_reg[32]; + __be32 rseq_1_reg[16]; + __be32 rseq_2_reg[16]; + __be32 aseq_gp_reg[128]; + __be32 aseq_0_reg[32]; + __be32 aseq_1_reg[16]; + __be32 aseq_2_reg[16]; + __be32 cmd_dma_reg[16]; + __be32 req0_dma_reg[15]; + __be32 resp0_dma_reg[15]; + __be32 req1_dma_reg[15]; + __be32 xmt0_dma_reg[32]; + __be32 xmt1_dma_reg[32]; + __be32 xmt2_dma_reg[32]; + __be32 xmt3_dma_reg[32]; + __be32 xmt4_dma_reg[32]; + __be32 xmt_data_dma_reg[16]; + __be32 rcvt0_data_dma_reg[32]; + __be32 rcvt1_data_dma_reg[32]; + __be32 risc_gp_reg[128]; + __be32 lmc_reg[128]; + __be32 fpm_hdw_reg[192]; + __be32 fb_hdw_reg[192]; + __be32 code_ram[0x2000]; + __be32 ext_mem[1]; }; struct qla81xx_fw_dump { - uint32_t host_status; - uint32_t host_risc_reg[32]; - uint32_t pcie_regs[4]; - uint32_t host_reg[32]; - uint32_t shadow_reg[11]; - uint32_t risc_io_reg; - uint16_t mailbox_reg[32]; - uint32_t xseq_gp_reg[128]; - uint32_t xseq_0_reg[48]; - uint32_t xseq_1_reg[16]; - uint32_t rseq_gp_reg[128]; - uint32_t rseq_0_reg[32]; - uint32_t rseq_1_reg[16]; - uint32_t rseq_2_reg[16]; - uint32_t aseq_gp_reg[128]; - uint32_t aseq_0_reg[32]; - uint32_t aseq_1_reg[16]; - uint32_t aseq_2_reg[16]; - uint32_t cmd_dma_reg[16]; - uint32_t req0_dma_reg[15]; - uint32_t resp0_dma_reg[15]; - uint32_t req1_dma_reg[15]; - uint32_t xmt0_dma_reg[32]; - uint32_t xmt1_dma_reg[32]; - uint32_t xmt2_dma_reg[32]; - uint32_t xmt3_dma_reg[32]; - uint32_t xmt4_dma_reg[32]; - uint32_t xmt_data_dma_reg[16]; - uint32_t rcvt0_data_dma_reg[32]; - uint32_t rcvt1_data_dma_reg[32]; - uint32_t risc_gp_reg[128]; - uint32_t lmc_reg[128]; - uint32_t fpm_hdw_reg[224]; - uint32_t fb_hdw_reg[208]; - uint32_t code_ram[0x2000]; - uint32_t ext_mem[1]; + __be32 host_status; + __be32 host_risc_reg[32]; + __be32 pcie_regs[4]; + __be32 host_reg[32]; + __be32 shadow_reg[11]; + __be32 risc_io_reg; + __be16 mailbox_reg[32]; + __be32 xseq_gp_reg[128]; + __be32 xseq_0_reg[48]; + __be32 xseq_1_reg[16]; + __be32 rseq_gp_reg[128]; + __be32 rseq_0_reg[32]; + __be32 rseq_1_reg[16]; + __be32 rseq_2_reg[16]; + __be32 aseq_gp_reg[128]; + __be32 aseq_0_reg[32]; + __be32 aseq_1_reg[16]; + __be32 aseq_2_reg[16]; + __be32 cmd_dma_reg[16]; + __be32 req0_dma_reg[15]; + __be32 resp0_dma_reg[15]; + __be32 req1_dma_reg[15]; + __be32 xmt0_dma_reg[32]; + __be32 xmt1_dma_reg[32]; + __be32 xmt2_dma_reg[32]; + __be32 xmt3_dma_reg[32]; + __be32 xmt4_dma_reg[32]; + __be32 xmt_data_dma_reg[16]; + __be32 rcvt0_data_dma_reg[32]; + __be32 rcvt1_data_dma_reg[32]; + __be32 risc_gp_reg[128]; + __be32 lmc_reg[128]; + __be32 fpm_hdw_reg[224]; + __be32 fb_hdw_reg[208]; + __be32 code_ram[0x2000]; + __be32 ext_mem[1]; }; struct qla83xx_fw_dump { - uint32_t host_status; - uint32_t host_risc_reg[48]; - uint32_t pcie_regs[4]; - uint32_t host_reg[32]; - uint32_t shadow_reg[11]; - uint32_t risc_io_reg; - uint16_t mailbox_reg[32]; - uint32_t xseq_gp_reg[256]; - uint32_t xseq_0_reg[48]; - uint32_t xseq_1_reg[16]; - uint32_t xseq_2_reg[16]; - uint32_t rseq_gp_reg[256]; - uint32_t rseq_0_reg[32]; - uint32_t rseq_1_reg[16]; - uint32_t rseq_2_reg[16]; - uint32_t rseq_3_reg[16]; - uint32_t aseq_gp_reg[256]; - uint32_t aseq_0_reg[32]; - uint32_t aseq_1_reg[16]; - uint32_t aseq_2_reg[16]; - uint32_t aseq_3_reg[16]; - uint32_t cmd_dma_reg[64]; - uint32_t req0_dma_reg[15]; - uint32_t resp0_dma_reg[15]; - uint32_t req1_dma_reg[15]; - uint32_t xmt0_dma_reg[32]; - uint32_t xmt1_dma_reg[32]; - uint32_t xmt2_dma_reg[32]; - uint32_t xmt3_dma_reg[32]; - uint32_t xmt4_dma_reg[32]; - uint32_t xmt_data_dma_reg[16]; - uint32_t rcvt0_data_dma_reg[32]; - uint32_t rcvt1_data_dma_reg[32]; - uint32_t risc_gp_reg[128]; - uint32_t lmc_reg[128]; - uint32_t fpm_hdw_reg[256]; - uint32_t rq0_array_reg[256]; - uint32_t rq1_array_reg[256]; - uint32_t rp0_array_reg[256]; - uint32_t rp1_array_reg[256]; - uint32_t queue_control_reg[16]; - uint32_t fb_hdw_reg[432]; - uint32_t at0_array_reg[128]; - uint32_t code_ram[0x2400]; - uint32_t ext_mem[1]; + __be32 host_status; + __be32 host_risc_reg[48]; + __be32 pcie_regs[4]; + __be32 host_reg[32]; + __be32 shadow_reg[11]; + __be32 risc_io_reg; + __be16 mailbox_reg[32]; + __be32 xseq_gp_reg[256]; + __be32 xseq_0_reg[48]; + __be32 xseq_1_reg[16]; + __be32 xseq_2_reg[16]; + __be32 rseq_gp_reg[256]; + __be32 rseq_0_reg[32]; + __be32 rseq_1_reg[16]; + __be32 rseq_2_reg[16]; + __be32 rseq_3_reg[16]; + __be32 aseq_gp_reg[256]; + __be32 aseq_0_reg[32]; + __be32 aseq_1_reg[16]; + __be32 aseq_2_reg[16]; + __be32 aseq_3_reg[16]; + __be32 cmd_dma_reg[64]; + __be32 req0_dma_reg[15]; + __be32 resp0_dma_reg[15]; + __be32 req1_dma_reg[15]; + __be32 xmt0_dma_reg[32]; + __be32 xmt1_dma_reg[32]; + __be32 xmt2_dma_reg[32]; + __be32 xmt3_dma_reg[32]; + __be32 xmt4_dma_reg[32]; + __be32 xmt_data_dma_reg[16]; + __be32 rcvt0_data_dma_reg[32]; + __be32 rcvt1_data_dma_reg[32]; + __be32 risc_gp_reg[128]; + __be32 lmc_reg[128]; + __be32 fpm_hdw_reg[256]; + __be32 rq0_array_reg[256]; + __be32 rq1_array_reg[256]; + __be32 rp0_array_reg[256]; + __be32 rp1_array_reg[256]; + __be32 queue_control_reg[16]; + __be32 fb_hdw_reg[432]; + __be32 at0_array_reg[128]; + __be32 code_ram[0x2400]; + __be32 ext_mem[1]; }; #define EFT_NUM_BUFFERS 4 @@ -223,45 +223,45 @@ struct qla83xx_fw_dump { #define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b)) struct qla2xxx_fce_chain { - uint32_t type; - uint32_t chain_size; + __be32 type; + __be32 chain_size; - uint32_t size; - uint32_t addr_l; - uint32_t addr_h; - uint32_t eregs[8]; + __be32 size; + __be32 addr_l; + __be32 addr_h; + __be32 eregs[8]; }; /* used by exchange off load and extended login offload */ struct qla2xxx_offld_chain { - uint32_t type; - uint32_t chain_size; + __be32 type; + __be32 chain_size; - uint32_t size; - uint32_t reserved; - u64 addr; + __be32 size; + __be32 reserved; + __be64 addr; }; struct qla2xxx_mq_chain { - uint32_t type; - uint32_t chain_size; + __be32 type; + __be32 chain_size; - uint32_t count; - uint32_t qregs[4 * QLA_MQ_SIZE]; + __be32 count; + __be32 qregs[4 * QLA_MQ_SIZE]; }; struct qla2xxx_mqueue_header { - uint32_t queue; + __be32 queue; #define TYPE_REQUEST_QUEUE 0x1 #define TYPE_RESPONSE_QUEUE 0x2 #define TYPE_ATIO_QUEUE 0x3 - uint32_t number; - uint32_t size; + __be32 number; + __be32 size; }; struct qla2xxx_mqueue_chain { - uint32_t type; - uint32_t chain_size; + __be32 type; + __be32 chain_size; }; #define DUMP_CHAIN_VARIANT 0x80000000 @@ -274,28 +274,28 @@ struct qla2xxx_mqueue_chain { struct qla2xxx_fw_dump { uint8_t signature[4]; - uint32_t version; + __be32 version; - uint32_t fw_major_version; - uint32_t fw_minor_version; - uint32_t fw_subminor_version; - uint32_t fw_attributes; + __be32 fw_major_version; + __be32 fw_minor_version; + __be32 fw_subminor_version; + __be32 fw_attributes; - uint32_t vendor; - uint32_t device; - uint32_t subsystem_vendor; - uint32_t subsystem_device; + __be32 vendor; + __be32 device; + __be32 subsystem_vendor; + __be32 subsystem_device; - uint32_t fixed_size; - uint32_t mem_size; - uint32_t req_q_size; - uint32_t rsp_q_size; + __be32 fixed_size; + __be32 mem_size; + __be32 req_q_size; + __be32 rsp_q_size; - uint32_t eft_size; - uint32_t eft_addr_l; - uint32_t eft_addr_h; + __be32 eft_size; + __be32 eft_addr_l; + __be32 eft_addr_h; - uint32_t header_size; + __be32 header_size; union { struct qla2100_fw_dump isp21; @@ -370,7 +370,7 @@ ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...); extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *, uint32_t, void **); -extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *, +extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, __be32 *, uint32_t, void **); extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *, struct qla_hw_data *); diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h index 3368fdf8b2dd..42dbf90d4651 100644 --- a/drivers/scsi/qla2xxx/qla_def.h +++ b/drivers/scsi/qla2xxx/qla_def.h @@ -504,7 +504,7 @@ struct srb_iocb { u32 rx_size; dma_addr_t els_plogi_pyld_dma; dma_addr_t els_resp_pyld_dma; - uint32_t fw_status[3]; + __le32 fw_status[3]; __le16 comp_status; __le16 len; } els_plogi; @@ -555,8 +555,8 @@ struct srb_iocb { #define MAX_IOCB_MB_REG 28 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) struct { - __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ - __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ + u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ + u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ void *out, *in; dma_addr_t out_dma, in_dma; struct completion comp; @@ -567,7 +567,7 @@ struct srb_iocb { } nack; struct { __le16 comp_status; - uint16_t rsp_pyld_len; + __le16 rsp_pyld_len; uint8_t aen_op; void *desc; @@ -698,23 +698,23 @@ struct msg_echo_lb { * ISP I/O Register Set structure definitions. */ struct device_reg_2xxx { - uint16_t flash_address; /* Flash BIOS address */ - uint16_t flash_data; /* Flash BIOS data */ - uint16_t unused_1[1]; /* Gap */ - uint16_t ctrl_status; /* Control/Status */ + __le16 flash_address; /* Flash BIOS address */ + __le16 flash_data; /* Flash BIOS data */ + __le16 unused_1[1]; /* Gap */ + __le16 ctrl_status; /* Control/Status */ #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ - uint16_t ictrl; /* Interrupt control */ + __le16 ictrl; /* Interrupt control */ #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ - uint16_t istatus; /* Interrupt status */ + __le16 istatus; /* Interrupt status */ #define ISR_RISC_INT BIT_3 /* RISC interrupt */ - uint16_t semaphore; /* Semaphore */ - uint16_t nvram; /* NVRAM register. */ + __le16 semaphore; /* Semaphore */ + __le16 nvram; /* NVRAM register. */ #define NVR_DESELECT 0 #define NVR_BUSY BIT_15 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ @@ -728,80 +728,80 @@ struct device_reg_2xxx { union { struct { - uint16_t mailbox0; - uint16_t mailbox1; - uint16_t mailbox2; - uint16_t mailbox3; - uint16_t mailbox4; - uint16_t mailbox5; - uint16_t mailbox6; - uint16_t mailbox7; - uint16_t unused_2[59]; /* Gap */ + __le16 mailbox0; + __le16 mailbox1; + __le16 mailbox2; + __le16 mailbox3; + __le16 mailbox4; + __le16 mailbox5; + __le16 mailbox6; + __le16 mailbox7; + __le16 unused_2[59]; /* Gap */ } __attribute__((packed)) isp2100; struct { /* Request Queue */ - uint16_t req_q_in; /* In-Pointer */ - uint16_t req_q_out; /* Out-Pointer */ + __le16 req_q_in; /* In-Pointer */ + __le16 req_q_out; /* Out-Pointer */ /* Response Queue */ - uint16_t rsp_q_in; /* In-Pointer */ - uint16_t rsp_q_out; /* Out-Pointer */ + __le16 rsp_q_in; /* In-Pointer */ + __le16 rsp_q_out; /* Out-Pointer */ /* RISC to Host Status */ - uint32_t host_status; + __le32 host_status; #define HSR_RISC_INT BIT_15 /* RISC interrupt */ #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ /* Host to Host Semaphore */ - uint16_t host_semaphore; - uint16_t unused_3[17]; /* Gap */ - uint16_t mailbox0; - uint16_t mailbox1; - uint16_t mailbox2; - uint16_t mailbox3; - uint16_t mailbox4; - uint16_t mailbox5; - uint16_t mailbox6; - uint16_t mailbox7; - uint16_t mailbox8; - uint16_t mailbox9; - uint16_t mailbox10; - uint16_t mailbox11; - uint16_t mailbox12; - uint16_t mailbox13; - uint16_t mailbox14; - uint16_t mailbox15; - uint16_t mailbox16; - uint16_t mailbox17; - uint16_t mailbox18; - uint16_t mailbox19; - uint16_t mailbox20; - uint16_t mailbox21; - uint16_t mailbox22; - uint16_t mailbox23; - uint16_t mailbox24; - uint16_t mailbox25; - uint16_t mailbox26; - uint16_t mailbox27; - uint16_t mailbox28; - uint16_t mailbox29; - uint16_t mailbox30; - uint16_t mailbox31; - uint16_t fb_cmd; - uint16_t unused_4[10]; /* Gap */ + __le16 host_semaphore; + __le16 unused_3[17]; /* Gap */ + __le16 mailbox0; + __le16 mailbox1; + __le16 mailbox2; + __le16 mailbox3; + __le16 mailbox4; + __le16 mailbox5; + __le16 mailbox6; + __le16 mailbox7; + __le16 mailbox8; + __le16 mailbox9; + __le16 mailbox10; + __le16 mailbox11; + __le16 mailbox12; + __le16 mailbox13; + __le16 mailbox14; + __le16 mailbox15; + __le16 mailbox16; + __le16 mailbox17; + __le16 mailbox18; + __le16 mailbox19; + __le16 mailbox20; + __le16 mailbox21; + __le16 mailbox22; + __le16 mailbox23; + __le16 mailbox24; + __le16 mailbox25; + __le16 mailbox26; + __le16 mailbox27; + __le16 mailbox28; + __le16 mailbox29; + __le16 mailbox30; + __le16 mailbox31; + __le16 fb_cmd; + __le16 unused_4[10]; /* Gap */ } __attribute__((packed)) isp2300; } u; - uint16_t fpm_diag_config; - uint16_t unused_5[0x4]; /* Gap */ - uint16_t risc_hw; - uint16_t unused_5_1; /* Gap */ - uint16_t pcr; /* Processor Control Register. */ - uint16_t unused_6[0x5]; /* Gap */ - uint16_t mctr; /* Memory Configuration and Timing. */ - uint16_t unused_7[0x3]; /* Gap */ - uint16_t fb_cmd_2100; /* Unused on 23XX */ - uint16_t unused_8[0x3]; /* Gap */ - uint16_t hccr; /* Host command & control register. */ + __le16 fpm_diag_config; + __le16 unused_5[0x4]; /* Gap */ + __le16 risc_hw; + __le16 unused_5_1; /* Gap */ + __le16 pcr; /* Processor Control Register. */ + __le16 unused_6[0x5]; /* Gap */ + __le16 mctr; /* Memory Configuration and Timing. */ + __le16 unused_7[0x3]; /* Gap */ + __le16 fb_cmd_2100; /* Unused on 23XX */ + __le16 unused_8[0x3]; /* Gap */ + __le16 hccr; /* Host command & control register. */ #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ /* HCCR commands */ @@ -814,9 +814,9 @@ struct device_reg_2xxx { #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ - uint16_t unused_9[5]; /* Gap */ - uint16_t gpiod; /* GPIO Data register. */ - uint16_t gpioe; /* GPIO Enable register. */ + __le16 unused_9[5]; /* Gap */ + __le16 gpiod; /* GPIO Data register. */ + __le16 gpioe; /* GPIO Enable register. */ #define GPIO_LED_MASK 0x00C0 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 @@ -828,95 +828,95 @@ struct device_reg_2xxx { union { struct { - uint16_t unused_10[8]; /* Gap */ - uint16_t mailbox8; - uint16_t mailbox9; - uint16_t mailbox10; - uint16_t mailbox11; - uint16_t mailbox12; - uint16_t mailbox13; - uint16_t mailbox14; - uint16_t mailbox15; - uint16_t mailbox16; - uint16_t mailbox17; - uint16_t mailbox18; - uint16_t mailbox19; - uint16_t mailbox20; - uint16_t mailbox21; - uint16_t mailbox22; - uint16_t mailbox23; /* Also probe reg. */ + __le16 unused_10[8]; /* Gap */ + __le16 mailbox8; + __le16 mailbox9; + __le16 mailbox10; + __le16 mailbox11; + __le16 mailbox12; + __le16 mailbox13; + __le16 mailbox14; + __le16 mailbox15; + __le16 mailbox16; + __le16 mailbox17; + __le16 mailbox18; + __le16 mailbox19; + __le16 mailbox20; + __le16 mailbox21; + __le16 mailbox22; + __le16 mailbox23; /* Also probe reg. */ } __attribute__((packed)) isp2200; } u_end; }; struct device_reg_25xxmq { - uint32_t req_q_in; - uint32_t req_q_out; - uint32_t rsp_q_in; - uint32_t rsp_q_out; - uint32_t atio_q_in; - uint32_t atio_q_out; + __le32 req_q_in; + __le32 req_q_out; + __le32 rsp_q_in; + __le32 rsp_q_out; + __le32 atio_q_in; + __le32 atio_q_out; }; struct device_reg_fx00 { - uint32_t mailbox0; /* 00 */ - uint32_t mailbox1; /* 04 */ - uint32_t mailbox2; /* 08 */ - uint32_t mailbox3; /* 0C */ - uint32_t mailbox4; /* 10 */ - uint32_t mailbox5; /* 14 */ - uint32_t mailbox6; /* 18 */ - uint32_t mailbox7; /* 1C */ - uint32_t mailbox8; /* 20 */ - uint32_t mailbox9; /* 24 */ - uint32_t mailbox10; /* 28 */ - uint32_t mailbox11; - uint32_t mailbox12; - uint32_t mailbox13; - uint32_t mailbox14; - uint32_t mailbox15; - uint32_t mailbox16; - uint32_t mailbox17; - uint32_t mailbox18; - uint32_t mailbox19; - uint32_t mailbox20; - uint32_t mailbox21; - uint32_t mailbox22; - uint32_t mailbox23; - uint32_t mailbox24; - uint32_t mailbox25; - uint32_t mailbox26; - uint32_t mailbox27; - uint32_t mailbox28; - uint32_t mailbox29; - uint32_t mailbox30; - uint32_t mailbox31; - uint32_t aenmailbox0; - uint32_t aenmailbox1; - uint32_t aenmailbox2; - uint32_t aenmailbox3; - uint32_t aenmailbox4; - uint32_t aenmailbox5; - uint32_t aenmailbox6; - uint32_t aenmailbox7; + __le32 mailbox0; /* 00 */ + __le32 mailbox1; /* 04 */ + __le32 mailbox2; /* 08 */ + __le32 mailbox3; /* 0C */ + __le32 mailbox4; /* 10 */ + __le32 mailbox5; /* 14 */ + __le32 mailbox6; /* 18 */ + __le32 mailbox7; /* 1C */ + __le32 mailbox8; /* 20 */ + __le32 mailbox9; /* 24 */ + __le32 mailbox10; /* 28 */ + __le32 mailbox11; + __le32 mailbox12; + __le32 mailbox13; + __le32 mailbox14; + __le32 mailbox15; + __le32 mailbox16; + __le32 mailbox17; + __le32 mailbox18; + __le32 mailbox19; + __le32 mailbox20; + __le32 mailbox21; + __le32 mailbox22; + __le32 mailbox23; + __le32 mailbox24; + __le32 mailbox25; + __le32 mailbox26; + __le32 mailbox27; + __le32 mailbox28; + __le32 mailbox29; + __le32 mailbox30; + __le32 mailbox31; + __le32 aenmailbox0; + __le32 aenmailbox1; + __le32 aenmailbox2; + __le32 aenmailbox3; + __le32 aenmailbox4; + __le32 aenmailbox5; + __le32 aenmailbox6; + __le32 aenmailbox7; /* Request Queue. */ - uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ - uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ + __le32 req_q_in; /* A0 - Request Queue In-Pointer */ + __le32 req_q_out; /* A4 - Request Queue Out-Pointer */ /* Response Queue. */ - uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ - uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ + __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */ + __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */ /* Init values shadowed on FW Up Event */ - uint32_t initval0; /* B0 */ - uint32_t initval1; /* B4 */ - uint32_t initval2; /* B8 */ - uint32_t initval3; /* BC */ - uint32_t initval4; /* C0 */ - uint32_t initval5; /* C4 */ - uint32_t initval6; /* C8 */ - uint32_t initval7; /* CC */ - uint32_t fwheartbeat; /* D0 */ - uint32_t pseudoaen; /* D4 */ + __le32 initval0; /* B0 */ + __le32 initval1; /* B4 */ + __le32 initval2; /* B8 */ + __le32 initval3; /* BC */ + __le32 initval4; /* C0 */ + __le32 initval5; /* C4 */ + __le32 initval6; /* C8 */ + __le32 initval7; /* CC */ + __le32 fwheartbeat; /* D0 */ + __le32 pseudoaen; /* D4 */ }; @@ -1351,7 +1351,7 @@ typedef struct { uint8_t port_id[4]; uint8_t node_name[WWN_SIZE]; uint8_t port_name[WWN_SIZE]; - uint16_t execution_throttle; + __le16 execution_throttle; uint16_t execution_count; uint8_t reset_count; uint8_t reserved_2; @@ -1437,9 +1437,9 @@ typedef struct { */ uint8_t firmware_options[2]; - uint16_t frame_payload_size; - uint16_t max_iocb_allocation; - uint16_t execution_throttle; + __le16 frame_payload_size; + __le16 max_iocb_allocation; + __le16 execution_throttle; uint8_t retry_count; uint8_t retry_delay; /* unused */ uint8_t port_name[WWN_SIZE]; /* Big endian. */ @@ -1448,17 +1448,17 @@ typedef struct { uint8_t login_timeout; uint8_t node_name[WWN_SIZE]; /* Big endian. */ - uint16_t request_q_outpointer; - uint16_t response_q_inpointer; - uint16_t request_q_length; - uint16_t response_q_length; - __le64 request_q_address __packed; - __le64 response_q_address __packed; + __le16 request_q_outpointer; + __le16 response_q_inpointer; + __le16 request_q_length; + __le16 response_q_length; + __le64 request_q_address __packed; + __le64 response_q_address __packed; - uint16_t lun_enables; + __le16 lun_enables; uint8_t command_resource_count; uint8_t immediate_notify_resource_count; - uint16_t timeout; + __le16 timeout; uint8_t reserved_2[2]; /* @@ -1606,8 +1606,8 @@ typedef struct { uint8_t firmware_options[2]; uint16_t frame_payload_size; - uint16_t max_iocb_allocation; - uint16_t execution_throttle; + __le16 max_iocb_allocation; + __le16 execution_throttle; uint8_t retry_count; uint8_t retry_delay; /* unused */ uint8_t port_name[WWN_SIZE]; /* Big endian. */ @@ -1731,7 +1731,7 @@ typedef struct { uint8_t reset_delay; uint8_t port_down_retry_count; uint8_t boot_id_number; - uint16_t max_luns_per_target; + __le16 max_luns_per_target; uint8_t fcode_boot_port_name[WWN_SIZE]; uint8_t alternate_port_name[WWN_SIZE]; uint8_t alternate_node_name[WWN_SIZE]; @@ -1837,7 +1837,7 @@ struct atio { }; typedef union { - uint16_t extended; + __le16 extended; struct { uint8_t reserved; uint8_t standard; @@ -1863,18 +1863,18 @@ typedef struct { uint8_t entry_status; /* Entry Status. */ uint32_t handle; /* System handle. */ target_id_t target; /* SCSI ID */ - uint16_t lun; /* SCSI LUN */ - uint16_t control_flags; /* Control flags. */ + __le16 lun; /* SCSI LUN */ + __le16 control_flags; /* Control flags. */ #define CF_WRITE BIT_6 #define CF_READ BIT_5 #define CF_SIMPLE_TAG BIT_3 #define CF_ORDERED_TAG BIT_2 #define CF_HEAD_TAG BIT_1 uint16_t reserved_1; - uint16_t timeout; /* Command timeout. */ - uint16_t dseg_count; /* Data segment count. */ + __le16 timeout; /* Command timeout. */ + __le16 dseg_count; /* Data segment count. */ uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ - uint32_t byte_count; /* Total byte count. */ + __le32 byte_count; /* Total byte count. */ union { struct dsd32 dsd32[3]; struct dsd64 dsd64[2]; @@ -1892,11 +1892,11 @@ typedef struct { uint8_t entry_status; /* Entry Status. */ uint32_t handle; /* System handle. */ target_id_t target; /* SCSI ID */ - uint16_t lun; /* SCSI LUN */ - uint16_t control_flags; /* Control flags. */ + __le16 lun; /* SCSI LUN */ + __le16 control_flags; /* Control flags. */ uint16_t reserved_1; - uint16_t timeout; /* Command timeout. */ - uint16_t dseg_count; /* Data segment count. */ + __le16 timeout; /* Command timeout. */ + __le16 dseg_count; /* Data segment count. */ uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ uint32_t byte_count; /* Total byte count. */ struct dsd64 dsd[2]; @@ -1958,7 +1958,7 @@ struct crc_context { __le16 guard_seed; /* Initial Guard Seed */ __le16 prot_opts; /* Requested Data Protection Mode */ __le16 blk_size; /* Data size in bytes */ - uint16_t runt_blk_guard; /* Guard value for runt block (tape + __le16 runt_blk_guard; /* Guard value for runt block (tape * only) */ __le32 byte_count; /* Total byte count/ total data * transfer count */ @@ -2011,13 +2011,13 @@ typedef struct { uint8_t sys_define; /* System defined. */ uint8_t entry_status; /* Entry Status. */ uint32_t handle; /* System handle. */ - uint16_t scsi_status; /* SCSI status. */ - uint16_t comp_status; /* Completion status. */ - uint16_t state_flags; /* State flags. */ - uint16_t status_flags; /* Status flags. */ - uint16_t rsp_info_len; /* Response Info Length. */ - uint16_t req_sense_length; /* Request sense data length. */ - uint32_t residual_length; /* Residual transfer length. */ + __le16 scsi_status; /* SCSI status. */ + __le16 comp_status; /* Completion status. */ + __le16 state_flags; /* State flags. */ + __le16 status_flags; /* Status flags. */ + __le16 rsp_info_len; /* Response Info Length. */ + __le16 req_sense_length; /* Request sense data length. */ + __le32 residual_length; /* Residual transfer length. */ uint8_t rsp_info[8]; /* FCP response information. */ uint8_t req_sense_data[32]; /* Request sense data. */ } sts_entry_t; @@ -2149,8 +2149,8 @@ typedef struct { /* clear port changed, */ /* use sequence number. */ uint8_t reserved_1; - uint16_t sequence_number; /* Sequence number of event */ - uint16_t lun; /* SCSI LUN */ + __le16 sequence_number; /* Sequence number of event */ + __le16 lun; /* SCSI LUN */ uint8_t reserved_2[48]; } mrk_entry_t; @@ -2165,19 +2165,19 @@ typedef struct { uint8_t entry_status; /* Entry Status. */ uint32_t handle1; /* System handle. */ target_id_t loop_id; - uint16_t status; - uint16_t control_flags; /* Control flags. */ + __le16 status; + __le16 control_flags; /* Control flags. */ uint16_t reserved2; - uint16_t timeout; - uint16_t cmd_dsd_count; - uint16_t total_dsd_count; + __le16 timeout; + __le16 cmd_dsd_count; + __le16 total_dsd_count; uint8_t type; uint8_t r_ctl; - uint16_t rx_id; + __le16 rx_id; uint16_t reserved3; uint32_t handle2; - uint32_t rsp_bytecount; - uint32_t req_bytecount; + __le32 rsp_bytecount; + __le32 req_bytecount; struct dsd64 req_dsd; struct dsd64 rsp_dsd; } ms_iocb_entry_t; @@ -2205,20 +2205,20 @@ struct mbx_entry { uint32_t handle; target_id_t loop_id; - uint16_t status; - uint16_t state_flags; - uint16_t status_flags; + __le16 status; + __le16 state_flags; + __le16 status_flags; uint32_t sys_define2[2]; - uint16_t mb0; - uint16_t mb1; - uint16_t mb2; - uint16_t mb3; - uint16_t mb6; - uint16_t mb7; - uint16_t mb9; - uint16_t mb10; + __le16 mb0; + __le16 mb1; + __le16 mb2; + __le16 mb3; + __le16 mb6; + __le16 mb7; + __le16 mb9; + __le16 mb10; uint32_t reserved_2[2]; uint8_t node_name[WWN_SIZE]; uint8_t port_name[WWN_SIZE]; @@ -2240,52 +2240,52 @@ struct imm_ntfy_from_isp { uint8_t entry_status; /* Entry Status. */ union { struct { - uint32_t sys_define_2; /* System defined. */ + __le32 sys_define_2; /* System defined. */ target_id_t target; - uint16_t lun; + __le16 lun; uint8_t target_id; uint8_t reserved_1; - uint16_t status_modifier; - uint16_t status; - uint16_t task_flags; - uint16_t seq_id; - uint16_t srr_rx_id; - uint32_t srr_rel_offs; - uint16_t srr_ui; + __le16 status_modifier; + __le16 status; + __le16 task_flags; + __le16 seq_id; + __le16 srr_rx_id; + __le32 srr_rel_offs; + __le16 srr_ui; #define SRR_IU_DATA_IN 0x1 #define SRR_IU_DATA_OUT 0x5 #define SRR_IU_STATUS 0x7 - uint16_t srr_ox_id; + __le16 srr_ox_id; uint8_t reserved_2[28]; |