diff options
| author | Pi-Hsun Shih <pihsun@chromium.org> | 2019-03-06 17:09:02 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-03-19 12:51:13 +0000 |
| commit | ed1666f6867059e1ed4e2e565a1c87c5580f1b38 (patch) | |
| tree | a01b5bb8ebb23c2aac1190888986a3b74e96b859 /sound/soc/mediatek/mt8173/mt8173-afe-pcm.c | |
| parent | 4e08d50d1fb6144df4b0b5c75a17edd344bf3d1b (diff) | |
ASoC: mediatek: Fix UBSAN warning.
In sound/soc/mediatek/common/mtk-afe-fe-dai.c, when xxx_reg is -1, it's
a no-op to call mtk_regmap_update_bits, but since both xxx_reg and
xxx_shift are set to -1, the (1 << xxx_shift) in the argument would
trigger a UBSAN warning.
Fix the warning by setting those xxx_shift to 0 instead.
Note that since the code explicitly checks .mono_shift >= 0 and
.fs_shift >= 0 before using them in '<<' operator, those two members are
not set to 0.
Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/mediatek/mt8173/mt8173-afe-pcm.c')
| -rw-r--r-- | sound/soc/mediatek/mt8173/mt8173-afe-pcm.c | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c b/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c index 166aed28330d..0382896c162e 100644 --- a/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c +++ b/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c @@ -714,13 +714,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = { .mono_reg = AFE_DAC_CON1, .mono_shift = 21, .hd_reg = -1, - .hd_shift = -1, .enable_reg = AFE_DAC_CON0, .enable_shift = 1, .msb_reg = AFE_MEMIF_MSB, .msb_shift = 0, .agent_disable_reg = -1, - .agent_disable_shift = -1, }, { .name = "DL2", .id = MT8173_AFE_MEMIF_DL2, @@ -732,13 +730,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = { .mono_reg = AFE_DAC_CON1, .mono_shift = 22, .hd_reg = -1, - .hd_shift = -1, .enable_reg = AFE_DAC_CON0, .enable_shift = 2, .msb_reg = AFE_MEMIF_MSB, .msb_shift = 1, .agent_disable_reg = -1, - .agent_disable_shift = -1, }, { .name = "VUL", .id = MT8173_AFE_MEMIF_VUL, @@ -750,13 +746,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = { .mono_reg = AFE_DAC_CON1, .mono_shift = 27, .hd_reg = -1, - .hd_shift = -1, .enable_reg = AFE_DAC_CON0, .enable_shift = 3, .msb_reg = AFE_MEMIF_MSB, .msb_shift = 6, .agent_disable_reg = -1, - .agent_disable_shift = -1, }, { .name = "DAI", .id = MT8173_AFE_MEMIF_DAI, @@ -768,13 +762,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = { .mono_reg = -1, .mono_shift = -1, .hd_reg = -1, - .hd_shift = -1, .enable_reg = AFE_DAC_CON0, .enable_shift = 4, .msb_reg = AFE_MEMIF_MSB, .msb_shift = 5, .agent_disable_reg = -1, - .agent_disable_shift = -1, }, { .name = "AWB", .id = MT8173_AFE_MEMIF_AWB, @@ -786,13 +778,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = { .mono_reg = AFE_DAC_CON1, .mono_shift = 24, .hd_reg = -1, - .hd_shift = -1, .enable_reg = AFE_DAC_CON0, .enable_shift = 6, .msb_reg = AFE_MEMIF_MSB, .msb_shift = 3, .agent_disable_reg = -1, - .agent_disable_shift = -1, }, { .name = "MOD_DAI", .id = MT8173_AFE_MEMIF_MOD_DAI, @@ -804,13 +794,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = { .mono_reg = AFE_DAC_CON1, .mono_shift = 30, .hd_reg = -1, - .hd_shift = -1, .enable_reg = AFE_DAC_CON0, .enable_shift = 7, .msb_reg = AFE_MEMIF_MSB, .msb_shift = 4, .agent_disable_reg = -1, - .agent_disable_shift = -1, }, { .name = "HDMI", .id = MT8173_AFE_MEMIF_HDMI, @@ -822,13 +810,10 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = { .mono_reg = -1, .mono_shift = -1, .hd_reg = -1, - .hd_shift = -1, .enable_reg = -1, - .enable_shift = -1, .msb_reg = AFE_MEMIF_MSB, .msb_shift = 8, .agent_disable_reg = -1, - .agent_disable_shift = -1, }, }; @@ -914,7 +899,6 @@ static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = { .irq_en_reg = AFE_IRQ_MCU_CON, .irq_en_shift = 12, .irq_fs_reg = -1, - .irq_fs_shift = -1, .irq_fs_maskbit = -1, .irq_clr_reg = AFE_IRQ_CLR, .irq_clr_shift = 4, |