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| author | Stefan Chulski <stefanc@marvell.com> | 2020-12-23 20:35:21 +0200 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2020-12-28 14:29:06 -0800 |
| commit | 4f374d2c43a9e5e773f1dee56db63bd6b8a36276 (patch) | |
| tree | 4a1b106253c48b8f2b31719ff94fc64f46badd80 /net/ipv4/fib_frontend.c | |
| parent | bb2cc7d7143f00717d4d9346817fc332bcf8ad2f (diff) | |
net: mvpp2: fix pkt coalescing int-threshold configuration
The packet coalescing interrupt threshold has separated registers
for different aggregated/cpu (sw-thread). The required value should
be loaded for every thread but not only for 1 current cpu.
Fixes: 213f428f5056 ("net: mvpp2: add support for TX interrupts and RX queue distribution modes")
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Link: https://lore.kernel.org/r/1608748521-11033-1-git-send-email-stefanc@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'net/ipv4/fib_frontend.c')
0 files changed, 0 insertions, 0 deletions