diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-03-08 10:02:58 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-03-08 10:02:58 -0800 |
| commit | cf2e8c544cd3b33e9e403b7b72404c221bf888d1 (patch) | |
| tree | 21b46d362626562921df14d75ee106259b3fa936 /include | |
| parent | 04e0361848afbe86fbf8b80945568df4c5bf6f07 (diff) | |
| parent | d2d833e0bf2bad221a955626b942b38312630894 (diff) | |
Merge tag 'mfd-next-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"New Drivers:
- Add STMPE ADC Input driver
- Add STMicroelectronics STPMIC1 Parent driver
- Add STMicroelectronics STPMIC1 OnKey Misc driver
- Add STMicroelectronics STPMIC1 Watchdog driver
- Add Cirrus Logic Lochnagar Parent driver
- Add TQ-Systems TQMX86 Parent driver
New Device Support:
- Add support for ADC to STMPE
New (or moved) Functionality:
- Move Lightbar functionality to its own driver; cros_ec_lightbar
- Move VBC functionality to its own driver; cros_ec_vbc
- Move VBC functionality to its own driver; cros_ec_vbc
- Move DebugFS functionality to its own driver; cros_ec_debugfs
- Move SYSFS functionality to its own driver; cros_ec_sysfs
- Add support for input voltage options; tps65218
Fixes:
- Use devm_* managed resources; cros_ec
- Device Tree documentation; stmpe, aspeed-lpc, lochnagar
- Trivial Clean-ups; stmpe
- Rip out broken modular code; aat2870-core, adp5520, as3711,
db8500-prcmu, htc-i2cpld, max8925-core, rc5t583, sta2x11-mfd,
syscon, tps65090, tps65910, tps68470 tps80031, wm831x-spi,
wm831x-i2c, wm831x-core, wm8350-i2c, wm8350-core, wm8400-core
- Kconfig fixups; INTEL_SOC_PMIC
- Improve error path; sm501, sec-core
- Use struct_size() helper; sm501
- Constify; at91-usart
- Use pointers instead of copying data; at91-usart
- Deliver proper return value; cros_ec_dev
- Trivial formatting/whitespace; sec-core"
* tag 'mfd-next-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (53 commits)
mfd: mxs-lradc: Mark expected switch fall-through
mfd: sec-core: Cleanup formatting to a consistent style
mfd: tqmx86: IO controller with I2C, Wachdog and GPIO
mfd: intel-lpss: Move linux/pm.h to the local header
mfd: cros_ec_dev: Return number of bytes read with CROS_EC_DEV_IOCRDMEM
mfd: tps68470: Drop unused MODULE_DEVICE_TABLE
mfd: at91-usart: No need to copy mfd_cell in probe
mfd: at91-usart: Constify at91_usart_spi_subdev and at91_usart_serial_subdev
mfd: lochnagar: Add support for the Cirrus Logic Lochnagar
mfd: lochnagar: Add initial binding documentation
dt-bindings: mfd: aspeed-lpc: Make parameter optional
mfd: sec-core: Return gracefully instead of BUG() if device cannot match
mfd: sm501: Use struct_size() in devm_kzalloc()
mfd: sm501: Fix potential NULL pointer dereference
mfd: Kconfig: Fix I2C_DESIGNWARE_PLATFORM dependencies
mfd: tps65218.c: Add input voltage options
mfd: wm8400-core: Make it explicitly non-modular
mfd: wm8350-core: Drop unused module infrastructure from non-modular code
mfd: wm8350-i2c: Make it explicitly non-modular
mfd: wm831x-core: Drop unused module infrastructure from non-modular code
...
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clk/lochnagar.h | 26 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/st,stpmic1.h | 50 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/lochnagar.h | 132 | ||||
| -rw-r--r-- | include/linux/mfd/cros_ec.h | 21 | ||||
| -rw-r--r-- | include/linux/mfd/lochnagar.h | 55 | ||||
| -rw-r--r-- | include/linux/mfd/lochnagar1_regs.h | 157 | ||||
| -rw-r--r-- | include/linux/mfd/lochnagar2_regs.h | 291 | ||||
| -rw-r--r-- | include/linux/mfd/stmpe.h | 21 | ||||
| -rw-r--r-- | include/linux/mfd/stpmic1.h | 212 | ||||
| -rw-r--r-- | include/linux/mfd/tps65218.h | 4 | ||||
| -rw-r--r-- | include/linux/mfd/wm831x/core.h | 1 | ||||
| -rw-r--r-- | include/linux/mfd/wm8350/core.h | 1 |
12 files changed, 948 insertions, 23 deletions
diff --git a/include/dt-bindings/clk/lochnagar.h b/include/dt-bindings/clk/lochnagar.h new file mode 100644 index 000000000000..8fa20551ff17 --- /dev/null +++ b/include/dt-bindings/clk/lochnagar.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree defines for Lochnagar clocking + * + * Copyright (c) 2017-2018 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + * + * Author: Charles Keepax <ckeepax@opensource.cirrus.com> + */ + +#ifndef DT_BINDINGS_CLK_LOCHNAGAR_H +#define DT_BINDINGS_CLK_LOCHNAGAR_H + +#define LOCHNAGAR_CDC_MCLK1 0 +#define LOCHNAGAR_CDC_MCLK2 1 +#define LOCHNAGAR_DSP_CLKIN 2 +#define LOCHNAGAR_GF_CLKOUT1 3 +#define LOCHNAGAR_GF_CLKOUT2 4 +#define LOCHNAGAR_PSIA1_MCLK 5 +#define LOCHNAGAR_PSIA2_MCLK 6 +#define LOCHNAGAR_SPDIF_MCLK 7 +#define LOCHNAGAR_ADAT_MCLK 8 +#define LOCHNAGAR_SOUNDCARD_MCLK 9 +#define LOCHNAGAR_SPDIF_CLKOUT 10 + +#endif diff --git a/include/dt-bindings/mfd/st,stpmic1.h b/include/dt-bindings/mfd/st,stpmic1.h new file mode 100644 index 000000000000..321cd08797d9 --- /dev/null +++ b/include/dt-bindings/mfd/st,stpmic1.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Philippe Peurichard <philippe.peurichard@st.com>, + * Pascal Paillet <p.paillet@st.com> for STMicroelectronics. + */ + +#ifndef __DT_BINDINGS_STPMIC1_H__ +#define __DT_BINDINGS_STPMIC1_H__ + +/* IRQ definitions */ +#define IT_PONKEY_F 0 +#define IT_PONKEY_R 1 +#define IT_WAKEUP_F 2 +#define IT_WAKEUP_R 3 +#define IT_VBUS_OTG_F 4 +#define IT_VBUS_OTG_R 5 +#define IT_SWOUT_F 6 +#define IT_SWOUT_R 7 + +#define IT_CURLIM_BUCK1 8 +#define IT_CURLIM_BUCK2 9 +#define IT_CURLIM_BUCK3 10 +#define IT_CURLIM_BUCK4 11 +#define IT_OCP_OTG 12 +#define IT_OCP_SWOUT 13 +#define IT_OCP_BOOST 14 +#define IT_OVP_BOOST 15 + +#define IT_CURLIM_LDO1 16 +#define IT_CURLIM_LDO2 17 +#define IT_CURLIM_LDO3 18 +#define IT_CURLIM_LDO4 19 +#define IT_CURLIM_LDO5 20 +#define IT_CURLIM_LDO6 21 +#define IT_SHORT_SWOTG 22 +#define IT_SHORT_SWOUT 23 + +#define IT_TWARN_F 24 +#define IT_TWARN_R 25 +#define IT_VINLOW_F 26 +#define IT_VINLOW_R 27 +#define IT_SWIN_F 30 +#define IT_SWIN_R 31 + +/* BUCK MODES definitions */ +#define STPMIC1_BUCK_MODE_NORMAL 0 +#define STPMIC1_BUCK_MODE_LP 2 + +#endif /* __DT_BINDINGS_STPMIC1_H__ */ diff --git a/include/dt-bindings/pinctrl/lochnagar.h b/include/dt-bindings/pinctrl/lochnagar.h new file mode 100644 index 000000000000..644760bf5725 --- /dev/null +++ b/include/dt-bindings/pinctrl/lochnagar.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree defines for Lochnagar pinctrl + * + * Copyright (c) 2018 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + * + * Author: Charles Keepax <ckeepax@opensource.cirrus.com> + */ + +#ifndef DT_BINDINGS_PINCTRL_LOCHNAGAR_H +#define DT_BINDINGS_PINCTRL_LOCHNAGAR_H + +#define LOCHNAGAR1_PIN_CDC_RESET 0 +#define LOCHNAGAR1_PIN_DSP_RESET 1 +#define LOCHNAGAR1_PIN_CDC_CIF1MODE 2 +#define LOCHNAGAR1_PIN_NUM_GPIOS 3 + +#define LOCHNAGAR2_PIN_CDC_RESET 0 +#define LOCHNAGAR2_PIN_DSP_RESET 1 +#define LOCHNAGAR2_PIN_CDC_CIF1MODE 2 +#define LOCHNAGAR2_PIN_CDC_LDOENA 3 +#define LOCHNAGAR2_PIN_SPDIF_HWMODE 4 +#define LOCHNAGAR2_PIN_SPDIF_RESET 5 +#define LOCHNAGAR2_PIN_FPGA_GPIO1 6 +#define LOCHNAGAR2_PIN_FPGA_GPIO2 7 +#define LOCHNAGAR2_PIN_FPGA_GPIO3 8 +#define LOCHNAGAR2_PIN_FPGA_GPIO4 9 +#define LOCHNAGAR2_PIN_FPGA_GPIO5 10 +#define LOCHNAGAR2_PIN_FPGA_GPIO6 11 +#define LOCHNAGAR2_PIN_CDC_GPIO1 12 +#define LOCHNAGAR2_PIN_CDC_GPIO2 13 +#define LOCHNAGAR2_PIN_CDC_GPIO3 14 +#define LOCHNAGAR2_PIN_CDC_GPIO4 15 +#define LOCHNAGAR2_PIN_CDC_GPIO5 16 +#define LOCHNAGAR2_PIN_CDC_GPIO6 17 +#define LOCHNAGAR2_PIN_CDC_GPIO7 18 +#define LOCHNAGAR2_PIN_CDC_GPIO8 19 +#define LOCHNAGAR2_PIN_DSP_GPIO1 20 +#define LOCHNAGAR2_PIN_DSP_GPIO2 21 +#define LOCHNAGAR2_PIN_DSP_GPIO3 22 +#define LOCHNAGAR2_PIN_DSP_GPIO4 23 +#define LOCHNAGAR2_PIN_DSP_GPIO5 24 +#define LOCHNAGAR2_PIN_DSP_GPIO6 25 +#define LOCHNAGAR2_PIN_GF_GPIO2 26 +#define LOCHNAGAR2_PIN_GF_GPIO3 27 +#define LOCHNAGAR2_PIN_GF_GPIO7 28 +#define LOCHNAGAR2_PIN_CDC_AIF1_BCLK 29 +#define LOCHNAGAR2_PIN_CDC_AIF1_RXDAT 30 +#define LOCHNAGAR2_PIN_CDC_AIF1_LRCLK 31 +#define LOCHNAGAR2_PIN_CDC_AIF1_TXDAT 32 +#define LOCHNAGAR2_PIN_CDC_AIF2_BCLK 33 +#define LOCHNAGAR2_PIN_CDC_AIF2_RXDAT 34 +#define LOCHNAGAR2_PIN_CDC_AIF2_LRCLK 35 +#define LOCHNAGAR2_PIN_CDC_AIF2_TXDAT 36 +#define LOCHNAGAR2_PIN_CDC_AIF3_BCLK 37 +#define LOCHNAGAR2_PIN_CDC_AIF3_RXDAT 38 +#define LOCHNAGAR2_PIN_CDC_AIF3_LRCLK 39 +#define LOCHNAGAR2_PIN_CDC_AIF3_TXDAT 40 +#define LOCHNAGAR2_PIN_DSP_AIF1_BCLK 41 +#define LOCHNAGAR2_PIN_DSP_AIF1_RXDAT 42 +#define LOCHNAGAR2_PIN_DSP_AIF1_LRCLK 43 +#define LOCHNAGAR2_PIN_DSP_AIF1_TXDAT 44 +#define LOCHNAGAR2_PIN_DSP_AIF2_BCLK 45 +#define LOCHNAGAR2_PIN_DSP_AIF2_RXDAT 46 +#define LOCHNAGAR2_PIN_DSP_AIF2_LRCLK 47 +#define LOCHNAGAR2_PIN_DSP_AIF2_TXDAT 48 +#define LOCHNAGAR2_PIN_PSIA1_BCLK 49 +#define LOCHNAGAR2_PIN_PSIA1_RXDAT 50 +#define LOCHNAGAR2_PIN_PSIA1_LRCLK 51 +#define LOCHNAGAR2_PIN_PSIA1_TXDAT 52 +#define LOCHNAGAR2_PIN_PSIA2_BCLK 53 +#define LOCHNAGAR2_PIN_PSIA2_RXDAT 54 +#define LOCHNAGAR2_PIN_PSIA2_LRCLK 55 +#define LOCHNAGAR2_PIN_PSIA2_TXDAT 56 +#define LOCHNAGAR2_PIN_GF_AIF3_BCLK 57 +#define LOCHNAGAR2_PIN_GF_AIF3_RXDAT 58 +#define LOCHNAGAR2_PIN_GF_AIF3_LRCLK 59 +#define LOCHNAGAR2_PIN_GF_AIF3_TXDAT 60 +#define LOCHNAGAR2_PIN_GF_AIF4_BCLK 61 +#define LOCHNAGAR2_PIN_GF_AIF4_RXDAT 62 +#define LOCHNAGAR2_PIN_GF_AIF4_LRCLK 63 +#define LOCHNAGAR2_PIN_GF_AIF4_TXDAT 64 +#define LOCHNAGAR2_PIN_GF_AIF1_BCLK 65 +#define LOCHNAGAR2_PIN_GF_AIF1_RXDAT 66 +#define LOCHNAGAR2_PIN_GF_AIF1_LRCLK 67 +#define LOCHNAGAR2_PIN_GF_AIF1_TXDAT 68 +#define LOCHNAGAR2_PIN_GF_AIF2_BCLK 69 +#define LOCHNAGAR2_PIN_GF_AIF2_RXDAT 70 +#define LOCHNAGAR2_PIN_GF_AIF2_LRCLK 71 +#define LOCHNAGAR2_PIN_GF_AIF2_TXDAT 72 +#define LOCHNAGAR2_PIN_DSP_UART1_RX 73 +#define LOCHNAGAR2_PIN_DSP_UART1_TX 74 +#define LOCHNAGAR2_PIN_DSP_UART2_RX 75 +#define LOCHNAGAR2_PIN_DSP_UART2_TX 76 +#define LOCHNAGAR2_PIN_GF_UART2_RX 77 +#define LOCHNAGAR2_PIN_GF_UART2_TX 78 +#define LOCHNAGAR2_PIN_USB_UART_RX 79 +#define LOCHNAGAR2_PIN_CDC_PDMCLK1 80 +#define LOCHNAGAR2_PIN_CDC_PDMDAT1 81 +#define LOCHNAGAR2_PIN_CDC_PDMCLK2 82 +#define LOCHNAGAR2_PIN_CDC_PDMDAT2 83 +#define LOCHNAGAR2_PIN_CDC_DMICCLK1 84 +#define LOCHNAGAR2_PIN_CDC_DMICDAT1 85 +#define LOCHNAGAR2_PIN_CDC_DMICCLK2 86 +#define LOCHNAGAR2_PIN_CDC_DMICDAT2 87 +#define LOCHNAGAR2_PIN_CDC_DMICCLK3 88 +#define LOCHNAGAR2_PIN_CDC_DMICDAT3 89 +#define LOCHNAGAR2_PIN_CDC_DMICCLK4 90 +#define LOCHNAGAR2_PIN_CDC_DMICDAT4 91 +#define LOCHNAGAR2_PIN_DSP_DMICCLK1 92 +#define LOCHNAGAR2_PIN_DSP_DMICDAT1 93 +#define LOCHNAGAR2_PIN_DSP_DMICCLK2 94 +#define LOCHNAGAR2_PIN_DSP_DMICDAT2 95 +#define LOCHNAGAR2_PIN_I2C2_SCL 96 +#define LOCHNAGAR2_PIN_I2C2_SDA 97 +#define LOCHNAGAR2_PIN_I2C3_SCL 98 +#define LOCHNAGAR2_PIN_I2C3_SDA 99 +#define LOCHNAGAR2_PIN_I2C4_SCL 100 +#define LOCHNAGAR2_PIN_I2C4_SDA 101 +#define LOCHNAGAR2_PIN_DSP_STANDBY 102 +#define LOCHNAGAR2_PIN_CDC_MCLK1 103 +#define LOCHNAGAR2_PIN_CDC_MCLK2 104 +#define LOCHNAGAR2_PIN_DSP_CLKIN 105 +#define LOCHNAGAR2_PIN_PSIA1_MCLK 106 +#define LOCHNAGAR2_PIN_PSIA2_MCLK 107 +#define LOCHNAGAR2_PIN_GF_GPIO1 108 +#define LOCHNAGAR2_PIN_GF_GPIO5 109 +#define LOCHNAGAR2_PIN_DSP_GPIO20 110 +#define LOCHNAGAR2_PIN_NUM_GPIOS 111 + +#endif diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h index de8b588c8776..8f2a8918bfa3 100644 --- a/include/linux/mfd/cros_ec.h +++ b/include/linux/mfd/cros_ec.h @@ -282,16 +282,6 @@ int cros_ec_cmd_xfer_status(struct cros_ec_device *ec_dev, struct cros_ec_command *msg); /** - * cros_ec_remove() - Remove a ChromeOS EC. - * @ec_dev: Device to register. - * - * Call this to deregister a ChromeOS EC, then clean up any private data. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_remove(struct cros_ec_device *ec_dev); - -/** * cros_ec_register() - Register a new ChromeOS EC, using the provided info. * @ec_dev: Device to register. * @@ -335,15 +325,4 @@ int cros_ec_get_next_event(struct cros_ec_device *ec_dev, bool *wake_event); */ u32 cros_ec_get_host_event(struct cros_ec_device *ec_dev); -/* sysfs stuff */ -extern struct attribute_group cros_ec_attr_group; -extern struct attribute_group cros_ec_lightbar_attr_group; -extern struct attribute_group cros_ec_vbc_attr_group; - -/* debugfs stuff */ -int cros_ec_debugfs_init(struct cros_ec_dev *ec); -void cros_ec_debugfs_remove(struct cros_ec_dev *ec); -void cros_ec_debugfs_suspend(struct cros_ec_dev *ec); -void cros_ec_debugfs_resume(struct cros_ec_dev *ec); - #endif /* __LINUX_MFD_CROS_EC_H */ diff --git a/include/linux/mfd/lochnagar.h b/include/linux/mfd/lochnagar.h new file mode 100644 index 000000000000..ff9e64cfc9fb --- /dev/null +++ b/include/linux/mfd/lochnagar.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Lochnagar internals + * + * Copyright (c) 2013-2018 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + * + * Author: Charles Keepax <ckeepax@opensource.cirrus.com> + */ + +#include <linux/device.h> +#include <linux/mutex.h> +#include <linux/regmap.h> + +#ifndef CIRRUS_LOCHNAGAR_H +#define CIRRUS_LOCHNAGAR_H + +enum lochnagar_type { + LOCHNAGAR1, + LOCHNAGAR2, +}; + +/** + * struct lochnagar - Core data for the Lochnagar audio board driver. + * + * @type: The type of Lochnagar device connected. + * @dev: A pointer to the struct device for the main MFD. + * @regmap: The devices main register map. + * @analogue_config_lock: Lock used to protect updates in the analogue + * configuration as these must not be changed whilst the hardware is processing + * the last update. + */ +struct lochnagar { + enum lochnagar_type type; + struct device *dev; + struct regmap *regmap; + + /* Lock to protect updates to the analogue configuration */ + struct mutex analogue_config_lock; +}; + +/* Register Addresses */ +#define LOCHNAGAR_SOFTWARE_RESET 0x00 +#define LOCHNAGAR_FIRMWARE_ID1 0x01 +#define LOCHNAGAR_FIRMWARE_ID2 0x02 + +/* (0x0000) Software Reset */ +#define LOCHNAGAR_DEVICE_ID_MASK 0xFFFC +#define LOCHNAGAR_DEVICE_ID_SHIFT 2 +#define LOCHNAGAR_REV_ID_MASK 0x0003 +#define LOCHNAGAR_REV_ID_SHIFT 0 + +int lochnagar_update_config(struct lochnagar *lochnagar); + +#endif diff --git a/include/linux/mfd/lochnagar1_regs.h b/include/linux/mfd/lochnagar1_regs.h new file mode 100644 index 000000000000..114b846245d9 --- /dev/null +++ b/include/linux/mfd/lochnagar1_regs.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Lochnagar1 register definitions + * + * Copyright (c) 2017-2018 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + * + * Author: Charles Keepax <ckeepax@opensource.cirrus.com> + */ + +#ifndef LOCHNAGAR1_REGISTERS_H +#define LOCHNAGAR1_REGISTERS_H + +/* Register Addresses */ +#define LOCHNAGAR1_CDC_AIF1_SEL 0x0008 +#define LOCHNAGAR1_CDC_AIF2_SEL 0x0009 +#define LOCHNAGAR1_CDC_AIF3_SEL 0x000A +#define LOCHNAGAR1_CDC_MCLK1_SEL 0x000B +#define LOCHNAGAR1_CDC_MCLK2_SEL 0x000C +#define LOCHNAGAR1_CDC_AIF_CTRL1 0x000D +#define LOCHNAGAR1_CDC_AIF_CTRL2 0x000E +#define LOCHNAGAR1_EXT_AIF_CTRL 0x000F +#define LOCHNAGAR1_DSP_AIF1_SEL 0x0010 +#define LOCHNAGAR1_DSP_AIF2_SEL 0x0011 +#define LOCHNAGAR1_DSP_CLKIN_SEL 0x0012 +#define LOCHNAGAR1_DSP_AIF 0x0013 +#define LOCHNAGAR1_GF_AIF1 0x0014 +#define LOCHNAGAR1_GF_AIF2 0x0015 +#define LOCHNAGAR1_PSIA_AIF 0x0016 +#define LOCHNAGAR1_PSIA1_SEL 0x0017 +#define LOCHNAGAR1_PSIA2_SEL 0x0018 +#define LOCHNAGAR1_SPDIF_AIF_SEL 0x0019 +#define LOCHNAGAR1_GF_AIF3_SEL 0x001C +#define LOCHNAGAR1_GF_AIF4_SEL 0x001D +#define LOCHNAGAR1_GF_CLKOUT1_SEL 0x001E +#define LOCHNAGAR1_GF_AIF1_SEL 0x001F +#define LOCHNAGAR1_GF_AIF2_SEL 0x0020 +#define LOCHNAGAR1_GF_GPIO2 0x0026 +#define LOCHNAGAR1_GF_GPIO3 0x0027 +#define LOCHNAGAR1_GF_GPIO7 0x0028 +#define LOCHNAGAR1_RST 0x0029 +#define LOCHNAGAR1_LED1 0x002A +#define LOCHNAGAR1_LED2 0x002B +#define LOCHNAGAR1_I2C_CTRL 0x0046 + +/* + * (0x0008 - 0x000C, 0x0010 - 0x0012, 0x0017 - 0x0020) + * CDC_AIF1_SEL - GF_AIF2_SEL + */ +#define LOCHNAGAR1_SRC_MASK 0xFF +#define LOCHNAGAR1_SRC_SHIFT 0 + +/* (0x000D) CDC_AIF_CTRL1 */ +#define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_MASK 0x40 +#define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_SHIFT 6 +#define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_MASK 0x20 +#define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_SHIFT 5 +#define LOCHNAGAR1_CDC_AIF2_ENA_MASK 0x10 +#define LOCHNAGAR1_CDC_AIF2_ENA_SHIFT 4 +#define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_MASK 0x04 +#define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_SHIFT 2 +#define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_MASK 0x02 +#define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_SHIFT 1 +#define LOCHNAGAR1_CDC_AIF1_ENA_MASK 0x01 +#define LOCHNAGAR1_CDC_AIF1_ENA_SHIFT 0 + +/* (0x000E) CDC_AIF_CTRL2 */ +#define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_MASK 0x40 +#define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_SHIFT 6 +#define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_MASK 0x20 +#define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_SHIFT 5 +#define LOCHNAGAR1_CDC_AIF3_ENA_MASK 0x10 +#define LOCHNAGAR1_CDC_AIF3_ENA_SHIFT 4 +#define LOCHNAGAR1_CDC_MCLK1_ENA_MASK 0x02 +#define LOCHNAGAR1_CDC_MCLK1_ENA_SHIFT 1 +#define LOCHNAGAR1_CDC_MCLK2_ENA_MASK 0x01 +#define LOCHNAGAR1_CDC_MCLK2_ENA_SHIFT 0 + +/* (0x000F) EXT_AIF_CTRL */ +#define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_MASK 0x20 +#define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_SHIFT 5 +#define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_MASK 0x10 +#define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_SHIFT 4 +#define LOCHNAGAR1_SPDIF_AIF_ENA_MASK 0x08 +#define LOCHNAGAR1_SPDIF_AIF_ENA_SHIFT 3 + +/* (0x0013) DSP_AIF */ +#define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_MASK 0x40 +#define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_SHIFT 6 +#define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_MASK 0x20 +#define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_SHIFT 5 +#define LOCHNAGAR1_DSP_AIF2_ENA_MASK 0x10 +#define LOCHNAGAR1_DSP_AIF2_ENA_SHIFT 4 +#define LOCHNAGAR1_DSP_CLKIN_ENA_MASK 0x08 +#define LOCHNAGAR1_DSP_CLKIN_ENA_SHIFT 3 +#define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_MASK 0x04 +#define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_SHIFT 2 +#define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_MASK 0x02 +#define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_SHIFT 1 +#define LOCHNAGAR1_DSP_AIF1_ENA_MASK 0x01 +#define LOCHNAGAR1_DSP_AIF1_ENA_SHIFT 0 + +/* (0x0014) GF_AIF1 */ +#define LOCHNAGAR1_GF_CLKOUT1_ENA_MASK 0x40 +#define LOCHNAGAR1_GF_CLKOUT1_ENA_SHIFT 6 +#define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_MASK 0x20 +#define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_SHIFT 5 +#define LOCHNAGAR1_GF_AIF3_BCLK_DIR_MASK 0x10 +#define LOCHNAGAR1_GF_AIF3_BCLK_DIR_SHIFT 4 +#define LOCHNAGAR1_GF_AIF3_ENA_MASK 0x08 +#define LOCHNAGAR1_GF_AIF3_ENA_SHIFT 3 +#define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_MASK 0x04 +#define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_SHIFT 2 +#define LOCHNAGAR1_GF_AIF1_BCLK_DIR_MASK 0x02 +#define LOCHNAGAR1_GF_AIF1_BCLK_DIR_SHIFT 1 +#define LOCHNAGAR1_GF_AIF1_ENA_MASK 0x01 +#define LOCHNAGAR1_GF_AIF1_ENA_SHIFT 0 + +/* (0x0015) GF_AIF2 */ +#define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_MASK 0x20 +#define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_SHIFT 5 +#define LOCHNAGAR1_GF_AIF4_BCLK_DIR_MASK 0x10 +#define LOCHNAGAR1_GF_AIF4_BCLK_DIR_SHIFT 4 +#define LOCHNAGAR1_GF_AIF4_ENA_MASK 0x08 +#define LOCHNAGAR1_GF_AIF4_ENA_SHIFT 3 +#define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_MASK 0x04 +#define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_SHIFT 2 +#define LOCHNAGAR1_GF_AIF2_BCLK_DIR_MASK 0x02 +#define LOCHNAGAR1_GF_AIF2_BCLK_DIR_SHIFT 1 +#define LOCHNAGAR1_GF_AIF2_ENA_MASK 0x01 +#define LOCHNAGAR1_GF_AIF2_ENA_SHIFT 0 + +/* (0x0016) PSIA_AIF */ +#define LOCHNAGAR1_PSIA2_LRCLK_DIR_MASK 0x40 +#define LOCHNAGAR1_PSIA2_LRCLK_DIR_SHIFT 6 +#define LOCHNAGAR1_PSIA2_BCLK_DIR_MASK 0x20 +#define LOCHNAGAR1_PSIA2_BCLK_DIR_SHIFT 5 +#define LOCHNAGAR1_PSIA2_ENA_MASK 0x10 +#define LOCHNAGAR1_PSIA2_ENA_SHIFT 4 +#define LOCHNAGAR1_PSIA1_LRCLK_DIR_MASK 0x04 +#define LOCHNAGAR1_PSIA1_LRCLK_DIR_SHIFT 2 +#define LOCHNAGAR1_PSIA1_BCLK_DIR_MASK 0x02 +#define LOCHNAGAR1_PSIA1_BCLK_DIR_SHIFT 1 +#define LOCHNAGAR1_PSIA1_ENA_MASK 0x01 +#define LOCHNAGAR1_PSIA1_ENA_SHIFT 0 + +/* (0x0029) RST */ +#define LOCHNAGAR1_DSP_RESET_MASK 0x02 +#define LOCHNAGAR1_DSP_RESET_SHIFT 1 +#define LOCHNAGAR1_CDC_RESET_MASK 0x01 +#define LOCHNAGAR1_CDC_RESET_SHIFT 0 + +/* (0x0046) I2C_CTRL */ +#define LOCHNAGAR1_CDC_CIF_MODE_MASK 0x01 +#define LOCHNAGAR1_CDC_CIF_MODE_SHIFT 0 + +#endif diff --git a/include/linux/mfd/lochnagar2_regs.h b/include/linux/mfd/lochnagar2_regs.h new file mode 100644 index 000000000000..419b25a332fd --- /dev/null +++ b/include/linux/mfd/lochnagar2_regs.h @@ -0,0 +1,291 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Lochnagar2 register definitions + * + * Copyright (c) 2017-2018 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + * + * Author: Charles Keepax <ckeepax@opensource.cirrus.com> + */ + +#ifndef LOCHNAGAR2_REGISTERS_H +#define LOCHNAGAR2_REGISTERS_H + +/* Register Addresses */ +#define LOCHNAGAR2_CDC_AIF1_CTRL 0x000D +#define LOCHNAGAR2_CDC_AIF2_CTRL 0x000E +#define LOCHNAGAR2_CDC_AIF3_CTRL 0x000F +#define LOCHNAGAR2_DSP_AIF1_CTRL 0x0010 +#define LOCHNAGAR2_DSP_AIF2_CTRL 0x0011 +#define LOCHNAGAR2_PSIA1_CTRL 0x0012 +#define LOCHNAGAR2_PSIA2_CTRL 0x0013 +#define LOCHNAGAR2_GF_AIF3_CTRL 0x0014 +#define LOCHNAGAR2_GF_AIF4_CTRL 0x0015 +#define LOCHNAGAR2_GF_AIF1_CTRL 0x0016 +#define LOCHNAGAR2_GF_AIF2_CTRL 0x0017 +#define LOCHNAGAR2_SPDIF_AIF_CTRL 0x0018 +#define LOCHNAGAR2_USB_AIF1_CTRL 0x0019 +#define LOCHNAGAR2_USB_AIF2_CTRL 0x001A +#define LOCHNAGAR2_ADAT_AIF_CTRL 0x001B +#define LOCHNAGAR2_CDC_MCLK1_CTRL 0x001E +#define LOCHNAGAR2_CDC_MCLK2_CTRL 0x001F +#define LOCHNAGAR2_DSP_CLKIN_CTRL 0x0020 +#define LOCHNAGAR2_PSIA1_MCLK_CTRL 0x0021 +#define LOCHNAGAR2_PSIA2_MCLK_CTRL 0x0022 +#define LOCHNAGAR2_SPDIF_MCLK_CTRL 0x0023 +#define LOCHNAGAR2_GF_CLKOUT1_CTRL 0x0024 +#define LOCHNAGAR2_GF_CLKOUT2_CTRL 0x0025 +#define LOCHNAGAR2_ADAT_MCLK_CTRL 0x0026 +#define LOCHNAGAR2_SOUNDCARD_MCLK_CTRL 0x0027 +#define LOCHNAGAR2_GPIO_FPGA_GPIO1 0x0031 +#define LOCHNAGAR2_GPIO_FPGA_GPIO2 0x0032 +#define LOCHNAGAR2_GPIO_FPGA_GPIO3 0x0033 +#define LOCHNAGAR2_GPIO_FPGA_GPIO4 0x0034 +#define LOCHNAGAR2_GPIO_FPGA_GPIO5 0x0035 +#define LOCHNAGAR2_GPIO_FPGA_GPIO6 0x0036 +#define LOCHNAGAR2_GPIO_CDC_GPIO1 0x0037 +#define LOCHNAGAR2_GPIO_CDC_GPIO2 0x0038 +#define LOCHNAGAR2_GPIO_CDC_GPIO3 0x0039 +#define LOCHNAGAR2_GPIO_CDC_GPIO4 0x003A +#define LOCHNAGAR2_GPIO_CDC_GPIO5 0x003B +#define LOCHNAGAR2_GPIO_CDC_GPIO6 0x003C +#define LOCHNAGAR2_GPIO_CDC_GPIO7 0x003D +#define LOCHNAGAR2_GPIO_CDC_GPIO8 0x003E +#define LOCHNAGAR2_GPIO_DSP_GPIO1 0x003F +#define LOCHNAGAR2_GPIO_DSP_GPIO2 0x0040 +#define LOCHNAGAR2_GPIO_DSP_GPIO3 0x0041 +#define LOCHNAGAR2_GPIO_DSP_GPIO4 0x0042 +#define LOCHNAGAR2_GPIO_DSP_GPIO5 0x0043 +#define LOCHNAGAR2_GPIO_DSP_GPIO6 0x0044 +#define LOCHNAGAR2_GPIO_GF_GPIO2 0x0045 +#define LOCHNAGAR2_GPIO_GF_GPIO3 0x0046 +#define LOCHNAGAR2_GPIO_GF_GPIO7 0x0047 +#define LOCHNAGAR2_GPIO_CDC_AIF1_BCLK 0x0048 +#define LOCHNAGAR2_GPIO_CDC_AIF1_RXDAT 0x0049 +#define LOCHNAGAR2_GPIO_CDC_AIF1_LRCLK 0x004A +#define LOCHNAGAR2_GPIO_CDC_AIF1_TXDAT 0x004B +#define LOCHNAGAR2_GPIO_CDC_AIF2_BCLK 0x004C +#define LOCHNAGAR2_GPIO_CDC_AIF2_RXDAT 0x004D +#define LOCHNAGAR2_GPIO_CDC_AIF2_LRCLK 0x004E +#define LOCHNAGAR2_GPIO_CDC_AIF2_TXDAT 0x004F +#define LOCHNAGAR2_GPIO_CDC_AIF3_BCLK 0x0050 +#define LOCHNAGAR2_GPIO_CDC_AIF3_RXDAT 0x0051 +#define LOCHNAGAR2_GPIO_CDC_AIF3_LRCLK 0x0052 +#define LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT 0x0053 +#define LOCHNAGAR2_GPIO_DSP_AIF1_BCLK 0x0054 +#define LOCHNAGAR2_GPIO_DSP_AIF1_RXDAT 0x0055 +#define LOCHNAGAR2_GPIO_DSP_AIF1_LRCLK 0x0056 +#define LOCHNAGAR2_GPIO_DSP_AIF1_TXDAT 0x0057 +#define LOCHNAGAR2_GPIO_DSP_AIF2_BCLK 0x0058 +#define LOCHNAGAR2_GPIO_DSP_AIF2_RXDAT 0x0059 +#define LOCHNAGAR2_GPIO_DSP_AIF2_LRCLK 0x005A +#define LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT 0x005B +#define LOCHNAGAR2_GPIO_PSIA1_BCLK 0x005C +#define LOCHNAGAR2_GPIO_PSIA1_RXDAT 0x005D +#define LOCHNAGAR2_GPIO_PSIA1_LRCLK 0x005E +#define LOCHNAGAR2_GPIO_PSIA1_TXDAT 0x005F +#define LOCHNAGAR2_GPIO_PSIA2_BCLK 0x0060 +#define LOCHNAGAR2_GPIO_PSIA2_RXDAT 0x0061 +#define LOCHNAGAR2_GPIO_PSIA2_LRCLK 0x0062 +#define LOCHNAGAR2_GPIO_PSIA2_TXDAT 0x0063 +#define LOCHNAGAR2_GPIO_GF_AIF3_BCLK 0x0064 +#define LOCHNAGAR2_GPIO_GF_AIF3_RXDAT 0x0065 +#define LOCHNAGAR2_GPIO_GF_AIF3_LRCLK 0x0066 +#define LOCHNAGAR2_GPIO_GF_AIF3_TXDAT 0x0067 +#define LOCHNAGAR2_GPIO_GF_AIF4_BCLK 0x0068 +#define LOCHNAGAR2_GPIO_GF_AIF4_RXDAT 0x0069 +#define LOCHNAGAR2_GPIO_GF_AIF4_LRCLK 0x006A +#define LOCHNAGAR2_GPIO_GF_AIF4_TXDAT 0x006B +#define LOCHNAGAR2_GPIO_GF_AIF1_BCLK 0x006C +#define LOCHNAGAR2_GPIO_GF_AIF1_RXDAT 0x006D +#define LOCHNAGAR2_GPIO_GF_AIF1_LRCLK 0x006E +#define LOCHNAGAR2_GPIO_GF_AIF1_TXDAT 0x006F +#define LOCHNAGAR2_GPIO_GF_AIF2_BCLK 0x0070 +#define LOCHNAGAR2_GPIO_GF_AIF2_RXDAT 0x0071 +#define LOCHNAGAR2_GPIO_GF_AIF2_LRCLK 0x0072 +#define LOCHNAGAR2_GPIO_GF_AIF2_TXDAT 0x0073 +#define LOCHNAGAR2_GPIO_DSP_UART1_RX 0x0074 +#define LOCHNAGAR2_GPIO_DSP_UART1_TX 0x0075 +#define LOCHNAGAR2_GPIO_DSP_UART2_RX 0x0076 +#define LOCHNAGAR2_GPIO_DSP_UART2_TX 0x0077 +#define LOCHNAGAR2_GPIO_GF_UART2_RX 0x0078 +#define LOCHNAGAR2_GPIO_GF_UART2_TX 0x0079 +#define LOCHNAGAR2_GPIO_USB_UART_RX 0x007A +#define LOCHNAGAR2_GPIO_CDC_PDMCLK1 0x007C +#define LOCHNAGAR2_GPIO_CDC_PDMDAT1 0x007D +#define LOCHNAGAR2_GPIO_CDC_PDMCLK2 0x007E +#define LOCHNAGAR2_GPIO_CDC_PDMDAT2 0x007F +#define LOCHNAGAR2_GPIO_CDC_DMICCLK1 0x0080 +#define LOCHNAGAR2_GPIO_CDC_DMICDAT1 0x0081 +#define LOCHNAGAR2_GPIO_CDC_DMICCLK2 0x0082 +#define LOCHNAGAR2_GPIO_CDC_DMICDAT2 0x0083 +#define LOCHNAGAR2_GPIO_CDC_DMICCLK3 0x0084 +#define LOCHNAGAR2_GPIO_CDC_DMICDAT3 0x0085 +#define LOCHNAGAR2_GPIO_CDC_DMICCLK4 0x0086 +#define LOCHNAGAR2_GPIO_CDC_DMICDAT4 0x0087 +#define LOCHNAGAR2_GPIO_DSP_DMICCLK1 0x0088 +#define LOCHNAGAR2_GPIO_DSP_DMICDAT1 0x0089 +#define LOCHNAGAR2_GPIO_DSP_DMICCLK2 0x008A +#define LOCHNAGAR2_GPIO_DSP_DMICDAT2 0x008B +#define LOCHNAGAR2_GPIO_I2C2_SCL 0x008C +#define LOCHNAGAR2_GPIO_I2C2_SDA 0x008D +#define LOCHNAGAR2_GPIO_I2C3_SCL 0x008E +#define LOCHNAGAR2_GPIO_I2C3_SDA 0x008F +#define LOCHNAGAR2_GPIO_I2C4_SCL 0x0090 +#define LOCHNAGAR2_GPIO_I2C4_SDA 0x0091 +#define LOCHNAGAR2_GPIO_DSP_STANDBY 0x0092 +#define LOCHNAGAR2_GPIO_CDC_MCLK1 0x0093 +#define LOCHNAGAR2_GPIO_CDC_MCLK2 0x0094 +#define LOCHNAGAR2_GPIO_DSP_CLKIN 0x0095 +#define LOCHNAGAR2_GPIO_PSIA1_MCLK 0x0096 +#define LOCHNAGAR2_GPIO_PSIA2_MCLK 0x0097 +#define LOCHNAGAR2_GPIO_GF_GPIO1 0x0098 +#define LOCHNAGAR2_GPIO_GF_GPIO5 0x0099 +#define LOCHNAGAR2_GPIO_DSP_GPIO20 0x009A +#define LOCHNAGAR2_GPIO_CHANNEL1 0x00B9 +#define LOCHNAGAR2_GPIO_CHANNEL2 0x00BA +#define LOCHNAGAR2_GPIO_CHANNEL3 0x00BB +#define LOCHNAGAR2_GPIO_CHANNEL4 0x00BC +#define LOCHNAGAR2_GPIO_CHANNEL5 0x00BD +#define LOCHNAGAR2_GPIO_CHANNEL6 0x00BE +#define LOCHNAGAR2_GPIO_CHANNEL7 0x00BF +#define LOCHNAGAR2_GPIO_CHANNEL8 0x00C0 +#define LOCHNAGAR2_GPIO_CHANNEL9 0x00C1 +#define LOCHNAGAR2_GPIO_CHANNEL10 0x00C2 +#define LOCHNAGAR2_GPIO_CHANNEL11 0x00C3 +#define LOCHNAGAR2_GPIO_CHANNEL12 0x00C4 +#define LOCHNAGAR2_GPIO_CHANNEL13 0x00C5 +#define LOCHNAGAR2_GPIO_CHANNEL14 0x00C6 +#define LOCHNAGAR2_GPIO_CHANNEL15 0x00C7 +#define LOCHNAGAR2_GPIO_CHANNEL16 0x00C8 +#define LOCHNAGAR2_MINICARD_RESETS 0x00DF +#define LOCHNAGAR2_ANALOGUE_PATH_CTRL1 0x00E3 +#define LOCHNAGAR2_ANALOGUE_PATH_CTRL2 0x00E4 +#define LOCHNAGAR2_COMMS_CTRL4 0x00F0 +#define LOCHNAGAR2_SPDIF_CTRL 0x00FE +#define LOCHNAGAR2_IMON_CTRL1 0x0108 +#define LOCHNAGAR2_IMON_CTRL2 0x0109 +#define LOCHNAGAR2_IMON_CTRL3 0x010A +#define LOCHNAGAR2_IMON_CTRL4 0x010B +#define LOCHNAGAR2_IMON_DATA1 0x010C +#define LOCHNAGAR2_IMON_DATA2 0x010D +#define LOCHNAGAR2_POWER_CTRL 0x0116 +#define LOCHNAGAR2_MICVDD_CTRL1 0x0119 +#define LOCHNAGAR2_MICVDD_CTRL2 0x011B +#define LOCHNAGAR2_VDDCORE_CDC_CTRL1 0x011E +#define LOCHNAGAR2_VDDCORE_CDC_CTRL2 0x0120 +#define LOCHNAGAR2_SOUNDCARD_AIF_CTRL 0x0180 + +/* (0x000D-0x001B, 0x0180) CDC_AIF1_CTRL - SOUNCARD_AIF_CTRL */ +#define LOCHNAGAR2_AIF_ENA_MASK 0x8000 +#define LOCHNAGAR2_AIF_ENA_SHIFT 15 +#define LOCHNAGAR2_AIF_LRCLK_DIR_MASK 0x4000 +#define LOCHNAGAR2_AIF_LRCLK_DIR_SHIFT 14 +#define LOCHNAGAR2_AIF_BCLK_DIR_MASK 0x2000 +#define LOCHNAGAR2_AIF_BCLK_DIR_SHIFT 13 +#define LOCHNAGAR2_AIF_SRC_MASK 0x00FF +#define LOCHNAGAR2_AIF_SRC_SHIFT 0 + +/* (0x001E - 0x0027) CDC_MCLK1_CTRL - SOUNDCARD_MCLK_CTRL */ +#define LOCHNAGAR2_CLK_ENA_MASK 0x8000 +#define LOCHNAGAR2_CLK_ENA_SHIFT 15 +#define LOCHNAGAR2_CLK_SRC_MASK 0x00FF +#define LOCHNAGAR2_CLK_SRC_SHIFT 0 + +/* (0x0031 - 0x009A) GPIO_FPGA_GPIO1 - GPIO_DSP_GPIO20 */ +#define LOCHNAGAR2_GPIO_SRC_MASK 0x00FF +#define LOCHNAGAR2_GPIO_SRC_SHIFT 0 + +/* (0x00B9 - 0x00C8) GPIO_CHANNEL1 - GPIO_CHANNEL16 */ +#define LOCHNAGAR2_GPIO_CHANNEL_STS_MASK 0x8000 +#define LOCHNAGAR2_GPIO_CHANNEL_STS_SHIFT 15 +#define LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK 0x00FF +#define LOCHNAGAR2_GPIO_CHANNEL_SRC_SHIFT 0 + +/* (0x00DF) MINICARD_RESETS */ +#define LOCHNAGAR2_DSP_RESET_MASK 0x0002 +#define LOCHNAGAR2_DSP_RESET_SHIFT 1 +#define LOCHNAGAR2_CDC_RESET_MASK 0x0001 +#define LOCHNAGAR2_CDC_RESET_SHIFT 0 + +/* (0x00E3) ANALOGUE_PATH_CTRL1 */ +#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK 0x8000 +#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_SHIFT 15 +#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK 0x4000 +#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_SHIFT 14 + +/* (0x00E4) ANALOGUE_PATH_CTRL2 */ +#define LOCHNAGAR2_P2_INPUT_BIAS_ENA_MASK 0x0080 +#define LOCHNAGAR2_P2_INPUT_BIAS_ENA_SHIFT 7 +#define LOCHNAGAR2_P1_INPUT_BIAS_ENA_MASK 0x0040 +#define LOCHNAGAR2_P1_INPUT_BIAS_ENA_SHIFT 6 +#define LOCHNAGAR2_P2_MICBIAS_SRC_MASK 0x0038 +#define LOCHNAGAR2_P2_MICBIAS_SRC_SHIFT 3 +#define LOCHNAGAR2_P1_MICBIAS_SRC_MASK 0x0007 +#define LOCHNAGAR2_P1_MICBIAS_SRC_SHIFT 0 + +/* (0x00F0) COMMS_CTRL4 */ +#define LOCHNAGAR2_CDC_CIF1MODE_MASK 0x0001 +#define LOCHNAGAR2_CDC_CIF1MODE_SHIFT 0 + +/* (0x00FE) SPDIF_CTRL */ +#define LOCHNAGAR2_SPDIF_HWMODE_MASK 0x0008 +#define LOCHNAGAR2_SPDIF_HWMODE_SHIFT 3 +#define LOCHNAGAR2_SPDIF_RESET_MASK 0x0001 +#define LOCHNAGAR2_SPDIF_RESET_SHIFT 0 + +/* (0x0108) IMON_CTRL1 */ +#define LOCHNAGAR2_IMON_ENA_MASK 0x8000 +#define LOCHNAGAR2_IMON_ENA_SHIFT 15 +#define LOCHNAGAR2_IMON_MEASURED_CHANNELS_MASK 0x03FC +#define LOCHNAGAR2_IMON_MEASURED_CHANNELS_SHIFT 2 +#define LOCHNAGAR2_IMON_MODE_SEL_MASK 0x0003 +#define LOCHNAGAR2_IMON_MODE_SEL_SHIFT 0 + +/* (0x0109) IMON_CTRL2 */ +#define LOCHNAGAR2_IMON_FSR_MASK 0x03FF +#define LOCHNAGAR2_IMON_FSR_SHIFT 0 + +/* (0x010A) IMON_CTRL3 */ +#define LOCHNAGAR2_IMON_DONE_MASK 0x0004 +#define LOCHNAGAR2_IMON_DONE_SHIFT 2 +#define LOCHNAGAR2_IMON_CONFIGURE_MASK 0x0002 +#define LOCHNAGAR2_IMON_CONFIGURE_SHIFT 1 +#define LOCHNAGAR2_IMON_MEASURE_MASK 0x0001 +#define LOCHNAGAR2_IMON_MEASURE_SHIFT 0 + +/* (0x010B) IMON_CTRL4 */ +#define LOCHNAGAR2_IMON_DATA_REQ_MASK 0x0080 +#define LOCHNAGAR2_IMON_DATA_REQ_SHIFT 7 +#define LOCHNAGAR2_IMON_CH_SEL_MASK 0x0070 +#define LOCHNAGAR2_IMON_CH_SEL_SHIFT 4 +#define LOCHNAGAR2_IMON_DATA_RDY_MASK 0x0008 +#define LOCHNAGAR2_IMON_DATA_RDY_SHIFT 3 +#define LOCHNAGAR2_IMON_CH_SRC_MASK 0x0007 +#define LOCHNAGAR2_IMON_CH_SRC_SHIFT 0 + +/* (0x010C, 0x010D) IMON_DATA1, IMON_DATA2 */ +#define LOCHNAGAR2_IMON_DATA_MASK 0xFFFF +#define LOCHNAGAR2_IMON_DATA_SHIFT 0 + +/* (0x0116) PO |