diff options
author | Graeme Gregory <gg@slimlogic.co.uk> | 2012-05-15 15:48:56 +0900 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2012-05-18 16:54:47 +0100 |
commit | 2945fbc2fcd83df03165342c1bc3ab83d0fe9c04 (patch) | |
tree | 7e20d24f42bf9af630526b3eb5d2ad1b5accf51d /include | |
parent | 38e7f5d1b73e71f87745a9c3e5806a6c28c34a53 (diff) |
mfd: palmas PMIC device support
Palmas is a PMIC from Texas Instruments and this is the MFD part of the
driver for this chip. The PMIC has SMPS and LDO regulators, a general
purpose ADC, GPIO, USB OTG mode detection, watchdog and RTC features.
Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk>
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/mfd/palmas.h | 2620 |
1 files changed, 2620 insertions, 0 deletions
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h new file mode 100644 index 000000000000..9cbc642d40ad --- /dev/null +++ b/include/linux/mfd/palmas.h @@ -0,0 +1,2620 @@ +/* + * TI Palmas + * + * Copyright 2011 Texas Instruments Inc. + * + * Author: Graeme Gregory <gg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __LINUX_MFD_PALMAS_H +#define __LINUX_MFD_PALMAS_H + +#include <linux/usb/otg.h> +#include <linux/leds.h> +#include <linux/regmap.h> +#include <linux/regulator/driver.h> + +#define PALMAS_NUM_CLIENTS 3 + +struct palmas_pmic; + +struct palmas { + struct device *dev; + + struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS]; + struct regmap *regmap[PALMAS_NUM_CLIENTS]; + + /* Stored chip id */ + int id; + + /* IRQ Data */ + int irq; + u32 irq_mask; + struct mutex irq_lock; + struct regmap_irq_chip_data *irq_data; + + /* Child Devices */ + struct palmas_pmic *pmic; + + /* GPIO MUXing */ + u8 gpio_muxed; + u8 led_muxed; + u8 pwm_muxed; +}; + +struct palmas_reg_init { + /* warm_rest controls the voltage levels after a warm reset + * + * 0: reload default values from OTP on warm reset + * 1: maintain voltage from VSEL on warm reset + */ + int warm_reset; + + /* roof_floor controls whether the regulator uses the i2c style + * of DVS or uses the method where a GPIO or other control method is + * attached to the NSLEEP/ENABLE1/ENABLE2 pins + * + * For SMPS + * + * 0: i2c selection of voltage + * 1: pin selection of voltage. + * + * For LDO unused + */ + int roof_floor; + + /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in + * the data sheet. + * + * For SMPS + * + * 0: Off + * 1: AUTO + * 2: ECO + * 3: Forced PWM + * + * For LDO + * + * 0: Off + * 1: On + */ + int mode_sleep; + + /* tstep is the timestep loaded to the TSTEP register + * + * For SMPS + * + * 0: Jump (no slope control) + * 1: 10mV/us + * 2: 5mV/us + * 3: 2.5mV/us + * + * For LDO unused + */ + int tstep; + + /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE + * register. Set this is the default voltage set in OTP needs + * to be overridden. + */ + u8 vsel; + +}; + +struct palmas_pmic_platform_data { + /* An array of pointers to regulator init data indexed by regulator + * ID + */ + struct regulator_init_data **reg_data; + + /* An array of pointers to structures containing sleep mode and DVS + * configuration for regulators indexed by ID + */ + struct palmas_reg_init **reg_init; + + /* use LDO6 for vibrator control */ + int ldo6_vibrator; + + +}; + +struct palmas_platform_data { + int gpio_base; + + /* bit value to be loaded to the POWER_CTRL register */ + u8 power_ctrl; + + /* + * boolean to select if we want to configure muxing here + * then the two value to load into the registers if true + */ + int mux_from_pdata; + u8 pad1, pad2; + + struct palmas_pmic_platform_data *pmic_pdata; +}; + +/* Define the palmas IRQ numbers */ +enum palmas_irqs { + /* INT1 registers */ + PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, + PALMAS_PWRON_IRQ, + PALMAS_LONG_PRESS_KEY_IRQ, + PALMAS_RPWRON_IRQ, + PALMAS_PWRDOWN_IRQ, + PALMAS_HOTDIE_IRQ, + PALMAS_VSYS_MON_IRQ, + PALMAS_VBAT_MON_IRQ, + /* INT2 registers */ + PALMAS_RTC_ALARM_IRQ, + PALMAS_RTC_TIMER_IRQ, + PALMAS_WDT_IRQ, + PALMAS_BATREMOVAL_IRQ, + PALMAS_RESET_IN_IRQ, + PALMAS_FBI_BB_IRQ, + PALMAS_SHORT_IRQ, + PALMAS_VAC_ACOK_IRQ, + /* INT3 registers */ + PALMAS_GPADC_AUTO_0_IRQ, + PALMAS_GPADC_AUTO_1_IRQ, + PALMAS_GPADC_EOC_SW_IRQ, + PALMAS_GPADC_EOC_RT_IRQ, + PALMAS_ID_OTG_IRQ, + PALMAS_ID_IRQ, + PALMAS_VBUS_OTG_IRQ, + PALMAS_VBUS_IRQ, + /* INT4 registers */ + PALMAS_GPIO_0_IRQ, + PALMAS_GPIO_1_IRQ, + PALMAS_GPIO_2_IRQ, + PALMAS_GPIO_3_IRQ, + PALMAS_GPIO_4_IRQ, + PALMAS_GPIO_5_IRQ, + PALMAS_GPIO_6_IRQ, + PALMAS_GPIO_7_IRQ, + /* Total Number IRQs */ + PALMAS_NUM_IRQ, +}; + +enum palmas_regulators { + /* SMPS regulators */ + PALMAS_REG_SMPS12, + PALMAS_REG_SMPS123, + PALMAS_REG_SMPS3, + PALMAS_REG_SMPS45, + PALMAS_REG_SMPS457, + PALMAS_REG_SMPS6, + PALMAS_REG_SMPS7, + PALMAS_REG_SMPS8, + PALMAS_REG_SMPS9, + PALMAS_REG_SMPS10, + /* LDO regulators */ + PALMAS_REG_LDO1, + PALMAS_REG_LDO2, + PALMAS_REG_LDO3, + PALMAS_REG_LDO4, + PALMAS_REG_LDO5, + PALMAS_REG_LDO6, + PALMAS_REG_LDO7, + PALMAS_REG_LDO8, + PALMAS_REG_LDO9, + PALMAS_REG_LDOLN, + PALMAS_REG_LDOUSB, + /* Total number of regulators */ + PALMAS_NUM_REGS, +}; + +struct palmas_pmic { + struct palmas *palmas; + struct device *dev; + struct regulator_desc desc[PALMAS_NUM_REGS]; + struct regulator_dev *rdev[PALMAS_NUM_REGS]; + struct mutex mutex; + + int smps123; + int smps457; + + int range[PALMAS_REG_SMPS10]; +}; + +/* defines so we can store the mux settings */ +#define PALMAS_GPIO_0_MUXED (1 << 0) +#define PALMAS_GPIO_1_MUXED (1 << 1) +#define PALMAS_GPIO_2_MUXED (1 << 2) +#define PALMAS_GPIO_3_MUXED (1 << 3) +#define PALMAS_GPIO_4_MUXED (1 << 4) +#define PALMAS_GPIO_5_MUXED (1 << 5) +#define PALMAS_GPIO_6_MUXED (1 << 6) +#define PALMAS_GPIO_7_MUXED (1 << 7) + +#define PALMAS_LED1_MUXED (1 << 0) +#define PALMAS_LED2_MUXED (1 << 1) + +#define PALMAS_PWM1_MUXED (1 << 0) +#define PALMAS_PWM2_MUXED (1 << 1) + +/* helper macro to get correct slave number */ +#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) +#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) + +/* Base addresses of IP blocks in Palmas */ +#define PALMAS_SMPS_DVS_BASE 0x20 +#define PALMAS_RTC_BASE 0x100 +#define PALMAS_VALIDITY_BASE 0x118 +#define PALMAS_SMPS_BASE 0x120 +#define PALMAS_LDO_BASE 0x150 +#define PALMAS_DVFS_BASE 0x180 +#define PALMAS_PMU_CONTROL_BASE 0x1A0 +#define PALMAS_RESOURCE_BASE 0x1D4 +#define PALMAS_PU_PD_OD_BASE 0x1F4 +#define PALMAS_LED_BASE 0x200 +#define PALMAS_INTERRUPT_BASE 0x210 +#define PALMAS_USB_OTG_BASE 0x250 +#define PALMAS_VIBRATOR_BASE 0x270 +#define PALMAS_GPIO_BASE 0x280 +#define PALMAS_USB_BASE 0x290 +#define PALMAS_GPADC_BASE 0x2C0 +#define PALMAS_TRIM_GPADC_BASE 0x3CD + +/* Registers for function RTC */ +#define PALMAS_SECONDS_REG 0x0 +#define PALMAS_MINUTES_REG 0x1 +#define PALMAS_HOURS_REG 0x2 +#define PALMAS_DAYS_REG 0x3 +#define PALMAS_MONTHS_REG 0x4 +#define PALMAS_YEARS_REG 0x5 +#define PALMAS_WEEKS_REG 0x6 +#define PALMAS_ALARM_SECONDS_REG 0x8 +#define PALMAS_ALARM_MINUTES_REG 0x9 +#define PALMAS_ALARM_HOURS_REG 0xA +#define PALMAS_ALARM_DAYS_REG 0xB +#define PALMAS_ALARM_MONTHS_REG 0xC +#define PALMAS_ALARM_YEARS_REG 0xD +#define PALMAS_RTC_CTRL_REG 0x10 +#define PALMAS_RTC_STATUS_REG 0x11 +#define PALMAS_RTC_INTERRUPTS_REG 0x12 +#define PALMAS_RTC_COMP_LSB_REG 0x13 +#define PALMAS_RTC_COMP_MSB_REG 0x14 +#define PALMAS_RTC_RES_PROG_REG 0x15 +#define PALMAS_RTC_RESET_STATUS_REG 0x16 + +/* Bit definitions for SECONDS_REG */ +#define PALMAS_SECONDS_REG_SEC1_MASK 0x70 +#define PALMAS_SECONDS_REG_SEC1_SHIFT 4 +#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f +#define PALMAS_SECONDS_REG_SEC0_SHIFT 0 + +/* Bit definitions for MINUTES_REG */ +#define PALMAS_MINUTES_REG_MIN1_MASK 0x70 +#define PALMAS_MINUTES_REG_MIN1_SHIFT 4 +#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f +#define PALMAS_MINUTES_REG_MIN0_SHIFT 0 + +/* Bit definitions for HOURS_REG */ +#define PALMAS_HOURS_REG_PM_NAM 0x80 +#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 +#define PALMAS_HOURS_REG_HOUR1_MASK 0x30 +#define PALMAS_HOURS_REG_HOUR1_SHIFT 4 +#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f +#define PALMAS_HOURS_REG_HOUR0_SHIFT 0 + +/* Bit definitions for DAYS_REG */ +#define PALMAS_DAYS_REG_DAY1_MASK 0x30 +#define PALMAS_DAYS_REG_DAY1_SHIFT 4 +#define PALMAS_DAYS_REG_DAY0_MASK 0x0f +#define PALMAS_DAYS_REG_DAY0_SHIFT 0 + +/* Bit definitions for MONTHS_REG */ +#define PALMAS_MONTHS_REG_MONTH1 0x10 +#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 +#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f +#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 + +/* Bit definitions for YEARS_REG */ +#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 +#define PALMAS_YEARS_REG_YEAR1_SHIFT 4 +#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f +#define PALMAS_YEARS_REG_YEAR0_SHIFT 0 + +/* Bit definitions for WEEKS_REG */ +#define PALMAS_WEEKS_REG_WEEK_MASK 0x07 +#define PALMAS_WEEKS_REG_WEEK_SHIFT 0 + +/* Bit definitions for ALARM_SECONDS_REG */ +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 + +/* Bit definitions for ALARM_MINUTES_REG */ +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 + +/* Bit definitions for ALARM_HOURS_REG */ +#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 +#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 + +/* Bit definitions for ALARM_DAYS_REG */ +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 + +/* Bit definitions for ALARM_MONTHS_REG */ +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 + +/* Bit definitions for ALARM_YEARS_REG */ +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 + +/* Bit definitions for RTC_CTRL_REG */ +#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 +#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 +#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 +#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 +#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 +#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 +#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 +#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 +#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 +#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 +#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 +#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 +#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 +#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 +#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 +#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 + +/* Bit definitions for RTC_STATUS_REG */ +#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 +#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 +#define PALMAS_RTC_STATUS_REG_ALARM 0x40 +#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 +#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 +#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 +#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 +#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 +#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 +#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 +#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 +#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 +#define PALMAS_RTC_STATUS_REG_RUN 0x02 +#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 + +/* Bit definitions for RTC_INTERRUPTS_REG */ +#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 +#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 +#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 +#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 +#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 +#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 +#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 +#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 + +/* Bit definitions for RTC_COMP_LSB_REG */ +#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff +#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 + +/* Bit definitions for RTC_COMP_MSB_REG */ +#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff +#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 + +/* Bit definitions for RTC_RES_PROG_REG */ +#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f +#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 + +/* Bit definitions for RTC_RESET_STATUS_REG */ +#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 +#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 + +/* Registers for function BACKUP */ +#define PALMAS_BACKUP0 0x0 +#define PALMAS_BACKUP1 0x1 +#define PALMAS_BACKUP2 0x2 +#define PALMAS_BACKUP3 0x3 +#define PALMAS_BACKUP4 0x4 +#define PALMAS_BACKUP5 0x5 +#define PALMAS_BACKUP6 0x6 +#define PALMAS_BACKUP7 0x7 + +/* Bit definitions for BACKUP0 */ +#define PALMAS_BACKUP0_BACKUP_MASK 0xff +#define PALMAS_BACKUP0_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP1 */ +#define PALMAS_BACKUP1_BACKUP_MASK 0xff +#define PALMAS_BACKUP1_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP2 */ +#define PALMAS_BACKUP2_BACKUP_MASK 0xff +#define PALMAS_BACKUP2_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP3 */ +#define PALMAS_BACKUP3_BACKUP_MASK 0xff +#define PALMAS_BACKUP3_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP4 */ +#define PALMAS_BACKUP4_BACKUP_MASK 0xff +#define PALMAS_BACKUP4_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP5 */ +#define PALMAS_BACKUP5_BACKUP_MASK 0xff +#define PALMAS_BACKUP5_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP6 */ +#define PALMAS_BACKUP6_BACKUP_MASK 0xff +#define PALMAS_BACKUP6_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP7 */ +#define PALMAS_BACKUP7_BACKUP_MASK 0xff +#define PALMAS_BACKUP7_BACKUP_SHIFT 0 + +/* Registers for function SMPS */ +#define PALMAS_SMPS12_CTRL 0x0 +#define PALMAS_SMPS12_TSTEP 0x1 +#define PALMAS_SMPS12_FORCE 0x2 +#define PALMAS_SMPS12_VOLTAGE 0x3 +#define PALMAS_SMPS3_CTRL 0x4 +#define PALMAS_SMPS3_VOLTAGE 0x7 +#define PALMAS_SMPS45_CTRL 0x8 +#define PALMAS_SMPS45_TSTEP 0x9 +#define PALMAS_SMPS45_FORCE 0xA +#define PALMAS_SMPS45_VOLTAGE 0xB +#define PALMAS_SMPS6_CTRL 0xC +#define PALMAS_SMPS6_TSTEP 0xD +#define PALMAS_SMPS6_FORCE 0xE +#define PALMAS_SMPS6_VOLTAGE 0xF +#define PALMAS_SMPS7_CTRL 0x10 +#define PALMAS_SMPS7_VOLTAGE 0x13 +#define PALMAS_SMPS8_CTRL 0x14 +#define PALMAS_SMPS8_TSTEP 0x15 +#define PALMAS_SMPS8_FORCE 0x16 +#define PALMAS_SMPS8_VOLTAGE 0x17 +#define PALMAS_SMPS9_CTRL 0x18 +#define PALMAS_SMPS9_VOLTAGE 0x1B +#define PALMAS_SMPS10_CTRL 0x1C +#define PALMAS_SMPS10_STATUS 0x1F +#define PALMAS_SMPS_CTRL 0x24 +#define PALMAS_SMPS_PD_CTRL 0x25 +#define PALMAS_SMPS_DITHER_EN 0x26 +#define PALMAS_SMPS_THERMAL_EN 0x27 +#define PALMAS_SMPS_THERMAL_STATUS 0x28 +#define PALMAS_SMPS_SHORT_STATUS 0x29 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A +#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B +#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C + +/* Bit definitions for SMPS12_CTRL */ +#define PALMAS_SMPS12_CTRL_WR_S 0x80 +#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 +#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS12_TSTEP */ +#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 +#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 + +/* Bit definitions for SMPS12_FORCE */ +#define PALMAS_SMPS12_FORCE_CMD 0x80 +#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 +#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f +#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS12_VOLTAGE */ +#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS3_CTRL */ +#define PALMAS_SMPS3_CTRL_WR_S 0x80 +#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS3_VOLTAGE */ +#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS45_CTRL */ +#define PALMAS_SMPS45_CTRL_WR_S 0x80 +#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 +#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS45_TSTEP */ +#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 +#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 + +/* Bit definitions for SMPS45_FORCE */ +#define PALMAS_SMPS45_FORCE_CMD 0x80 +#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 +#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f +#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS45_VOLTAGE */ +#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS6_CTRL */ +#define PALMAS_SMPS6_CTRL_WR_S 0x80 +#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 +#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS6_TSTEP */ +#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 +#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 + +/* Bit definitions for SMPS6_FORCE */ +#define PALMAS_SMPS6_FORCE_CMD 0x80 +#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 +#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f +#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS6_VOLTAGE */ +#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS7_CTRL */ +#define PALMAS_SMPS7_CTRL_WR_S 0x80 +#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS7_VOLTAGE */ +#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS8_CTRL */ +#define PALMAS_SMPS8_CTRL_WR_S 0x80 +#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 +#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS8_TSTEP */ +#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 +#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 + +/* Bit definitions for SMPS8_FORCE */ +#define PALMAS_SMPS8_FORCE_CMD 0x80 +#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 +#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f +#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS8_VOLTAGE */ +#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS9_CTRL */ +#define PALMAS_SMPS9_CTRL_WR_S 0x80 +#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS9_VOLTAGE */ +#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS10_CTRL */ +#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 +#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 +#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f +#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS10_STATUS */ +#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f +#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 + +/* Bit definitions for SMPS_CTRL */ +#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 +#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 +#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 +#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 +#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c +#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 +#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 +#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 + +/* Bit definitions for SMPS_PD_CTRL */ +#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 +#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 +#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 +#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 +#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 +#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 +#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 +#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 +#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 +#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 +#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 +#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 +#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 +#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 + +/* Bit definitions for SMPS_THERMAL_EN */ +#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 +#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 +#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 +#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 +#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 +#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 +#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 +#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 +#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 +#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 + +/* Bit definitions for SMPS_THERMAL_STATUS */ +#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 + +/* Bit definitions for SMPS_SHORT_STATUS */ +#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 +#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 +#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 +#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 +#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 +#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 +#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 +#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 +#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 +#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 +#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 +#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 +#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 +#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 +#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 +#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 + +/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 + +/* Bit definitions for SMPS_POWERGOOD_MASK1 */ +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 + +/* Bit definitions for SMPS_POWERGOOD_MASK2 */ +#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 +#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 +#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 +#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 +#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 +#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 +#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 +#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 + +/* Registers for function LDO */ +#define PALMAS_LDO1_CTRL 0x0 +#define PALMAS_LDO1_VOLTAGE 0x1 +#define PALMAS_LDO2_CTRL 0x2 +#define PALMAS_LDO2_VOLTAGE 0x3 +#define PALMAS_LDO3_CTRL 0x4 +#define PALMAS_LDO3_VOLTAGE 0x5 +#define PALMAS_LDO4_CTRL 0x6 +#define PALMAS_LDO4_VOLTAGE 0x7 +#define PALMAS_LDO5_CTRL 0x8 +#define PALMAS_LDO5_VOLTAGE 0x9 +#define PALMAS_LDO6_CTRL 0xA +#define PALMAS_LDO6_VOLTAGE 0xB +#define PALMAS_LDO7_CTRL 0xC +#define PALMAS_LDO7_VOLTAGE 0xD +#define PALMAS_LDO8_CTRL 0xE +#define PALMAS_LDO8_VOLTAGE 0xF +#define PALMAS_LDO9_CTRL 0x10 +#define PALMAS_LDO9_VOLTAGE 0x11 +#define PALMAS_LDOLN_CTRL 0x12 +#define PALMAS_LDOLN_VOLTAGE 0x13 +#define PALMAS_LDOUSB_CTRL 0x14 +#define PALMAS_LDOUSB_VOLTAGE 0x15 +#define PALMAS_LDO_CTRL 0x1A +#define PALMAS_LDO_PD_CTRL1 0x1B +#define PALMAS_LDO_PD_CTRL2 0x1C +#define PALMAS_LDO_SHORT_STATUS1 0x1D +#define PALMAS_LDO_SHORT_STATUS2 0x1E + +/* Bit definitions for LDO1_CTRL */ +#define PALMAS_LDO1_CTRL_WR_S 0x80 +#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO1_CTRL_STATUS 0x10 +#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO1_VOLTAGE */ +#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO2_CTRL */ +#define PALMAS_LDO2_CTRL_WR_S 0x80 +#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO2_CTRL_STATUS 0x10 +#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO2_VOLTAGE */ +#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO3_CTRL */ +#define PALMAS_LDO3_CTRL_WR_S 0x80 +#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO3_CTRL_STATUS 0x10 +#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO3_VOLTAGE */ +#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO4_CTRL */ +#define PALMAS_LDO4_CTRL_WR_S 0x80 +#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO4_CTRL_STATUS 0x10 +#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO4_VOLTAGE */ +#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO5_CTRL */ +#define PALMAS_LDO5_CTRL_WR_S 0x80 +#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO5_CTRL_STATUS 0x10 +#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO5_VOLTAGE */ +#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO6_CTRL */ +#define PALMAS_LDO6_CTRL_WR_S 0x80 +#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 +#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 +#define PALMAS_LDO6_CTRL_STATUS 0x10 +#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO6_VOLTAGE */ +#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO7_CTRL */ +#define PALMAS_LDO7_CTRL_WR_S 0x80 +#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO7_CTRL_STATUS 0x10 +#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO7_VOLTAGE */ +#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO8_CTRL */ +#define PALMAS_LDO8_CTRL_WR_S 0x80 +#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 +#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 +#define PALMAS_LDO8_CTRL_STATUS 0x10 +#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO8_VOLTAGE */ +#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO9_CTRL */ +#define PALMAS_LDO9_CTRL_WR_S 0x80 +#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 +#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 +#define PALMAS_LDO9_CTRL_STATUS 0x10 +#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO9_VOLTAGE */ +#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDOLN_CTRL */ +#define PALMAS_LDOLN_CTRL_WR_S 0x80 +#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDOLN_CTRL_STATUS 0x10 +#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDOLN_VOLTAGE */ +#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDOUSB_CTRL */ +#define PALMAS_LDOUSB_CTRL_WR_S 0x80 +#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDOUSB_CTRL_STATUS 0x10 +#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDOUSB_VOLTAGE */ +#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO_CTRL */ +#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 +#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 + +/* Bit definitions for LDO_PD_CTRL1 */ +#define PALMAS_LDO_PD_CTRL1_LDO8 0x80 +#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 +#define PALMAS_LDO_PD_CTRL1_LDO7 0x40 +#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 +#define PALMAS_LDO_PD_CTRL1_LDO6 0x20 +#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 +#define PALMAS_LDO_PD_CTRL1_LDO5 0x10 +#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 +#define PALMAS_LDO_PD_CTRL1_LDO4 0x08 +#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 +#define PALMAS_LDO_PD_CTRL1_LDO3 0x04 +#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 +#define PALMAS_LDO_PD_CTRL1_LDO2 0x02 +#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 +#define PALMAS_LDO_PD_CTRL1_LDO1 0x01 +#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 + +/* Bit definitions for LDO_PD_CTRL2 */ +#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 +#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 +#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 +#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 +#define PALMAS_LDO_PD_CTRL2_LDO9 0x01 +#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 + +/* Bit definitions for LDO_SHORT_STATUS1 */ +#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 +#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 +#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 +#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 +#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 +#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 +#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 +#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 +#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 +#define PALMAS_LDO_SHORT_STATUS1_L |