Merge tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Pin control bulk changes for the v4.11 kernel cycle.

  Core changes:

   - Switch the generic pin config argument from 16 to 24 bits, only use
     8 bits for the configuration type. We might need to encode more
     information about a certain setting than we need to encode
     different generic settings.

   - Add a cross-talk API to the pin control GPIO back-end, utilizing
     pinctrl_gpio_set_config() from GPIO drivers that want to set up a
     certain pin configuration in the back-end.

     This also includes the .set_config() refactoring of the GPIO chips,
     so that they pass a generic configuration for things like
     debouncing and single ended (typically open drain). This change has
     also been merged in an immutable branch to the GPIO tree.

   - Take hogs with a delayed work, so that we finalize probing a pin
     controller before trying to get any hogs.

   - For pin controllers putting all group and function definitions into
     the device tree, we now have generic code to deal with this and it
     is used in two drivers so far.

   - Simplifications of the pin request conflict check.

   - Make dt_free_map() optional.

  Updates to drivers:

   - pinctrl-single now use the generic helpers to generate dynamic
     group and function tables from the device tree.

   - Texas Instruments IOdelay configuration driver add-on to
     pinctrl-single.

   - i.MX: use radix trees to store groups and functions, use the new
     generic group and function helpers to manage them.

   - Intel: add support for hardware debouncing and 1K pull-down. New
     subdriver for the Gemini Lake SoC.

   - Renesas SH-PFC: drive strength and bias support, CAN bus muxing,
     MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791.

   - Aspeed: use syscon cross-dependencies to set up related bits in the
     LPC host controller and display controller.

   - Aspeed: finalize G4 and G5 support. Fix mux configuration on GPIOs.
     Add banks Y, Z, AA, AB and AC.

   - AMD: support additional GPIO.

   - STM32: set this controller to strict muxing mode. STM32H743 MCU
     support.

   - Allwinner sunxi: deep simplifications on how to support subvariants
     of SoCs without adding to much SoC-specific data for each
     subvariant, especially for sun5i variants. New driver for V3s SoCs.
     New driver for the H5 SoC. Support A31/A31s variants with the new
     variant framework.

   - Mvebu: simplifications to use a MMIO and regmap abstraction. New
     subdrivers for the 98DX3236, 98DX5241 SoCs.

   - Samsung Exynos: delete Exynos4415 support. Add crosstalk to the SoC
     driver to access regmaps. Add infrastructure for pin-bank retention
     control. Clean out the pin retention control from
     arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly in
     the Samsung pin control driver(s).

   - Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin.

   - Qualcomm: use raw spinlock variants: this makes the qualcomm driver
     realtime-safe"

* tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (111 commits)
  pinctrl: samsung: Fix return value check in samsung_pinctrl_get_soc_data()
  pinctrl: intel: unlock on error in intel_config_set_pull()
  pinctrl: berlin: make bool drivers explicitly non-modular
  pinctrl: spear: make bool drivers explicitly non-modular
  pinctrl: mvebu: make bool drivers explicitly non-modular
  pinctrl: sunxi: make sun5i explicitly non-modular
  pinctrl: sunxi: Remove stray printk call in sun5i driver's probe function
  pinctrl: samsung: mark PM functions as __maybe_unused
  pinctrl: sunxi: Remove redundant A31s pinctrl driver
  pinctrl: sunxi: Support A31/A31s with pinctrl variants
  pinctrl: Amend bindings for STM32 pinctrl
  pinctrl: Add STM32 pinctrl driver DT bindings
  pinctrl: stm32: Add STM32H743 MCU support
  include: dt-bindings: Add STM32H7 pinctrl DT defines
  gpio: aspeed: Remove dependence on GPIOF_* macros
  pinctrl: stm32: fix bad location of gpiochip_lock_as_irq
  drivers: pinctrl: add driver for Allwinner H5 SoC
  pinctrl: intel: Add Intel Gemini Lake pin controller support
  pinctrl: intel: Add support for 1k additional pull-down
  pinctrl: intel: Add support for hardware debouncer
  ...

1 files changed, 1612 insertions, 0 deletions

diff --git a/include/dt-bindings/pinctrl/stm32h7-pinfunc.h b/include/dt-bindings/pinctrl/stm32h7-pinfunc.h
new file mode 100644
index 000000000000..cb673b5e8e1e
--- /dev/null
+++ b/include/dt-bindings/pinctrl/stm32h7-pinfunc.h
@@ -0,0 +1,1612 @@
+#ifndef _DT_BINDINGS_STM32H7_PINFUNC_H
+#define _DT_BINDINGS_STM32H7_PINFUNC_H
+
+#define STM32H7_PA0_FUNC_GPIO 0x0
+#define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
+#define STM32H7_PA0_FUNC_TIM5_CH1 0x3
+#define STM32H7_PA0_FUNC_TIM8_ETR 0x4
+#define STM32H7_PA0_FUNC_TIM15_BKIN 0x5
+#define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8
+#define STM32H7_PA0_FUNC_UART4_TX 0x9
+#define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa
+#define STM32H7_PA0_FUNC_SAI2_SD_B 0xb
+#define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc
+#define STM32H7_PA0_FUNC_EVENTOUT 0x10
+#define STM32H7_PA0_FUNC_ANALOG 0x11
+
+#define STM32H7_PA1_FUNC_GPIO 0x100
+#define STM32H7_PA1_FUNC_TIM2_CH2 0x102
+#define STM32H7_PA1_FUNC_TIM5_CH2 0x103
+#define STM32H7_PA1_FUNC_LPTIM3_OUT 0x104
+#define STM32H7_PA1_FUNC_TIM15_CH1N 0x105
+#define STM32H7_PA1_FUNC_USART2_RTS 0x108
+#define STM32H7_PA1_FUNC_UART4_RX 0x109
+#define STM32H7_PA1_FUNC_QUADSPI_BK1_IO3 0x10a
+#define STM32H7_PA1_FUNC_SAI2_MCK_B 0x10b
+#define STM32H7_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c
+#define STM32H7_PA1_FUNC_LCD_R2 0x10f
+#define STM32H7_PA1_FUNC_EVENTOUT 0x110
+#define STM32H7_PA1_FUNC_ANALOG 0x111
+
+#define STM32H7_PA2_FUNC_GPIO 0x200
+#define STM32H7_PA2_FUNC_TIM2_CH3 0x202
+#define STM32H7_PA2_FUNC_TIM5_CH3 0x203
+#define STM32H7_PA2_FUNC_LPTIM4_OUT 0x204
+#define STM32H7_PA2_FUNC_TIM15_CH1 0x205
+#define STM32H7_PA2_FUNC_USART2_TX 0x208
+#define STM32H7_PA2_FUNC_SAI2_SCK_B 0x209
+#define STM32H7_PA2_FUNC_ETH_MDIO 0x20c
+#define STM32H7_PA2_FUNC_MDIOS_MDIO 0x20d
+#define STM32H7_PA2_FUNC_LCD_R1 0x20f
+#define STM32H7_PA2_FUNC_EVENTOUT 0x210
+#define STM32H7_PA2_FUNC_ANALOG 0x211
+
+#define STM32H7_PA3_FUNC_GPIO 0x300
+#define STM32H7_PA3_FUNC_TIM2_CH4 0x302
+#define STM32H7_PA3_FUNC_TIM5_CH4 0x303
+#define STM32H7_PA3_FUNC_LPTIM5_OUT 0x304
+#define STM32H7_PA3_FUNC_TIM15_CH2 0x305
+#define STM32H7_PA3_FUNC_USART2_RX 0x308
+#define STM32H7_PA3_FUNC_LCD_B2 0x30a
+#define STM32H7_PA3_FUNC_OTG_HS_ULPI_D0 0x30b
+#define STM32H7_PA3_FUNC_ETH_MII_COL 0x30c
+#define STM32H7_PA3_FUNC_LCD_B5 0x30f
+#define STM32H7_PA3_FUNC_EVENTOUT 0x310
+#define STM32H7_PA3_FUNC_ANALOG 0x311
+
+#define STM32H7_PA4_FUNC_GPIO 0x400
+#define STM32H7_PA4_FUNC_TIM5_ETR 0x403
+#define STM32H7_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406
+#define STM32H7_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407
+#define STM32H7_PA4_FUNC_USART2_CK 0x408
+#define STM32H7_PA4_FUNC_SPI6_NSS 0x409
+#define STM32H7_PA4_FUNC_OTG_HS_SOF 0x40d
+#define STM32H7_PA4_FUNC_DCMI_HSYNC 0x40e
+#define STM32H7_PA4_FUNC_LCD_VSYNC 0x40f
+#define STM32H7_PA4_FUNC_EVENTOUT 0x410
+#define STM32H7_PA4_FUNC_ANALOG 0x411
+
+#define STM32H7_PA5_FUNC_GPIO 0x500
+#define STM32H7_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502
+#define STM32H7_PA5_FUNC_TIM8_CH1N 0x504
+#define STM32H7_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506
+#define STM32H7_PA5_FUNC_SPI6_SCK 0x509
+#define STM32H7_PA5_FUNC_OTG_HS_ULPI_CK 0x50b
+#define STM32H7_PA5_FUNC_LCD_R4 0x50f
+#define STM32H7_PA5_FUNC_EVENTOUT 0x510
+#define STM32H7_PA5_FUNC_ANALOG 0x511
+
+#define STM32H7_PA6_FUNC_GPIO 0x600
+#define STM32H7_PA6_FUNC_TIM1_BKIN 0x602
+#define STM32H7_PA6_FUNC_TIM3_CH1 0x603
+#define STM32H7_PA6_FUNC_TIM8_BKIN 0x604
+#define STM32H7_PA6_FUNC_SPI1_MISO_I2S1_SDI 0x606
+#define STM32H7_PA6_FUNC_SPI6_MISO 0x609
+#define STM32H7_PA6_FUNC_TIM13_CH1 0x60a
+#define STM32H7_PA6_FUNC_TIM8_BKIN_COMP12 0x60b
+#define STM32H7_PA6_FUNC_MDIOS_MDC 0x60c
+#define STM32H7_PA6_FUNC_TIM1_BKIN_COMP12 0x60d
+#define STM32H7_PA6_FUNC_DCMI_PIXCLK 0x60e
+#define STM32H7_PA6_FUNC_LCD_G2 0x60f
+#define STM32H7_PA6_FUNC_EVENTOUT 0x610
+#define STM32H7_PA6_FUNC_ANALOG 0x611
+
+#define STM32H7_PA7_FUNC_GPIO 0x700
+#define STM32H7_PA7_FUNC_TIM1_CH1N 0x702
+#define STM32H7_PA7_FUNC_TIM3_CH2 0x703
+#define STM32H7_PA7_FUNC_TIM8_CH1N 0x704
+#define STM32H7_PA7_FUNC_SPI1_MOSI_I2S1_SDO 0x706
+#define STM32H7_PA7_FUNC_SPI6_MOSI 0x709
+#define STM32H7_PA7_FUNC_TIM14_CH1 0x70a
+#define STM32H7_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c
+#define STM32H7_PA7_FUNC_FMC_SDNWE 0x70d
+#define STM32H7_PA7_FUNC_EVENTOUT 0x710
+#define STM32H7_PA7_FUNC_ANALOG 0x711
+
+#define STM32H7_PA8_FUNC_GPIO 0x800
+#define STM32H7_PA8_FUNC_MCO1 0x801
+#define STM32H7_PA8_FUNC_TIM1_CH1 0x802
+#define STM32H7_PA8_FUNC_HRTIM_CHB2 0x803
+#define STM32H7_PA8_FUNC_TIM8_BKIN2 0x804
+#define STM32H7_PA8_FUNC_I2C3_SCL 0x805
+#define STM32H7_PA8_FUNC_USART1_CK 0x808
+#define STM32H7_PA8_FUNC_OTG_FS_SOF 0x80b
+#define STM32H7_PA8_FUNC_UART7_RX 0x80c
+#define STM32H7_PA8_FUNC_TIM8_BKIN2_COMP12 0x80d
+#define STM32H7_PA8_FUNC_LCD_B3 0x80e
+#define STM32H7_PA8_FUNC_LCD_R6 0x80f
+#define STM32H7_PA8_FUNC_EVENTOUT 0x810
+#define STM32H7_PA8_FUNC_ANALOG 0x811
+
+#define STM32H7_PA9_FUNC_GPIO 0x900
+#define STM32H7_PA9_FUNC_TIM1_CH2 0x902
+#define STM32H7_PA9_FUNC_HRTIM_CHC1 0x903
+#define STM32H7_PA9_FUNC_LPUART1_TX 0x904
+#define STM32H7_PA9_FUNC_I2C3_SMBA 0x905
+#define STM32H7_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906
+#define STM32H7_PA9_FUNC_USART1_TX 0x908
+#define STM32H7_PA9_FUNC_CAN1_RXFD 0x90a
+#define STM32H7_PA9_FUNC_ETH_TX_ER 0x90c
+#define STM32H7_PA9_FUNC_DCMI_D0 0x90e
+#define STM32H7_PA9_FUNC_LCD_R5 0x90f
+#define STM32H7_PA9_FUNC_EVENTOUT 0x910
+#define STM32H7_PA9_FUNC_ANALOG 0x911
+
+#define STM32H7_PA10_FUNC_GPIO 0xa00
+#define STM32H7_PA10_FUNC_TIM1_CH3 0xa02
+#define STM32H7_PA10_FUNC_HRTIM_CHC2 0xa03
+#define STM32H7_PA10_FUNC_LPUART1_RX 0xa04
+#define STM32H7_PA10_FUNC_USART1_RX 0xa08
+#define STM32H7_PA10_FUNC_CAN1_TXFD 0xa0a
+#define STM32H7_PA10_FUNC_OTG_FS_ID 0xa0b
+#define STM32H7_PA10_FUNC_MDIOS_MDIO 0xa0c
+#define STM32H7_PA10_FUNC_LCD_B4 0xa0d
+#define STM32H7_PA10_FUNC_DCMI_D1 0xa0e
+#define STM32H7_PA10_FUNC_LCD_B1 0xa0f
+#define STM32H7_PA10_FUNC_EVENTOUT 0xa10
+#define STM32H7_PA10_FUNC_ANALOG 0xa11
+
+#define STM32H7_PA11_FUNC_GPIO 0xb00
+#define STM32H7_PA11_FUNC_TIM1_CH4 0xb02
+#define STM32H7_PA11_FUNC_HRTIM_CHD1 0xb03
+#define STM32H7_PA11_FUNC_LPUART1_CTS 0xb04
+#define STM32H7_PA11_FUNC_SPI2_NSS_I2S2_WS 0xb06
+#define STM32H7_PA11_FUNC_UART4_RX 0xb07
+#define STM32H7_PA11_FUNC_USART1_CTS_NSS 0xb08
+#define STM32H7_PA11_FUNC_CAN1_RX 0xb0a
+#define STM32H7_PA11_FUNC_OTG_FS_DM 0xb0b
+#define STM32H7_PA11_FUNC_LCD_R4 0xb0f
+#define STM32H7_PA11_FUNC_EVENTOUT 0xb10
+#define STM32H7_PA11_FUNC_ANALOG 0xb11
+
+#define STM32H7_PA12_FUNC_GPIO 0xc00
+#define STM32H7_PA12_FUNC_TIM1_ETR 0xc02
+#define STM32H7_PA12_FUNC_HRTIM_CHD2 0xc03
+#define STM32H7_PA12_FUNC_LPUART1_RTS 0xc04
+#define STM32H7_PA12_FUNC_SPI2_SCK_I2S2_CK 0xc06
+#define STM32H7_PA12_FUNC_UART4_TX 0xc07
+#define STM32H7_PA12_FUNC_USART1_RTS 0xc08
+#define STM32H7_PA12_FUNC_SAI2_FS_B 0xc09
+#define STM32H7_PA12_FUNC_CAN1_TX 0xc0a
+#define STM32H7_PA12_FUNC_OTG_FS_DP 0xc0b
+#define STM32H7_PA12_FUNC_LCD_R5 0xc0f
+#define STM32H7_PA12_FUNC_EVENTOUT 0xc10
+#define STM32H7_PA12_FUNC_ANALOG 0xc11
+
+#define STM32H7_PA13_FUNC_GPIO 0xd00
+#define STM32H7_PA13_FUNC_JTMS_SWDIO 0xd01
+#define STM32H7_PA13_FUNC_EVENTOUT 0xd10
+#define STM32H7_PA13_FUNC_ANALOG 0xd11
+
+#define STM32H7_PA14_FUNC_GPIO 0xe00
+#define STM32H7_PA14_FUNC_JTCK_SWCLK 0xe01
+#define STM32H7_PA14_FUNC_EVENTOUT 0xe10
+#define STM32H7_PA14_FUNC_ANALOG 0xe11
+
+#define STM32H7_PA15_FUNC_GPIO 0xf00
+#define STM32H7_PA15_FUNC_JTDI 0xf01
+#define STM32H7_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02
+#define STM32H7_PA15_FUNC_HRTIM_FLT1 0xf03
+#define STM32H7_PA15_FUNC_HDMI_CEC 0xf05
+#define STM32H7_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06
+#define STM32H7_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07
+#define STM32H7_PA15_FUNC_SPI6_NSS 0xf08
+#define STM32H7_PA15_FUNC_UART4_RTS 0xf09
+#define STM32H7_PA15_FUNC_UART7_TX 0xf0c
+#define STM32H7_PA15_FUNC_DSI_TE 0xf0e
+#define STM32H7_PA15_FUNC_EVENTOUT 0xf10
+#define STM32H7_PA15_FUNC_ANALOG 0xf11
+
+#define STM32H7_PB0_FUNC_GPIO 0x1000
+#define STM32H7_PB0_FUNC_TIM1_CH2N 0x1002
+#define STM32H7_PB0_FUNC_TIM3_CH3 0x1003
+#define STM32H7_PB0_FUNC_TIM8_CH2N 0x1004
+#define STM32H7_PB0_FUNC_DFSDM_CKOUT 0x1007
+#define STM32H7_PB0_FUNC_UART4_CTS 0x1009
+#define STM32H7_PB0_FUNC_LCD_R3 0x100a
+#define STM32H7_PB0_FUNC_OTG_HS_ULPI_D1 0x100b
+#define STM32H7_PB0_FUNC_ETH_MII_RXD2 0x100c
+#define STM32H7_PB0_FUNC_LCD_G1 0x100f
+#define STM32H7_PB0_FUNC_EVENTOUT 0x1010
+#define STM32H7_PB0_FUNC_ANALOG 0x1011
+
+#define STM32H7_PB1_FUNC_GPIO 0x1100
+#define STM32H7_PB1_FUNC_TIM1_CH3N 0x1102
+#define STM32H7_PB1_FUNC_TIM3_CH4 0x1103
+#define STM32H7_PB1_FUNC_TIM8_CH3N 0x1104
+#define STM32H7_PB1_FUNC_DFSDM_DATIN1 0x1107
+#define STM32H7_PB1_FUNC_LCD_R6 0x110a
+#define STM32H7_PB1_FUNC_OTG_HS_ULPI_D2 0x110b
+#define STM32H7_PB1_FUNC_ETH_MII_RXD3 0x110c
+#define STM32H7_PB1_FUNC_LCD_G0 0x110f
+#define STM32H7_PB1_FUNC_EVENTOUT 0x1110
+#define STM32H7_PB1_FUNC_ANALOG 0x1111
+
+#define STM32H7_PB2_FUNC_GPIO 0x1200
+#define STM32H7_PB2_FUNC_SAI1_D1 0x1203
+#define STM32H7_PB2_FUNC_DFSDM_CKIN1 0x1205
+#define STM32H7_PB2_FUNC_SAI1_SD_A 0x1207
+#define STM32H7_PB2_FUNC_SPI3_MOSI_I2S3_SDO 0x1208
+#define STM32H7_PB2_FUNC_SAI4_SD_A 0x1209
+#define STM32H7_PB2_FUNC_QUADSPI_CLK 0x120a
+#define STM32H7_PB2_FUNC_SAI4_D1 0x120b
+#define STM32H7_PB2_FUNC_ETH_TX_ER 0x120c
+#define STM32H7_PB2_FUNC_EVENTOUT 0x1210
+#define STM32H7_PB2_FUNC_ANALOG 0x1211
+
+#define STM32H7_PB3_FUNC_GPIO 0x1300
+#define STM32H7_PB3_FUNC_JTDO_TRACESWO 0x1301
+#define STM32H7_PB3_FUNC_TIM2_CH2 0x1302
+#define STM32H7_PB3_FUNC_HRTIM_FLT4 0x1303
+#define STM32H7_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306
+#define STM32H7_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307
+#define STM32H7_PB3_FUNC_SPI6_SCK 0x1309
+#define STM32H7_PB3_FUNC_SDMMC2_D2 0x130a
+#define STM32H7_PB3_FUNC_UART7_RX 0x130c
+#define STM32H7_PB3_FUNC_EVENTOUT 0x1310
+#define STM32H7_PB3_FUNC_ANALOG 0x1311
+
+#define STM32H7_PB4_FUNC_GPIO 0x1400
+#define STM32H7_PB4_FUNC_NJTRST 0x1401
+#define STM32H7_PB4_FUNC_TIM16_BKIN 0x1402
+#define STM32H7_PB4_FUNC_TIM3_CH1 0x1403
+#define STM32H7_PB4_FUNC_HRTIM_EEV6 0x1404
+#define STM32H7_PB4_FUNC_SPI1_MISO_I2S1_SDI 0x1406
+#define STM32H7_PB4_FUNC_SPI3_MISO_I2S3_SDI 0x1407
+#define STM32H7_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408
+#define STM32H7_PB4_FUNC_SPI6_MISO 0x1409
+#define STM32H7_PB4_FUNC_SDMMC2_D3 0x140a
+#define STM32H7_PB4_FUNC_UART7_TX 0x140c
+#define STM32H7_PB4_FUNC_EVENTOUT 0x1410
+#define STM32H7_PB4_FUNC_ANALOG 0x1411
+
+#define STM32H7_PB5_FUNC_GPIO 0x1500
+#define STM32H7_PB5_FUNC_TIM17_BKIN 0x1502
+#define STM32H7_PB5_FUNC_TIM3_CH2 0x1503
+#define STM32H7_PB5_FUNC_HRTIM_EEV7 0x1504
+#define STM32H7_PB5_FUNC_I2C1_SMBA 0x1505
+#define STM32H7_PB5_FUNC_SPI1_MOSI_I2S1_SDO 0x1506
+#define STM32H7_PB5_FUNC_I2C4_SMBA 0x1507
+#define STM32H7_PB5_FUNC_SPI3_MOSI_I2S3_SDO 0x1508
+#define STM32H7_PB5_FUNC_SPI6_MOSI 0x1509
+#define STM32H7_PB5_FUNC_CAN2_RX 0x150a
+#define STM32H7_PB5_FUNC_OTG_HS_ULPI_D7 0x150b
+#define STM32H7_PB5_FUNC_ETH_PPS_OUT 0x150c
+#define STM32H7_PB5_FUNC_FMC_SDCKE1 0x150d
+#define STM32H7_PB5_FUNC_DCMI_D10 0x150e
+#define STM32H7_PB5_FUNC_UART5_RX 0x150f
+#define STM32H7_PB5_FUNC_EVENTOUT 0x1510
+#define STM32H7_PB5_FUNC_ANALOG 0x1511
+
+#define STM32H7_PB6_FUNC_GPIO 0x1600
+#define STM32H7_PB6_FUNC_TIM16_CH1N 0x1602
+#define STM32H7_PB6_FUNC_TIM4_CH1 0x1603
+#define STM32H7_PB6_FUNC_HRTIM_EEV8 0x1604
+#define STM32H7_PB6_FUNC_I2C1_SCL 0x1605
+#define STM32H7_PB6_FUNC_HDMI_CEC 0x1606
+#define STM32H7_PB6_FUNC_I2C4_SCL 0x1607
+#define STM32H7_PB6_FUNC_USART1_TX 0x1608
+#define STM32H7_PB6_FUNC_LPUART1_TX 0x1609
+#define STM32H7_PB6_FUNC_CAN2_TX 0x160a
+#define STM32H7_PB6_FUNC_QUADSPI_BK1_NCS 0x160b
+#define STM32H7_PB6_FUNC_DFSDM_DATIN5 0x160c
+#define STM32H7_PB6_FUNC_FMC_SDNE1 0x160d
+#define STM32H7_PB6_FUNC_DCMI_D5 0x160e
+#define STM32H7_PB6_FUNC_UART5_TX 0x160f
+#define STM32H7_PB6_FUNC_EVENTOUT 0x1610
+#define STM32H7_PB6_FUNC_ANALOG 0x1611
+
+#define STM32H7_PB7_FUNC_GPIO 0x1700
+#define STM32H7_PB7_FUNC_TIM17_CH1N 0x1702
+#define STM32H7_PB7_FUNC_TIM4_CH2 0x1703
+#define STM32H7_PB7_FUNC_HRTIM_EEV9 0x1704
+#define STM32H7_PB7_FUNC_I2C1_SDA 0x1705
+#define STM32H7_PB7_FUNC_I2C4_SDA 0x1707
+#define STM32H7_PB7_FUNC_USART1_RX 0x1708
+#define STM32H7_PB7_FUNC_LPUART1_RX 0x1709
+#define STM32H7_PB7_FUNC_CAN2_TXFD 0x170a
+#define STM32H7_PB7_FUNC_DFSDM_CKIN5 0x170c
+#define STM32H7_PB7_FUNC_FMC_NL 0x170d
+#define STM32H7_PB7_FUNC_DCMI_VSYNC 0x170e
+#define STM32H7_PB7_FUNC_EVENTOUT 0x1710
+#define STM32H7_PB7_FUNC_ANALOG 0x1711
+
+#define STM32H7_PB8_FUNC_GPIO 0x1800
+#define STM32H7_PB8_FUNC_TIM16_CH1 0x1802
+#define STM32H7_PB8_FUNC_TIM4_CH3 0x1803
+#define STM32H7_PB8_FUNC_DFSDM_CKIN7 0x1804
+#define STM32H7_PB8_FUNC_I2C1_SCL 0x1805
+#define STM32H7_PB8_FUNC_I2C4_SCL 0x1807
+#define STM32H7_PB8_FUNC_SDMMC1_CKIN 0x1808
+#define STM32H7_PB8_FUNC_UART4_RX 0x1809
+#define STM32H7_PB8_FUNC_CAN1_RX 0x180a
+#define STM32H7_PB8_FUNC_SDMMC2_D4 0x180b
+#define STM32H7_PB8_FUNC_ETH_MII_TXD3 0x180c
+#define STM32H7_PB8_FUNC_SDMMC1_D4 0x180d
+#define STM32H7_PB8_FUNC_DCMI_D6 0x180e
+#define STM32H7_PB8_FUNC_LCD_B6 0x180f
+#define STM32H7_PB8_FUNC_EVENTOUT 0x1810
+#define STM32H7_PB8_FUNC_ANALOG 0x1811
+
+#define STM32H7_PB9_FUNC_GPIO 0x1900
+#define STM32H7_PB9_FUNC_TIM17_CH1 0x1902
+#define STM32H7_PB9_FUNC_TIM4_CH4 0x1903
+#define STM32H7_PB9_FUNC_DFSDM_DATIN7 0x1904
+#define STM32H7_PB9_FUNC_I2C1_SDA 0x1905
+#define STM32H7_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906
+#define STM32H7_PB9_FUNC_I2C4_SDA 0x1907
+#define STM32H7_PB9_FUNC_SDMMC1_CDIR 0x1908
+#define STM32H7_PB9_FUNC_UART4_TX 0x1909
+#define STM32H7_PB9_FUNC_CAN1_TX 0x190a
+#define STM32H7_PB9_FUNC_SDMMC2_D5 0x190b
+#define STM32H7_PB9_FUNC_I2C4_SMBA 0x190c
+#define STM32H7_PB9_FUNC_SDMMC1_D5 0x190d
+#define STM32H7_PB9_FUNC_DCMI_D7 0x190e
+#define STM32H7_PB9_FUNC_LCD_B7 0x190f
+#define STM32H7_PB9_FUNC_EVENTOUT 0x1910
+#define STM32H7_PB9_FUNC_ANALOG 0x1911
+
+#define STM32H7_PB10_FUNC_GPIO 0x1a00
+#define STM32H7_PB10_FUNC_TIM2_CH3 0x1a02
+#define STM32H7_PB10_FUNC_HRTIM_SCOUT 0x1a03
+#define STM32H7_PB10_FUNC_LPTIM2_IN1 0x1a04
+#define STM32H7_PB10_FUNC_I2C2_SCL 0x1a05
+#define STM32H7_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06
+#define STM32H7_PB10_FUNC_DFSDM_DATIN7 0x1a07
+#define STM32H7_PB10_FUNC_USART3_TX 0x1a08
+#define STM32H7_PB10_FUNC_QUADSPI_BK1_NCS 0x1a0a
+#define STM32H7_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b
+#define STM32H7_PB10_FUNC_ETH_MII_RX_ER 0x1a0c
+#define STM32H7_PB10_FUNC_LCD_G4 0x1a0f
+#define STM32H7_PB10_FUNC_EVENTOUT 0x1a10
+#define STM32H7_PB10_FUNC_ANALOG 0x1a11
+
+#define STM32H7_PB11_FUNC_GPIO 0x1b00
+#define STM32H7_PB11_FUNC_TIM2_CH4 0x1b02
+#define STM32H7_PB11_FUNC_HRTIM_SCIN 0x1b03
+#define STM32H7_PB11_FUNC_LPTIM2_ETR 0x1b04
+#define STM32H7_PB11_FUNC_I2C2_SDA 0x1b05
+#define STM32H7_PB11_FUNC_DFSDM_CKIN7 0x1b07
+#define STM32H7_PB11_FUNC_USART3_RX 0x1b08
+#define STM32H7_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b
+#define STM32H7_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c
+#define STM32H7_PB11_FUNC_DSI_TE 0x1b0e
+#define STM32H7_PB11_FUNC_LCD_G5 0x1b0f
+#define STM32H7_PB11_FUNC_EVENTOUT 0x1b10
+#define STM32H7_PB11_FUNC_ANALOG 0x1b11
+
+#define STM32H7_PB12_FUNC_GPIO 0x1c00
+#define STM32H7_PB12_FUNC_TIM1_BKIN 0x1c02
+#define STM32H7_PB12_FUNC_I2C2_SMBA 0x1c05
+#define STM32H7_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06
+#define STM32H7_PB12_FUNC_DFSDM_DATIN1 0x1c07
+#define STM32H7_PB12_FUNC_USART3_CK 0x1c08
+#define STM32H7_PB12_FUNC_CAN2_RX 0x1c0a
+#define STM32H7_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b
+#define STM32H7_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c
+#define STM32H7_PB12_FUNC_OTG_HS_ID 0x1c0d
+#define STM32H7_PB12_FUNC_TIM1_BKIN_COMP12 0x1c0e
+#define STM32H7_PB12_FUNC_UART5_RX 0x1c0f
+#define STM32H7_PB12_FUNC_EVENTOUT 0x1c10
+#define STM32H7_PB12_FUNC_ANALOG 0x1c11
+
+#define STM32H7_PB13_FUNC_GPIO 0x1d00
+#define STM32H7_PB13_FUNC_TIM1_CH1N 0x1d02
+#define STM32H7_PB13_FUNC_LPTIM2_OUT 0x1d04
+#define STM32H7_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06
+#define STM32H7_PB13_FUNC_DFSDM_CKIN1 0x1d07
+#define STM32H7_PB13_FUNC_USART3_CTS_NSS 0x1d08
+#define STM32H7_PB13_FUNC_CAN2_TX 0x1d0a
+#define STM32H7_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b
+#define STM32H7_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c
+#define STM32H7_PB13_FUNC_UART5_TX 0x1d0f
+#define STM32H7_PB13_FUNC_EVENTOUT 0x1d10
+#define STM32H7_PB13_FUNC_ANALOG 0x1d11
+
+#define STM32H7_PB14_FUNC_GPIO 0x1e00
+#define STM32H7_PB14_FUNC_TIM1_CH2N 0x1e02
+#define STM32H7_PB14_FUNC_TIM8_CH2N 0x1e04
+#define STM32H7_PB14_FUNC_USART1_TX 0x1e05
+#define STM32H7_PB14_FUNC_SPI2_MISO_I2S2_SDI 0x1e06
+#define STM32H7_PB14_FUNC_DFSDM_DATIN2 0x1e07
+#define STM32H7_PB14_FUNC_USART3_RTS 0x1e08
+#define STM32H7_PB14_FUNC_UART4_RTS 0x1e09
+#define STM32H7_PB14_FUNC_SDMMC2_D0 0x1e0a
+#define STM32H7_PB14_FUNC_OTG_HS_DM 0x1e0d
+#define STM32H7_PB14_FUNC_EVENTOUT 0x1e10
+#define STM32H7_PB14_FUNC_ANALOG 0x1e11
+
+#define STM32H7_PB15_FUNC_GPIO 0x1f00
+#define STM32H7_PB15_FUNC_RTC_REFIN 0x1f01
+#define STM32H7_PB15_FUNC_TIM1_CH3N 0x1f02
+#define STM32H7_PB15_FUNC_TIM8_CH3N 0x1f04
+#define STM32H7_PB15_FUNC_USART1_RX 0x1f05
+#define STM32H7_PB15_FUNC_SPI2_MOSI_I2S2_SDO 0x1f06
+#define STM32H7_PB15_FUNC_DFSDM_CKIN2 0x1f07
+#define STM32H7_PB15_FUNC_UART4_CTS 0x1f09
+#define STM32H7_PB15_FUNC_SDMMC2_D1 0x1f0a
+#define STM32H7_PB15_FUNC_OTG_HS_DP 0x1f0d
+#define STM32H7_PB15_FUNC_EVENTOUT 0x1f10
+#define STM32H7_PB15_FUNC_ANALOG 0x1f11
+
+#define STM32H7_PC0_FUNC_GPIO 0x2000
+#define STM32H7_PC0_FUNC_DFSDM_CKIN0 0x2004
+#define STM32H7_PC0_FUNC_DFSDM_DATIN4 0x2007
+#define STM32H7_PC0_FUNC_SAI2_FS_B 0x2009
+#define STM32H7_PC0_FUNC_OTG_HS_ULPI_STP 0x200b
+#define STM32H7_PC0_FUNC_FMC_SDNWE 0x200d
+#define STM32H7_PC0_FUNC_LCD_R5 0x200f
+#define STM32H7_PC0_FUNC_EVENTOUT 0x2010
+#define STM32H7_PC0_FUNC_ANALOG 0x2011
+
+#define STM32H7_PC1_FUNC_GPIO 0x2100
+#define STM32H7_PC1_FUNC_TRACED0 0x2101
+#define STM32H7_PC1_FUNC_SAI1_D1 0x2103
+#define STM32H7_PC1_FUNC_DFSDM_DATIN0 0x2104
+#define STM32H7_PC1_FUNC_DFSDM_CKIN4 0x2105
+#define STM32H7_PC1_FUNC_SPI2_MOSI_I2S2_SDO 0x2106
+#define STM32H7_PC1_FUNC_SAI1_SD_A 0x2107
+#define STM32H7_PC1_FUNC_SAI4_SD_A 0x2109
+#define STM32H7_PC1_FUNC_SDMMC2_CK 0x210a
+#define STM32H7_PC1_FUNC_SAI4_D1 0x210b
+#define STM32H7_PC1_FUNC_ETH_MDC 0x210c
+#define STM32H7_PC1_FUNC_MDIOS_MDC 0x210d
+#define STM32H7_PC1_FUNC_EVENTOUT 0x2110
+#define STM32H7_PC1_FUNC_ANALOG 0x2111
+
+#define STM32H7_PC2_FUNC_GPIO 0x2200
+#define STM32H7_PC2_FUNC_DFSDM_CKIN1 0x2204
+#define STM32H7_PC2_FUNC_SPI2_MISO_I2S2_SDI 0x2206
+#define STM32H7_PC2_FUNC_DFSDM_CKOUT 0x2207
+#define STM32H7_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b
+#define STM32H7_PC2_FUNC_ETH_MII_TXD2 0x220c
+#define STM32H7_PC2_FUNC_FMC_SDNE0 0x220d
+#define STM32H7_PC2_FUNC_EVENTOUT 0x2210
+#define STM32H7_PC2_FUNC_ANALOG 0x2211
+
+#define STM32H7_PC3_FUNC_GPIO 0x2300
+#define STM32H7_PC3_FUNC_DFSDM_DATIN1 0x2304
+#define STM32H7_PC3_FUNC_SPI2_MOSI_I2S2_SDO 0x2306
+#define STM32H7_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b
+#define STM32H7_PC3_FUNC_ETH_MII_TX_CLK 0x230c
+#define STM32H7_PC3_FUNC_FMC_SDCKE0 0x230d
+#define STM32H7_PC3_FUNC_EVENTOUT 0x2310
+#define STM32H7_PC3_FUNC_ANALOG 0x2311
+
+#define STM32H7_PC4_FUNC_GPIO 0x2400
+#define STM32H7_PC4_FUNC_DFSDM_CKIN2 0x2404
+#define STM32H7_PC4_FUNC_I2S1_MCK 0x2406
+#define STM32H7_PC4_FUNC_SPDIFRX_IN2 0x240a
+#define STM32H7_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c
+#define STM32H7_PC4_FUNC_FMC_SDNE0 0x240d
+#define STM32H7_PC4_FUNC_EVENTOUT 0x2410
+#define STM32H7_PC4_FUNC_ANALOG 0x2411
+
+#define STM32H7_PC5_FUNC_GPIO 0x2500
+#define STM32H7_PC5_FUNC_SAI1_D3 0x2503
+#define STM32H7_PC5_FUNC_DFSDM_DATIN2 0x2504
+#define STM32H7_PC5_FUNC_SPDIFRX_IN3 0x250a
+#define STM32H7_PC5_FUNC_SAI4_D3 0x250b
+#define STM32H7_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c
+#define STM32H7_PC5_FUNC_FMC_SDCKE0 0x250d
+#define STM32H7_PC5_FUNC_COMP_1_OUT 0x250e
+#define STM32H7_PC5_FUNC_EVENTOUT 0x2510
+#define STM32H7_PC5_FUNC_ANALOG 0x2511
+
+#define STM32H7_PC6_FUNC_GPIO 0x2600
+#define STM32H7_PC6_FUNC_HRTIM_CHA1 0x2602
+#define STM32H7_PC6_FUNC_TIM3_CH1 0x2603
+#define STM32H7_PC6_FUNC_TIM8_CH1 0x2604
+#define STM32H7_PC6_FUNC_DFSDM_CKIN3 0x2605
+#define STM32H7_PC6_FUNC_I2S2_MCK 0x2606
+#define STM32H7_PC6_FUNC_USART6_TX 0x2608
+#define STM32H7_PC6_FUNC_SDMMC1_D0DIR 0x2609
+#define STM32H7_PC6_FUNC_FMC_NWAIT 0x260a
+#define STM32H7_PC6_FUNC_SDMMC2_D6 0x260b
+#define STM32H7_PC6_FUNC_SDMMC1_D6 0x260d
+#define STM32H7_PC6_FUNC_DCMI_D0 0x260e
+#define STM32H7_PC6_FUNC_LCD_HSYNC 0x260f
+#define STM32H7_PC6_FUNC_EVENTOUT 0x2610
+#define STM32H7_PC6_FUNC_ANALOG 0x2611
+
+#define STM32H7_PC7_FUNC_GPIO 0x2700
+#define STM32H7_PC7_FUNC_TRGIO 0x2701
+#define STM32H7_PC7_FUNC_HRTIM_CHA2 0x2702
+#define STM32H7_PC7_FUNC_TIM3_CH2 0x2703
+#define STM32H7_PC7_FUNC_TIM8_CH2 0x2704
+#define STM32H7_PC7_FUNC_DFSDM_DATIN3 0x2705
+#define STM32H7_PC7_FUNC_I2S3_MCK 0x2707
+#define STM32H7_PC7_FUNC_USART6_RX 0x2708
+#define STM32H7_PC7_FUNC_SDMMC1_D123DIR 0x2709
+#define STM32H7_PC7_FUNC_FMC_NE1 0x270a
+#define STM32H7_PC7_FUNC_SDMMC2_D7 0x270b
+#define STM32H7_PC7_FUNC_SWPMI_TX 0x270c
+#define STM32H7_PC7_FUNC_SDMMC1_D7 0x270d
+#define STM32H7_PC7_FUNC_DCMI_D1 0x270e
+#define STM32H7_PC7_FUNC_LCD_G6 0x270f
+#define STM32H7_PC7_FUNC_EVENTOUT 0x2710
+#define STM32H7_PC7_FUNC_ANALOG 0x2711
+
+#define STM32H7_PC8_FUNC_GPIO 0x2800
+#define STM32H7_PC8_FUNC_TRACED1 0x2801
+#define STM32H7_PC8_FUNC_HRTIM_CHB1 0x2802
+#define STM32H7_PC8_FUNC_TIM3_CH3 0x2803
+#define STM32H7_PC8_FUNC_TIM8_CH3 0x2804
+#define STM32H7_PC8_FUNC_USART6_CK 0x2808
+#define STM32H7_PC8_FUNC_UART5_RTS 0x2809
+#define STM32H7_PC8_FUNC_FMC_NE2_FMC_NCE 0x280a
+#define STM32H7_PC8_FUNC_SWPMI_RX 0x280c
+#define STM32H7_PC8_FUNC_SDMMC1_D0 0x280d
+#define STM32H7_PC8_FUNC_DCMI_D2 0x280e
+#define STM32H7_PC8_FUNC_EVENTOUT 0x2810
+#define STM32H7_PC8_FUNC_ANALOG 0x2811
+
+#define STM32H7_PC9_FUNC_GPIO 0x2900
+#define STM32H7_PC9_FUNC_MCO2 0x2901
+#define STM32H7_PC9_FUNC_TIM3_CH4 0x2903
+#define STM32H7_PC9_FUNC_TIM8_CH4 0x2904
+#define STM32H7_PC9_FUNC_I2C3_SDA 0x2905
+#define STM32H7_PC9_FUNC_I2S_CKIN 0x2906
+#define STM32H7_PC9_FUNC_UART5_CTS 0x2909
+#define STM32H7_PC9_FUNC_QUADSPI_BK1_IO0 0x290a
+#define STM32H7_PC9_FUNC_LCD_G3 0x290b
+#define STM32H7_PC9_FUNC_SWPMI_SUSPEND 0x290c
+#define STM32H7_PC9_FUNC_SDMMC1_D1 0x290d
+#define STM32H7_PC9_FUNC_DCMI_D3 0x290e
+#define STM32H7_PC9_FUNC_LCD_B2 0x290f
+#define STM32H7_PC9_FUNC_EVENTOUT 0x2910
+#define STM32H7_PC9_FUNC_ANALOG 0x2911
+
+#define STM32H7_PC10_FUNC_GPIO 0x2a00
+#define STM32H7_PC10_FUNC_HRTIM_EEV1 0x2a03
+#define STM32H7_PC10_FUNC_DFSDM_CKIN5 0x2a04
+#define STM32H7_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07
+#define STM32H7_PC10_FUNC_USART3_TX 0x2a08
+#define STM32H7_PC10_FUNC_UART4_TX 0x2a09
+#define STM32H7_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a
+#define STM32H7_PC10_FUNC_SDMMC1_D2 0x2a0d
+#define STM32H7_PC10_FUNC_DCMI_D8 0x2a0e
+#define STM32H7_PC10_FUNC_LCD_R2 0x2a0f
+#define STM32H7_PC10_FUNC_EVENTOUT 0x2a10
+#define STM32H7_PC10_FUNC_ANALOG 0x2a11
+
+#define STM32H7_PC11_FUNC_GPIO 0x2b00
+#define STM32H7_PC11_FUNC_HRTIM_FLT2 0x2b03
+#define STM32H7_PC11_FUNC_DFSDM_DATIN5 0x2b04
+#define STM32H7_PC11_FUNC_SPI3_MISO_I2S3_SDI 0x2b07
+#define STM32H7_PC11_FUNC_USART3_RX 0x2b08
+#define STM32H7_PC11_FUNC_UART4_RX 0x2b09
+#define STM32H7_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a
+#define STM32H7_PC11_FUNC_SDMMC1_D3 0x2b0d
+#define STM32H7_PC11_FUNC_DCMI_D4 0x2b0e
+#define STM32H7_PC11_FUNC_EVENTOUT 0x2b10
+#define STM32H7_PC11_FUNC_ANALOG 0x2b11
+
+#define STM32H7_PC12_FUNC_GPIO 0x2c00
+#define STM32H7_PC12_FUNC_TRACED3 0x2c01
+#define STM32H7_PC12_FUNC_HRTIM_EEV2 0x2c03
+#define STM32H7_PC12_FUNC_SPI3_MOSI_I2S3_SDO 0x2c07
+#define STM32H7_PC12_FUNC_USART3_CK 0x2c08
+#define STM32H7_PC12_FUNC_UART5_TX 0x2c09
+#define STM32H7_PC12_FUNC_SDMMC1_CK 0x2c0d
+#define STM32H7_PC12_FUNC_DCMI_D9 0x2c0e
+#define STM32H7_PC12_FUNC_EVENTOUT 0x2c10
+#define STM32H7_PC12_FUNC_ANALOG 0x2c11
+
+#define STM32H7_PC13_FUNC_GPIO 0x2d00
+#define STM32H7_PC13_FUNC_EVENTOUT 0x2d10
+#define STM32H7_PC13_FUNC_ANALOG 0x2d11
+
+#define STM32H7_PC14_FUNC_GPIO 0x2e00
+#define STM32H7_PC14_FUNC_EVENTOUT 0x2e10
+#define STM32H7_PC14_FUNC_ANALOG 0x2e11
+
+#define STM32H7_PC15_FUNC_GPIO 0x2f00
+#define STM32H7_PC15_FUNC_EVENTOUT 0x2f10
+#define STM32H7_PC15_FUNC_ANALOG 0x2f11
+
+#define STM32H7_PD0_FUNC_GPIO 0x3000
+#define STM32H7_PD0_FUNC_DFSDM_CKIN6 0x3004
+#define STM32H7_PD0_FUNC_SAI3_SCK_A 0x3007
+#define STM32H7_PD0_FUNC_UART4_RX 0x3009
+#define STM32H7_PD0_FUNC_CAN1_RX 0x300a
+#define STM32H7_PD0_FUNC_FMC_D2_FMC_DA2 0x300d
+#define STM32H7_PD0_FUNC_EVENTOUT 0x3010
+#define STM32H7_PD0_FUNC_ANALOG 0x3011
+
+#define STM32H7_PD1_FUNC_GPIO 0x3100
+#define STM32H7_PD1_FUNC_DFSDM_DATIN6 0x3104
+#define STM32H7_PD1_FUNC_SAI3_SD_A 0x3107
+#define STM32H7_PD1_FUNC_UART4_TX 0x3109
+#define STM32H7_PD1_FUNC_CAN1_TX 0x310a
+#define STM32H7_PD1_FUNC_FMC_D3_FMC_DA3 0x310d
+#define STM32H7_PD1_FUNC_EVENTOUT 0x3110
+#define STM32H7_PD1_FUNC_ANALOG 0x3111
+
+#define STM32H7_PD2_FUNC_GPIO 0x3200
+#define STM32H7_PD2_FUNC_TRACED2 0x3201
+#define STM32H7_PD2_FUNC_TIM3_ETR 0x3203
+#define STM32H7_PD2_FUNC_UART5_RX 0x3209
+#define STM32H7_PD2_FUNC_SDMMC1_CMD 0x320d
+#define STM32H7_PD2_FUNC_DCMI_D11 0x320e
+#define STM32H7_PD2_FUNC_EVENTOUT 0x3210
+#define STM32H7_PD2_FUNC_ANALOG 0x3211
+
+#define STM32H7_PD3_FUNC_GPIO 0x3300
+#define STM32H7_PD3_FUNC_DFSDM_CKOUT 0x3304
+#define STM32H7_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306
+#define STM32H7_PD3_FUNC_USART2_CTS_NSS 0x3308
+#define STM32H7_PD3_FUNC_FMC_CLK 0x330d
+#define STM32H7_PD3_FUNC_DCMI_D5 0x330e
+#define STM32H7_PD3_FUNC_LCD_G7 0x330f
+#define STM32H7_PD3_FUNC_EVENTOUT 0x3310
+#define STM32H7_PD3_FUNC_ANALOG 0x3311
+
+#define STM32H7_PD4_FUNC_GPIO 0x3400
+#define STM32H7_PD4_FUNC_HRTIM_FLT3 0x3403
+#define STM32H7_PD4_FUNC_SAI3_FS_A 0x3407
+#define STM32H7_PD4_FUNC_USART2_RTS 0x3408
+#define STM32H7_PD4_FUNC_CAN1_RXFD 0x340a
+#define STM32H7_PD4_FUNC_FMC_NOE 0x340d
+#define STM32H7_PD4_FUNC_EVENTOUT 0x3410
+#define STM32H7_PD4_FUNC_ANALOG 0x3411
+
+#define STM32H7_PD5_FUNC_GPIO 0x3500
+#define STM32H7_PD5_FUNC_HRTIM_EEV3 0x3503
+#define STM32H7_PD5_FUNC_USART2_TX 0x3508
+#define STM32H7_PD5_FUNC_CAN1_TXFD 0x350a
+#define STM32H7_PD5_FUNC_FMC_NWE 0x350d
+#define STM32H7_PD5_FUNC_EVENTOUT 0x3510
+#define STM32H7_PD5_FUNC_ANALOG 0x3511
+
+#define STM32H7_PD6_FUNC_GPIO 0x3600
+#define STM32H7_PD6_FUNC_SAI1_D1 0x3603
+#define STM32H7_PD6_FUNC_DFSDM_CKIN4 0x3604
+#define STM32H7_PD6_FUNC_DFSDM_DATIN1 0x3605
+#define STM32H7_PD6_FUNC_SPI3_MOSI_I2S3_SDO 0x3606
+#define STM32H7_PD6_FUNC_SAI1_SD_A 0x3607
+#define STM32H7_PD6_FUNC_USART2_RX 0x3608
+#define STM32H7_PD6_FUNC_SAI4_SD_A 0x3609
+#define STM32H7_PD6_FUNC_CAN2_RXFD 0x360a
+#define STM32H7_PD6_FUNC_SAI4_D1 0x360b
+#define STM32H7_PD6_FUNC_SDMMC2_CK 0x360c
+#define STM32H7_PD6_FUNC_FMC_NWAIT 0x360d
+#define STM32H7_PD6_FUNC_DCMI_D10 0x360e
+#define STM32H7_PD6_FUNC_LCD_B2 0x360f
+#define STM32H7_PD6_FUNC_EVENTOUT 0x3610
+#define STM32H7_PD6_FUNC_ANALOG 0x3611
+
+#define STM32H7_PD7_FUNC_GPIO 0x3700
+#define STM32H7_PD7_FUNC_DFSDM_DATIN4 0x3704
+#define STM32H7_PD7_FUNC_SPI1_MOSI_I2S1_SDO 0x3706
+#define STM32H7_PD7_FUNC_DFSDM_CKIN1 0x3707
+#define STM32H7_PD7_FUNC_USART2_CK 0x3708
+#define STM32H7_PD7_FUNC_SPDIFRX_IN0 0x370a
+#define STM32H7_PD7_FUNC_SDMMC2_CMD 0x370c
+#define STM32H7_PD7_FUNC_FMC_NE1 0x370d
+#define STM32H7_PD7_FUNC_EVENTOUT 0x3710
+#define STM32H7_PD7_FUNC_ANALOG 0x3711
+
+#define STM32H7_PD8_FUNC_GPIO 0x3800
+#define STM32H7_PD8_FUNC_DFSDM_CKIN3 0x3804
+#define STM32H7_PD8_FUNC_SAI3_SCK_B 0x3807
+#define STM32H7_PD8_FUNC_USART3_TX 0x3808
+#define STM32H7_PD8_FUNC_SPDIFRX_IN1 0x380a
+#define STM32H7_PD8_FUNC_FMC_D13_FMC_DA13 0x380d
+#define STM32H7_PD8_FUNC_EVENTOUT 0x3810
+#define STM32H7_PD8_FUNC_ANALOG 0x3811
+
+#define STM32H7_PD9_FUNC_GPIO 0x3900
+#define STM32H7_PD9_FUNC_DFSDM_DATIN3 0x3904
+#define STM32H7_PD9_FUNC_SAI3_SD_B 0x3907
+#define STM32H7_PD9_FUNC_USART3_RX 0x3908
+#define STM32H7_PD9_FUNC_CAN2_RXFD 0x390a
+#define STM32H7_PD9_FUNC_FMC_D14_FMC_DA14 0x390d
+#define STM32H7_PD9_FUNC_EVENTOUT 0x3910
+#define STM32H7_PD9_FUNC_ANALOG 0x3911
+
+#define STM32H7_PD10_FUNC_GPIO 0x3a00
+#define STM32H7_PD10_FUNC_DFSDM_CKOUT 0x3a04
+#define STM32H7_PD10_FUNC_SAI3_FS_B 0x3a07
+#define STM32H7_PD10_FUNC_USART3_CK 0x3a08
+#define STM32H7_PD10_FUNC_CAN2_TXFD 0x3a0a
+#define STM32H7_PD10_FUNC_FMC_D15_FMC_DA15 0x3a0d
+#define STM32H7_PD10_FUNC_LCD_B3 0x3a0f
+#define STM32H7_PD10_FUNC_EVENTOUT 0x3a10
+#define STM32H7_PD10_FUNC_ANALOG 0x3a11
+
+#define STM32H7_PD11_FUNC_GPIO 0x3b00
+#define STM32H7_PD11_FUNC_LPTIM2_IN2 0x3b04
+#define STM32H7_PD11_FUNC_I2C4_SMBA 0x3b05
+#define STM32H7_PD11_FUNC_USART3_CTS_NSS 0x3b08
+#define STM32H7_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a
+#define STM32H7_PD11_FUNC_SAI2_SD_A 0x3b0b
+#define STM32H7_PD11_FUNC_FMC_A16 0x3b0d
+#define STM32H7_PD11_FUNC_EVENTOUT 0x3b10
+#define STM32H7_PD11_FUNC_ANALOG 0x3b11
+
+#define STM32H7_PD12_FUNC_GPIO 0x3c00
+#define STM32H7_PD12_FUNC_LPTIM1_IN1 0x3c02
+#define STM32H7_PD12_FUNC_TIM4_CH1 0x3c03
+#define STM32H7_PD12_FUNC_LPTIM2_IN1 0x3c04
+#define STM32H7_PD12_FUNC_I2C4_SCL 0x3c05
+#define STM32H7_PD12_FUNC_USART3_RTS 0x3c08
+#define STM32H7_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a
+#define STM32H7_PD12_FUNC_SAI2_FS_A 0x3c0b
+#define STM32H7_PD12_FUNC_FMC_A17 0x3c0d
+#define STM32H7_PD12_FUNC_EVENTOUT 0x3c10
+#define STM32H7_PD12_FUNC_ANALOG 0x3c11
+
+#define STM32H7_PD13_FUNC_GPIO 0x3d00
+#define STM32H7_PD13_FUNC_LPTIM1_OUT 0x3d02
+#define STM32H7_PD13_FUNC_TIM4_CH2 0x3d03
+#define STM32H7_PD13_FUNC_I2C4_SDA 0x3d05
+#define STM32H7_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a
+#define STM32H7_PD13_FUNC_SAI2_SCK_A 0x3d0b
+#define STM32H7_PD13_FUNC_FMC_A18 0x3d0d
+#define STM32H7_PD13_FUNC_EVENTOUT 0x3d10
+#define STM32H7_PD13_FUNC_ANALOG 0x3d11
+
+#define STM32H7_PD14_FUNC_GPIO 0x3e00
+#define STM32H7_PD14_FUNC_TIM4_CH3 0x3e03
+#define STM32H7_PD14_FUNC_SAI3_MCLK_B 0x3e07
+#define STM32H7_PD14_FUNC_UART8_CTS 0x3e09
+#define STM32H7_PD14_FUNC_FMC_D0_FMC_DA0 0x3e0d
+#define STM32H7_PD14_FUNC_EVENTOUT 0x3e10
+#define STM32H7_PD14_FUNC_ANALOG 0x3e11
+
+#define STM32H7_PD15_FUNC_GPIO 0x3f00
+#define STM32H7_PD15_FUNC_TIM4_CH4 0x3f03
+#define STM32H7_PD15_FUNC_SAI3_MCLK_A 0x3f07
+#define STM32H7_PD15_FUNC_UART8_RTS 0x3f09
+#define STM32H7_PD15_FUNC_FMC_D1_FMC_DA1 0x3f0d
+#define STM32H7_PD15_FUNC_EVENTOUT 0x3f10
+#define STM32H7_PD15_FUNC_ANALOG 0x3f11
+
+#define STM32H7_PE0_FUNC_GPIO 0x4000
+#define STM32H7_PE0_FUNC_LPTIM1_ETR 0x4002
+#define STM32H7_PE0_FUNC_TIM4_ETR 0x4003
+#define STM32H7_PE0_FUNC_HRTIM_SCIN 0x4004
+#define STM32H7_PE0_FUNC_LPTIM2_ETR 0x4005
+#define STM32H7_PE0_FUNC_UART8_RX 0x4009
+#define STM32H7_PE0_FUNC_CAN1_RXFD 0x400a
+#define STM32H7_PE0_FUNC_SAI2_MCK_A 0x400b
+#define STM32H7_PE0_FUNC_FMC_NBL0 0x400d
+#define STM32H7_PE0_FUNC_DCMI_D2 0x400e
+#define STM32H7_PE0_FUNC_EVENTOUT 0x4010
+#define STM32H7_PE0_FUNC_ANALOG 0x4011
+
+#define STM32H7_PE1_FUNC_GPIO 0x4100
+#define STM32H7_PE1_FUNC_LPTIM1_IN2 0x4102
+#define STM32H7_PE1_FUNC_HRTIM_SCOUT 0x4104
+#define STM32H7_PE1_FUNC_UART8_TX 0x4109
+#define STM32H7_PE1_FUNC_CAN1_TXFD 0x410a
+#define STM32H7_PE1_FUNC_FMC_NBL1 0x410d
+#define STM32H7_PE1_FUNC_DCMI_D3 0x410e
+#define STM32H7_PE1_FUNC_EVENTOUT 0x4110
+#define STM32H7_PE1_FUNC_ANALOG 0x4111
+
+#define STM32H7_PE2_FUNC_GPIO 0x4200
+#define STM32H7_PE2_FUNC_TRACECLK 0x4201
+#define STM32H7_PE2_FUNC_SAI1_CK1 0x4203
+#define STM32H7_PE2_FUNC_SPI4_SCK 0x4206
+#define STM32H7_PE2_FUNC_SAI1_MCLK_A 0x4207
+#define STM32H7_PE2_FUNC_SAI4_MCLK_A 0x4209
+#define STM32H7_PE2_FUNC_QUADSPI_BK1_IO2 0x420a
+#define STM32H7_PE2_FUNC_SAI4_CK1 0x420b
+#define STM32H7_PE2_FUNC_ETH_MII_TXD3 0x420c
+#define STM32H7_PE2_FUNC_FMC_A23 0x420d
+#define STM32H7_PE2_FUNC_EVENTOUT 0x4210
+#define STM32H7_PE2_FUNC_ANALOG 0x4211
+
+#define STM32H7_PE3_FUNC_GPIO 0x4300
+#define STM32H7_PE3_FUNC_TRACED0 0x4301
+#define STM32H7_PE3_FUNC_TIM15_BKIN 0x4305
+#define STM32H7_PE3_FUNC_SAI1_SD_B 0x4307
+#define STM32H7_PE3_FUNC_SAI4_SD_B 0x4309
+#define STM32H7_PE3_FUNC_FMC_A19 0x430d
+#define STM32H7_PE3_FUNC_EVENTOUT 0x4310
+#define STM32H7_PE3_FUNC_ANALOG 0x4311
+
+#define STM32H7_PE4_FUNC_GPIO 0x4400
+#define STM32H7_PE4_FUNC_TRACED1 0x4401
+#define STM32H7_PE4_FUNC_SAI1_D2 0x4403
+#define STM32H7_PE4_FUNC_DFSDM_DATIN3 0x4404
+#define STM32H7_PE4_FUNC_TIM15_CH1N 0x4405
+#define STM32H7_PE4_FUNC_SPI4_NSS 0x4406
+#define STM32H7_PE4_FUNC_SAI1_FS_A 0x4407
+#define STM32H7_PE4_FUNC_SAI4_FS_A 0x4409
+#define STM32H7_PE4_FUNC_SAI4_D2 0x440b
+#define STM32H7_PE4_FUNC_FMC_A20 0x440d
+#define STM32H7_PE4_FUNC_DCMI_D4 0x440e
+#define STM32H7_PE4_FUNC_LCD_B0 0x440f
+#define STM32H7_PE4_FUNC_EVENTOUT 0x4410
+#define STM32H7_PE4_FUNC_ANALOG 0x4411
+
+#define STM32H7_PE5_FUNC_GPIO 0x4500
+#define STM32H7_PE5_FUNC_TRACED2 0x4501
+#define STM32H7_PE5_FUNC_SAI1_CK2 0x4503
+#define STM32H7_PE5_FUNC_DFSDM_CKIN3 0x4504
+#define STM32H7_PE5_FUNC_TIM15_CH1 0x4505
+#define STM32H7_PE5_FUNC_SPI4_MISO 0x4506
+#define STM32H7_PE5_FUNC_SAI1_SCK_A 0x4507
+#define STM32H7_PE5_FUNC_SAI4_SCK_A 0x4509
+#define STM32H7_PE5_FUNC_SAI4_CK2 0x450b
+#define STM32H7_PE5_FUNC_FMC_A21 0x450d
+#define STM32H7_PE5_FUNC_DCMI_D6 0x450e
+#define STM32H7_PE5_FUNC_LCD_G0 0x450f
+#define STM32H7_PE5_FUNC_EVENTOUT 0x4510
+#define STM32H7_PE5_FUNC_ANALOG 0x4511
+
+#define STM32H7_PE6_FUNC_GPIO 0x4600
+#define STM32H7_PE6_FUNC_TRACED3 0x4601
+#define STM32H7_PE6_FUNC_TIM1_BKIN2 0x4602
+#define STM32H7_PE6_FUNC_SAI1_D1 0x4603
+#define STM32H7_PE6_FUNC_TIM15_CH2 0x4605
+#define STM32H7_PE6_FUNC_SPI4_MOSI 0x4606
+#define STM32H7_PE6_FUNC_SAI1_SD_A 0x4607
+#define STM32H7_PE6_FUNC_SAI4_SD_A 0x4609
+#define STM32H7_PE6_FUNC_SAI4_D1 0x460a
+#define STM32H7_PE6_FUNC_SAI2_MCK_B 0x460b
+#define STM32H7_PE6_FUNC_TIM1_BKIN2_COMP12 0x460c
+#define STM32H7_PE6_FUNC_FMC_A22 0x460d
+#define STM32H7_PE6_FUNC_DCMI_D7 0x460e
+#define STM32H7_PE6_FUNC_LCD_G1 0x460f
+#define STM32H7_PE6_FUNC_EVENTOUT 0x4610
+#define STM32H7_PE6_FUNC_ANALOG 0x4611
+
+#define STM32H7_PE7_FUNC_GPIO 0x4700
+#define STM32H7_PE7_FUNC_TIM1_ETR 0x4702
+#define STM32H7_PE7_FUNC_DFSDM_DATIN2 0x4704
+#define STM32H7_PE7_FUNC_UART7_RX 0x4708
+#define STM32H7_PE7_FUNC_QUADSPI_BK2_IO0 0x470b
+#define STM32H7_PE7_FUNC_FMC_D4_FMC_DA4 0x470d
+#define STM32H7_PE7_FUNC_EVENTOUT 0x4710
+#define STM32H7_PE7_FUNC_ANALOG 0x4711
+
+#define STM32H7_PE8_FUNC_GPIO 0x4800
+#define STM32H7_PE8_FUNC_TIM1_CH1N 0x4802
+#define STM32H7_PE8_FUNC_DFSDM_CKIN2 0x4804
+#define STM32H7_PE8_FUNC_UART7_TX 0x4808
+#define STM32H7_PE8_FUNC_QUADSPI_BK2_IO1 0x480b
+#define STM32H7_PE8_FUNC_FMC_D5_FMC_DA5 0x480d
+#define STM32H7_PE8_FUNC_COMP_2_OUT 0x480e
+#define STM32H7_PE8_FUNC_EVENTOUT 0x4810
+#define STM32H7_PE8_FUNC_ANALOG 0x4811
+
+#define STM32H7_PE9_FUNC_GPIO 0x4900
+#define STM32H7_PE9_