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| author | Stephen Boyd <sboyd@codeaurora.org> | 2017-10-05 16:52:59 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-10-05 16:52:59 -0700 |
| commit | 0a4e632b6f9d1ccabe3e9507814184cd34ff3f31 (patch) | |
| tree | 159fb3f5e032d119228ff07e1478f57887da58a5 /include/dt-bindings/clock/s3c2443.h | |
| parent | e7cc33358a88e0a0949370ada47144c11c2aa290 (diff) | |
| parent | 5dcbeca615ef12047a5f4097b91030cbf995b1d2 (diff) | |
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle
Diffstat (limited to 'include/dt-bindings/clock/s3c2443.h')
0 files changed, 0 insertions, 0 deletions