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author | Linus Walleij <linus.walleij@linaro.org> | 2018-10-23 09:24:22 +0200 |
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committer | Linus Walleij <linus.walleij@linaro.org> | 2018-10-24 16:26:35 +0200 |
commit | e982e3f02071473cd1211e26cbe74a56b5be0aa0 (patch) | |
tree | 8194fb21d45713281a7d86a6d29871413317d034 /include/drm/drm_syncobj.h | |
parent | 9edb6a0b206cb46782f9e74be035894bff9e0064 (diff) |
drm: dsi: Add lane clock rate fields to DSI device
The DSI devices have a maximum operating frequency specified
in their data sheet per the MIPI specification, and DSI hosts
that can scale their frequency need this information to set
their clock dividers right.
As current panel drivers often lack this information, specify
that setting it to zero will make the DSI host use some
reasonable default.
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20181023072422.25754-1-linus.walleij@linaro.org
Diffstat (limited to 'include/drm/drm_syncobj.h')
0 files changed, 0 insertions, 0 deletions