[PATCH] mips: nuke trailing whitespace

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

41 files changed, 315 insertions, 315 deletions

diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
index 40ceedcf454e..30b18ea6cb11 100644
--- a/include/asm-mips/asmmacro.h
+++ b/include/asm-mips/asmmacro.h
@@ -7,10 +7,10 @@
  */
 #ifndef _ASM_ASMMACRO_H
 #define _ASM_ASMMACRO_H
- 
+
 #include <linux/config.h>
 #include <asm/hazards.h>
- 
+
 #ifdef CONFIG_32BIT
 #include <asm/asmmacro-32.h>
 #endif
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index bc136dcfdbe6..eb8d79dba11c 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -20,13 +20,13 @@
 #define SZLONG_MASK 31UL
 #define __LL	"ll	"
 #define __SC	"sc	"
-#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) 
+#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
 #elif (_MIPS_SZLONG == 64)
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
 #define __LL	"lld	"
 #define __SC	"scd	"
-#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) 
+#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
 #endif
 
 #ifdef __KERNEL__
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h
index ae3e2a38fd5f..a438548e6ef3 100644
--- a/include/asm-mips/ddb5xxx/ddb5477.h
+++ b/include/asm-mips/ddb5xxx/ddb5477.h
@@ -247,7 +247,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
  *  All PCI irq but INTC are active low.
  */
 
-/* 
+/*
  * irq number block assignment
  */
 
@@ -285,7 +285,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
 #define VRC5477_IRQ_IOPCI_INTB	(17 + VRC5477_IRQ_BASE)      /* USB-P */
 #define VRC5477_IRQ_IOPCI_INTC	(18 + VRC5477_IRQ_BASE)      /* AC97 */
 #define VRC5477_IRQ_IOPCI_INTD	(19 + VRC5477_IRQ_BASE)      /* Reserved */
-#define VRC5477_IRQ_UART1	(20 + VRC5477_IRQ_BASE)     
+#define VRC5477_IRQ_UART1	(20 + VRC5477_IRQ_BASE)
 #define VRC5477_IRQ_SPT0	(21 + VRC5477_IRQ_BASE)      /* special purpose timer 0 */
 #define VRC5477_IRQ_GPT0	(22 + VRC5477_IRQ_BASE)      /* general purpose timer 0 */
 #define VRC5477_IRQ_GPT1	(23 + VRC5477_IRQ_BASE)      /* general purpose timer 1 */
@@ -301,7 +301,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
 /*
  * i2859 irq assignment
  */
-#define I8259_IRQ_RESERVED_0	(0 + I8259_IRQ_BASE)	
+#define I8259_IRQ_RESERVED_0	(0 + I8259_IRQ_BASE)
 #define I8259_IRQ_KEYBOARD	(1 + I8259_IRQ_BASE)	/* M1543 default */
 #define I8259_IRQ_CASCADE	(2 + I8259_IRQ_BASE)
 #define I8259_IRQ_UART_B	(3 + I8259_IRQ_BASE)	/* M1543 default, may conflict with RTC according to schematic diagram  */
diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h
index 1d9aa0979181..2b5fddc8f487 100644
--- a/include/asm-mips/fpregdef.h
+++ b/include/asm-mips/fpregdef.h
@@ -13,7 +13,7 @@
 #define _ASM_FPREGDEF_H
 
 #include <asm/sgidefs.h>
-                                                                                
+
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
@@ -56,7 +56,7 @@
 #define fcr31	$31      /* FPU status register */
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-                                                                                
+
 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
 
 #define fv0	$f0	/* return value */
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
index 6cb38d5c0407..ea24e733b1bc 100644
--- a/include/asm-mips/fpu.h
+++ b/include/asm-mips/fpu.h
@@ -82,7 +82,7 @@ do {									\
 
 static inline int is_fpu_owner(void)
 {
-	return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); 
+	return cpu_has_fpu && test_thread_flag(TIF_USEDFPU);
 }
 
 static inline void own_fpu(void)
@@ -90,7 +90,7 @@ static inline void own_fpu(void)
 	if (cpu_has_fpu) {
 		__enable_fpu();
 		KSTK_STATUS(current) |= ST0_CU1;
-		set_thread_flag(TIF_USEDFPU); 
+		set_thread_flag(TIF_USEDFPU);
 	}
 }
 
@@ -98,7 +98,7 @@ static inline void lose_fpu(void)
 {
 	if (cpu_has_fpu) {
 		KSTK_STATUS(current) &= ~ST0_CU1;
-		clear_thread_flag(TIF_USEDFPU); 
+		clear_thread_flag(TIF_USEDFPU);
 		__disable_fpu();
 	}
 }
@@ -127,7 +127,7 @@ static inline void restore_fp(struct task_struct *tsk)
 static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
 {
 	if (cpu_has_fpu) {
-		if ((tsk == current) && is_fpu_owner()) 
+		if ((tsk == current) && is_fpu_owner())
 			_save_fp(current);
 		return tsk->thread.fpu.hard.fpr;
 	}
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
index 2b7b0fdeac19..432011b16c26 100644
--- a/include/asm-mips/ip32/mace.h
+++ b/include/asm-mips/ip32/mace.h
@@ -94,7 +94,7 @@ struct mace_video {
 	unsigned long xxx;	/* later... */
 };
 
-/* 
+/*
  * Ethernet interface
  */
 struct mace_ethernet {
@@ -129,7 +129,7 @@ struct mace_ethernet {
 	volatile unsigned long rx_fifo;
 };
 
-/* 
+/*
  * Peripherals
  */
 
@@ -251,7 +251,7 @@ struct mace_timers {
 	timer_reg audio_out2;
 	timer_reg video_in1;
 	timer_reg video_in2;
-	timer_reg video_out;	
+	timer_reg video_out;
 };
 
 struct mace_perif {
@@ -272,7 +272,7 @@ struct mace_perif {
 };
 
 
-/* 
+/*
  * ISA peripherals
  */
 
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
index 21d0fb7cee64..9e88c7669c7a 100644
--- a/include/asm-mips/lasat/serial.h
+++ b/include/asm-mips/lasat/serial.h
@@ -1,13 +1,13 @@
 #include <asm/lasat/lasat.h>
 
 /* Lasat 100 boards serial configuration */
-#define LASAT_BASE_BAUD_100 		( 7372800 / 16 ) 
+#define LASAT_BASE_BAUD_100 		( 7372800 / 16 )
 #define LASAT_UART_REGS_BASE_100	0x1c8b0000
 #define LASAT_UART_REGS_SHIFT_100	2
 #define LASATINT_UART_100		8
 
 /* * LASAT 200 boards serial configuration */
-#define LASAT_BASE_BAUD_200		(100000000 / 16 / 12) 
+#define LASAT_BASE_BAUD_200		(100000000 / 16 / 12)
 #define LASAT_UART_REGS_BASE_200	(Vrc5074_PHYS_BASE + 0x0300)
 #define LASAT_UART_REGS_SHIFT_200	3
 #define LASATINT_UART_200		13
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 2b36ea346910..148bae2fa7d3 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -1383,7 +1383,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define PCI_IO_START    0
 #define PCI_IO_END      0
 #define PCI_MEM_START   0
-#define PCI_MEM_END     0 
+#define PCI_MEM_END     0
 #define PCI_FIRST_DEVFN 0
 #define PCI_LAST_DEVFN  0
 #endif
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index 4691398a414f..efafe65258b6 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -23,7 +23,7 @@
  *
  * ########################################################################
  *
- * 
+ *
  */
 #ifndef __ASM_DB1X00_H
 #define __ASM_DB1X00_H
diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h
index 8cf0d042c864..c9dad99b1232 100644
--- a/include/asm-mips/mach-jazz/floppy.h
+++ b/include/asm-mips/mach-jazz/floppy.h
@@ -92,7 +92,7 @@ static inline int fd_request_irq(void)
 	return request_irq(FLOPPY_IRQ, floppy_interrupt,
 	                   SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL);
 }
-                                                                                
+
 static inline void fd_free_irq(void)
 {
 	free_irq(FLOPPY_IRQ, NULL);
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h
index d6c779747b3c..ff6d40c87a25 100644
--- a/include/asm-mips/mach-pb1x00/pb1500.h
+++ b/include/asm-mips/mach-pb1x00/pb1500.h
@@ -33,11 +33,11 @@
 #define PCI_BOARD_REG             0xAE000010
 #define PCMCIA_BOARD_REG          0xAE000010
   #define PC_DEASSERT_RST               0x80
-  #define PC_DRV_EN                     0x10 
+  #define PC_DRV_EN                     0x10
 #define PB1500_G_CONTROL          0xAE000014
 #define PB1500_RST_VDDI           0xAE00001C
 #define PB1500_LEDS               0xAE000018
-  
+
 #define PB1500_HEX_LED            0xAF000004
 #define PB1500_HEX_LED_BLANK      0xAF000008
 
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index da03a32c1ca7..5bea49feec66 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -171,11 +171,11 @@ static inline void blast_dcache16(void)
 	unsigned long start = INDEX_BASE;
 	unsigned long end = start + current_cpu_data.dcache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-	unsigned long ws_end = current_cpu_data.dcache.ways << 
+	unsigned long ws_end = current_cpu_data.dcache.ways <<
 	                       current_cpu_data.dcache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
 		for (addr = start; addr < end; addr += 0x200)
 			cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
@@ -200,8 +200,8 @@ static inline void blast_dcache16_page_indexed(unsigned long page)
 	                       current_cpu_data.dcache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x200) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x200)
 			cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
 
@@ -214,8 +214,8 @@ static inline void blast_icache16(void)
 	                       current_cpu_data.icache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x200) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x200)
 			cache16_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -239,8 +239,8 @@ static inline void blast_icache16_page_indexed(unsigned long page)
 	                       current_cpu_data.icache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x200) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x200)
 			cache16_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -249,11 +249,11 @@ static inline void blast_scache16(void)
 	unsigned long start = INDEX_BASE;
 	unsigned long end = start + current_cpu_data.scache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-	unsigned long ws_end = current_cpu_data.scache.ways << 
+	unsigned long ws_end = current_cpu_data.scache.ways <<
 	                       current_cpu_data.scache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
 		for (addr = start; addr < end; addr += 0x200)
 			cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -278,8 +278,8 @@ static inline void blast_scache16_page_indexed(unsigned long page)
 	                       current_cpu_data.scache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x200) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x200)
 			cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
@@ -318,8 +318,8 @@ static inline void blast_dcache32(void)
 	                       current_cpu_data.dcache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x400) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x400)
 			cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
 
@@ -343,8 +343,8 @@ static inline void blast_dcache32_page_indexed(unsigned long page)
 	                       current_cpu_data.dcache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x400) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x400)
 			cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
 
@@ -357,8 +357,8 @@ static inline void blast_icache32(void)
 	                       current_cpu_data.icache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x400) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x400)
 			cache32_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -383,7 +383,7 @@ static inline void blast_icache32_page_indexed(unsigned long page)
 	unsigned long ws, addr;
 
 	for (ws = 0; ws < ws_end; ws += ws_inc)
-		for (addr = start; addr < end; addr += 0x400) 
+		for (addr = start; addr < end; addr += 0x400)
 			cache32_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -392,11 +392,11 @@ static inline void blast_scache32(void)
 	unsigned long start = INDEX_BASE;
 	unsigned long end = start + current_cpu_data.scache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-	unsigned long ws_end = current_cpu_data.scache.ways << 
+	unsigned long ws_end = current_cpu_data.scache.ways <<
 	                       current_cpu_data.scache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
 		for (addr = start; addr < end; addr += 0x400)
 			cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -421,8 +421,8 @@ static inline void blast_scache32_page_indexed(unsigned long page)
 	                       current_cpu_data.scache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x400) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x400)
 			cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
@@ -461,8 +461,8 @@ static inline void blast_icache64(void)
 	                       current_cpu_data.icache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x800) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x800)
 			cache64_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -487,7 +487,7 @@ static inline void blast_icache64_page_indexed(unsigned long page)
 	unsigned long ws, addr;
 
 	for (ws = 0; ws < ws_end; ws += ws_inc)
-		for (addr = start; addr < end; addr += 0x800) 
+		for (addr = start; addr < end; addr += 0x800)
 			cache64_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -496,11 +496,11 @@ static inline void blast_scache64(void)
 	unsigned long start = INDEX_BASE;
 	unsigned long end = start + current_cpu_data.scache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-	unsigned long ws_end = current_cpu_data.scache.ways << 
+	unsigned long ws_end = current_cpu_data.scache.ways <<
 	                       current_cpu_data.scache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
 		for (addr = start; addr < end; addr += 0x800)
 			cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -525,8 +525,8 @@ static inline void blast_scache64_page_indexed(unsigned long page)
 	                       current_cpu_data.scache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x800) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x800)
 			cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
@@ -561,11 +561,11 @@ static inline void blast_scache128(void)
 	unsigned long start = INDEX_BASE;
 	unsigned long end = start + current_cpu_data.scache.waysize;
 	unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-	unsigned long ws_end = current_cpu_data.scache.ways << 
+	unsigned long ws_end = current_cpu_data.scache.ways <<
 	                       current_cpu_data.scache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
 		for (addr = start; addr < end; addr += 0x1000)
 			cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -590,8 +590,8 @@ static inline void blast_scache128_page_indexed(unsigned long page)
 	                       current_cpu_data.scache.waybit;
 	unsigned long ws, addr;
 
-	for (ws = 0; ws < ws_end; ws += ws_inc) 
-		for (addr = start; addr < end; addr += 0x1000) 
+	for (ws = 0; ws < ws_end; ws += ws_inc)
+		for (addr = start; addr < end; addr += 0x1000)
 			cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h
index 31c0c2347f4f..3c4b637fd925 100644
--- a/include/asm-mips/rtc.h
+++ b/include/asm-mips/rtc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-mips/rtc.h 
+ * include/asm-mips/rtc.h
  *
  * (Really an interface for drivers/char/genrtc.c)
  *
diff --git a/include/asm-mips/sgi/gio.h b/include/asm-mips/sgi/gio.h
index a38d66f99872..889cf028c95d 100644
--- a/include/asm-mips/sgi/gio.h
+++ b/include/asm-mips/sgi/gio.h
@@ -16,7 +16,7 @@
  *
  * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
  * three physical connectors, but only two slots, GFX and EXP0.
- * 
+ *
  * There is 10MB of GIO address space for GIO64 slot devices
  * slot#   slot type address range            size
  * -----   --------- ----------------------- -----
diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h
index a5b988d7327a..ac3dfc7af5b0 100644
--- a/include/asm-mips/sgi/hpc3.h
+++ b/include/asm-mips/sgi/hpc3.h
@@ -221,7 +221,7 @@ struct hpc3_regs {
 #define HPC3_BESTAT_PIDMASK	0x3f700	/* DMA channel parity identifier */
 
 	u32 _unused1[0x14000/4 - 5];	/* padding */
-	
+
 	/* Now direct PIO per-HPC3 peripheral access to external regs. */
 	volatile u32 scsi0_ext[256];	/* SCSI channel 0 external regs */
 	u32 _unused2[0x7c00/4];
@@ -304,7 +304,7 @@ struct hpc3_regs {
 	volatile u32 bbram[8192-50-14];	/* Battery backed ram */
 };
 
-/* 
+/*
  * It is possible to have two HPC3's within the address space on
  * one machine, though only having one is more likely on an Indy.
  */
diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h
index 169187f53fbc..f3e3dc9bb732 100644
--- a/include/asm-mips/sgi/ioc.h
+++ b/include/asm-mips/sgi/ioc.h
@@ -16,7 +16,7 @@
 #include <linux/types.h>
 #include <asm/sgi/pi1.h>
 
-/* 
+/*
  * All registers are 8-bit wide alligned on 32-bit boundary. Bad things
  * happen if you try word access them. You have been warned.
  */
@@ -138,7 +138,7 @@ struct sgioc_regs {
 	u8 _sysid[3];
 	volatile u8 sysid;
 #define SGIOC_SYSID_FULLHOUSE	0x01
-#define SGIOC_SYSID_BOARDREV(x)	((x & 0xe0) > 5) 
+#define SGIOC_SYSID_BOARDREV(x)	((x & 0xe0) > 5)
 #define SGIOC_SYSID_CHIPREV(x)	((x & 0x1e) > 1)
 	u32 _unused2;
 	u8 _read[3];
diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h
index 97d73adb4e40..bbfc05c3cab9 100644
--- a/include/asm-mips/sgi/ip22.h
+++ b/include/asm-mips/sgi/ip22.h
@@ -12,7 +12,7 @@
 #ifndef _SGI_IP22_H
 #define _SGI_IP22_H
 
-/* 
+/*
  * These are the virtual IRQ numbers, we divide all IRQ's into
  * 'spaces', the 'space' determines where and how to enable/disable
  * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups
diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h
index fd98f930607c..c52f7834c7c8 100644
--- a/include/asm-mips/sgi/mc.h
+++ b/include/asm-mips/sgi/mc.h
@@ -182,14 +182,14 @@ struct sgimc_regs {
 	volatile u32 dtlb_hi3;
 	u32 _unused33;
 	volatile u32 dtlb_lo3;
-	
+
 	u32 _unused34[0x0392];
-	
+
 	u32 _unused35;
 	volatile u32 rpsscounter;	/* Chirps at 100ns */
 
 	u32 _unused36[0x1000/4-2*4];
-	
+
 	u32 _unused37;
 	volatile u32 maddronly;		/* Address DMA goes at */
 	u32 _unused38;
diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h
index 7ac5da13ce8a..b5e7dae19f0f 100644
--- a/include/asm-mips/sibyte/carmel.h
+++ b/include/asm-mips/sibyte/carmel.h
@@ -25,12 +25,12 @@
 
 #define SIBYTE_BOARD_NAME "Carmel"
 
-#define GPIO_PHY_INTERRUPT      2 
-#define GPIO_NONMASKABLE_INT    3 
-#define GPIO_CF_INSERTED        6 
-#define GPIO_MONTEREY_RESET     7 
-#define GPIO_QUADUART_INT       8 
-#define GPIO_CF_INT             9 
+#define GPIO_PHY_INTERRUPT      2
+#define GPIO_NONMASKABLE_INT    3
+#define GPIO_CF_INSERTED        6
+#define GPIO_MONTEREY_RESET     7
+#define GPIO_QUADUART_INT       8
+#define GPIO_CF_INT             9
 #define GPIO_FPGA_CCLK          10
 #define GPIO_FPGA_DOUT          11
 #define GPIO_FPGA_DIN           12
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index 96088fb074a4..40ef97c76c8b 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
-    *  Global constants and macros		File: sb1250_defs.h	
-    *  
+    *
+    *  Global constants and macros		File: sb1250_defs.h
+    *
     *  This file contains macros and definitions used by the other
     *  include files.
     *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -105,7 +105,7 @@
 #define	SIBYTE_HDR_FMASK_112x_ALL		0x0000f00
 #define	SIBYTE_HDR_FMASK_112x_PASS1		0x0000100
 
-/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */ 
+/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */
 #define	SIBYTE_HDR_FMASK(chip, pass)					\
     (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
 #define	SIBYTE_HDR_FMASK_ALLREVS(chip)					\
@@ -150,31 +150,31 @@
 
 /*  *********************************************************************
     *  Naming schemes for constants in these files:
-    *  
-    *  M_xxx           MASK constant (identifies bits in a register). 
+    *
+    *  M_xxx           MASK constant (identifies bits in a register).
     *                  For multi-bit fields, all bits in the field will
     *                  be set.
     *
     *  K_xxx           "Code" constant (value for data in a multi-bit
     *                  field).  The value is right justified.
     *
-    *  V_xxx           "Value" constant.  This is the same as the 
+    *  V_xxx           "Value" constant.  This is the same as the
     *                  corresponding "K_xxx" constant, except it is
     *                  shifted to the correct position in the register.
     *
     *  S_xxx           SHIFT constant.  This is the number of bits that
-    *                  a field value (code) needs to be shifted 
+    *                  a field value (code) needs to be shifted
     *                  (towards the left) to put the value in the right
     *                  position for the register.
     *
-    *  A_xxx           ADDRESS constant.  This will be a physical 
+    *  A_xxx           ADDRESS constant.  This will be a physical
     *                  address.  Use the PHYS_TO_K1 macro to generate
     *                  a K1SEG address.