diff options
author | Jani Nikula <jani.nikula@intel.com> | 2020-01-27 20:26:06 +0200 |
---|---|---|
committer | Jani Nikula <jani.nikula@intel.com> | 2020-01-29 10:45:43 +0200 |
commit | dc008bf0aa091c33caa76ea9d262f4ddffb054a7 (patch) | |
tree | b18741e98bd5288a8e87b89875429738e498221c /drivers | |
parent | f7960e7f8f24328bb20120b3a4c398bb937322b5 (diff) |
drm/i915/display: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/41b937d632edb59ca2ddecefd9ac613c2f998d58.1580149467.git.jani.nikula@intel.com
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 1171 |
1 files changed, 622 insertions, 549 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7f94d5ca4207..c0e5002ce64c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -519,13 +519,11 @@ static void skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) { if (enable) - I915_WRITE(CLKGATE_DIS_PSL(pipe), - I915_READ(CLKGATE_DIS_PSL(pipe)) | - DUPS1_GATING_DIS | DUPS2_GATING_DIS); + intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); else - I915_WRITE(CLKGATE_DIS_PSL(pipe), - I915_READ(CLKGATE_DIS_PSL(pipe)) & - ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); + intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); } /* Wa_2006604312:icl */ @@ -534,11 +532,11 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) { if (enable) - I915_WRITE(CLKGATE_DIS_PSL(pipe), - I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); + intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); else - I915_WRITE(CLKGATE_DIS_PSL(pipe), - I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); + intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); } static bool @@ -1050,9 +1048,9 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, else line_mask = DSL_LINEMASK_GEN3; - line1 = I915_READ(reg) & line_mask; + line1 = intel_de_read(dev_priv, reg) & line_mask; msleep(5); - line2 = I915_READ(reg) & line_mask; + line2 = intel_de_read(dev_priv, reg) & line_mask; return line1 != line2; } @@ -1105,7 +1103,7 @@ void assert_pll(struct drm_i915_private *dev_priv, u32 val; bool cur_state; - val = I915_READ(DPLL(pipe)); + val = intel_de_read(dev_priv, DPLL(pipe)); cur_state = !!(val & DPLL_VCO_ENABLE); I915_STATE_WARN(cur_state != state, "PLL state assertion failure (expected %s, current %s)\n", @@ -1141,10 +1139,11 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv, * so pipe->transcoder cast is fine here. */ enum transcoder cpu_transcoder = (enum transcoder)pipe; - u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); + u32 val = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(cpu_transcoder)); cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); } else { - u32 val = I915_READ(FDI_TX_CTL(pipe)); + u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)); cur_state = !!(val & FDI_TX_ENABLE); } I915_STATE_WARN(cur_state != state, @@ -1160,7 +1159,7 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv, u32 val; bool cur_state; - val = I915_READ(FDI_RX_CTL(pipe)); + val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); cur_state = !!(val & FDI_RX_ENABLE); I915_STATE_WARN(cur_state != state, "FDI RX state assertion failure (expected %s, current %s)\n", @@ -1182,7 +1181,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, if (HAS_DDI(dev_priv)) return; - val = I915_READ(FDI_TX_CTL(pipe)); + val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)); I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); } @@ -1192,7 +1191,7 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, u32 val; bool cur_state; - val = I915_READ(FDI_RX_CTL(pipe)); + val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); cur_state = !!(val & FDI_RX_PLL_ENABLE); I915_STATE_WARN(cur_state != state, "FDI RX PLL assertion failure (expected %s, current %s)\n", @@ -1213,7 +1212,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) u32 port_sel; pp_reg = PP_CONTROL(0); - port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; + port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; switch (port_sel) { case PANEL_PORT_SELECT_LVDS: @@ -1240,13 +1239,13 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) u32 port_sel; pp_reg = PP_CONTROL(0); - port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; + port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS); intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe); } - val = I915_READ(pp_reg); + val = intel_de_read(dev_priv, pp_reg); if (!(val & PANEL_POWER_ON) || ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) locked = false; @@ -1270,7 +1269,7 @@ void assert_pipe(struct drm_i915_private *dev_priv, power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); if (wakeref) { - u32 val = I915_READ(PIPECONF(cpu_transcoder)); + u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); cur_state = !!(val & PIPECONF_ENABLE); intel_display_power_put(dev_priv, power_domain, wakeref); @@ -1320,7 +1319,7 @@ void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, u32 val; bool enabled; - val = I915_READ(PCH_TRANSCONF(pipe)); + val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); enabled = !!(val & TRANS_ENABLE); I915_STATE_WARN(enabled, "transcoder assertion failed, should be off on pipe %c but is still active\n", @@ -1394,8 +1393,8 @@ static void _vlv_enable_pll(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); - POSTING_READ(DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); + intel_de_posting_read(dev_priv, DPLL(pipe)); udelay(150); if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) @@ -1416,8 +1415,9 @@ static void vlv_enable_pll(struct intel_crtc *crtc, if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) _vlv_enable_pll(crtc, pipe_config); - I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); - POSTING_READ(DPLL_MD(pipe)); + intel_de_write(dev_priv, DPLL_MD(pipe), + pipe_config->dpll_hw_state.dpll_md); + intel_de_posting_read(dev_priv, DPLL_MD(pipe)); } @@ -1444,7 +1444,7 @@ static void _chv_enable_pll(struct intel_crtc *crtc, udelay(1); /* Enable PLL */ - I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); + intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); /* Check PLL is locked */ if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) @@ -1472,19 +1472,21 @@ static void chv_enable_pll(struct intel_crtc *crtc, * DPLLCMD is AWOL. Use chicken bits to propagate * the value from DPLLBMD to either pipe B or C. */ - I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); - I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); - I915_WRITE(CBR4_VLV, 0); + intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); + intel_de_write(dev_priv, DPLL_MD(PIPE_B), + pipe_config->dpll_hw_state.dpll_md); + intel_de_write(dev_priv, CBR4_VLV, 0); dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; /* * DPLLB VGA mode also seems to cause problems. * We should always have it disabled. */ - WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); + WARN_ON((intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); } else { - I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); - POSTING_READ(DPLL_MD(pipe)); + intel_de_write(dev_priv, DPLL_MD(pipe), + pipe_config->dpll_hw_state.dpll_md); + intel_de_posting_read(dev_priv, DPLL_MD(pipe)); } } @@ -1515,29 +1517,29 @@ static void i9xx_enable_pll(struct intel_crtc *crtc, * the P1/P2 dividers. Otherwise the DPLL will keep using the old * dividers, even though the register value does change. */ - I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS); - I915_WRITE(reg, dpll); + intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS); + intel_de_write(dev_priv, reg, dpll); /* Wait for the clocks to stabilize. */ - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); if (INTEL_GEN(dev_priv) >= 4) { - I915_WRITE(DPLL_MD(crtc->pipe), - crtc_state->dpll_hw_state.dpll_md); + intel_de_write(dev_priv, DPLL_MD(crtc->pipe), + crtc_state->dpll_hw_state.dpll_md); } else { /* The pixel multiplier can only be updated once the * DPLL is enabled and the clocks are stable. * * So write it again. */ - I915_WRITE(reg, dpll); + intel_de_write(dev_priv, reg, dpll); } /* We do this three times for luck */ for (i = 0; i < 3; i++) { - I915_WRITE(reg, dpll); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, dpll); + intel_de_posting_read(dev_priv, reg); udelay(150); /* wait for warmup */ } } @@ -1555,8 +1557,8 @@ static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) /* Make sure the pipe isn't still relying on us */ assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); - I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); - POSTING_READ(DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); + intel_de_posting_read(dev_priv, DPLL(pipe)); } static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) @@ -1571,8 +1573,8 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; - I915_WRITE(DPLL(pipe), val); - POSTING_READ(DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), val); + intel_de_posting_read(dev_priv, DPLL(pipe)); } static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) @@ -1588,8 +1590,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; - I915_WRITE(DPLL(pipe), val); - POSTING_READ(DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), val); + intel_de_posting_read(dev_priv, DPLL(pipe)); vlv_dpio_get(dev_priv); @@ -1630,7 +1632,8 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, port_mask, expected_mask, 1000)) WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", dport->base.base.base.id, dport->base.base.name, - I915_READ(dpll_reg) & port_mask, expected_mask); + intel_de_read(dev_priv, dpll_reg) & port_mask, + expected_mask); } static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) @@ -1650,7 +1653,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) if (HAS_PCH_CPT(dev_priv)) { reg = TRANS_CHICKEN2(pipe); - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); /* * Workaround: Set the timing override bit * before enabling the pch transcoder. @@ -1659,12 +1662,12 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) /* Configure frame start delay to match the CPU */ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } reg = PCH_TRANSCONF(pipe); - val = I915_READ(reg); - pipeconf_val = I915_READ(PIPECONF(pipe)); + val = intel_de_read(dev_priv, reg); + pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); if (HAS_PCH_IBX(dev_priv)) { /* Configure frame start delay to match the CPU */ @@ -1694,7 +1697,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) val |= TRANS_PROGRESSIVE; } - I915_WRITE(reg, val | TRANS_ENABLE); + intel_de_write(dev_priv, reg, val | TRANS_ENABLE); if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) drm_err(&dev_priv->drm, "failed to enable transcoder %c\n", pipe_name(pipe)); @@ -1709,16 +1712,16 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); assert_fdi_rx_enabled(dev_priv, PIPE_A); - val = I915_READ(TRANS_CHICKEN2(PIPE_A)); + val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); /* Workaround: set timing override bit. */ val |= TRANS_CHICKEN2_TIMING_OVERRIDE; /* Configure frame start delay to match the CPU */ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); - I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); + intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); val = TRANS_ENABLE; - pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); + pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACED_ILK) @@ -1726,7 +1729,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, else val |= TRANS_PROGRESSIVE; - I915_WRITE(LPT_TRANSCONF, val); + intel_de_write(dev_priv, LPT_TRANSCONF, val); if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, TRANS_STATE_ENABLE, 100)) drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); @@ -1746,9 +1749,9 @@ static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv, assert_pch_ports_disabled(dev_priv, pipe); reg = PCH_TRANSCONF(pipe); - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); val &= ~TRANS_ENABLE; - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); /* wait for PCH transcoder off, transcoder state */ if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", @@ -1757,9 +1760,9 @@ static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv, if (HAS_PCH_CPT(dev_priv)) { /* Workaround: Clear the timing override chicken bit again. */ reg = TRANS_CHICKEN2(pipe); - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } } @@ -1767,18 +1770,18 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) { u32 val; - val = I915_READ(LPT_TRANSCONF); + val = intel_de_read(dev_priv, LPT_TRANSCONF); val &= ~TRANS_ENABLE; - I915_WRITE(LPT_TRANSCONF, val); + intel_de_write(dev_priv, LPT_TRANSCONF, val); /* wait for PCH transcoder off, transcoder state */ if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, TRANS_STATE_ENABLE, 50)) drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); /* Workaround: clear timing override bit. */ - val = I915_READ(TRANS_CHICKEN2(PIPE_A)); + val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; - I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); + intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); } enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) @@ -1866,15 +1869,15 @@ static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) trace_intel_pipe_enable(crtc); reg = PIPECONF(cpu_transcoder); - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); if (val & PIPECONF_ENABLE) { /* we keep both pipes enabled on 830 */ WARN_ON(!IS_I830(dev_priv)); return; } - I915_WRITE(reg, val | PIPECONF_ENABLE); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); + intel_de_posting_read(dev_priv, reg); /* * Until the pipe starts PIPEDSL reads will return a stale value, @@ -1907,7 +1910,7 @@ void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) trace_intel_pipe_disable(crtc); reg = PIPECONF(cpu_transcoder); - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); if ((val & PIPECONF_ENABLE) == 0) return; @@ -1922,7 +1925,7 @@ void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) if (!IS_I830(dev_priv)) val &= ~PIPECONF_ENABLE; - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); if ((val & PIPECONF_ENABLE) == 0) intel_wait_for_pipe_off(old_crtc_state); } @@ -4349,7 +4352,8 @@ static void i9xx_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), + plane_state->color_plane[0].stride); if (INTEL_GEN(dev_priv) < 4) { /* @@ -4357,21 +4361,26 @@ static void i9xx_update_plane(struct intel_plane *plane, * generator but let's assume we still need to * program whatever is there. */ - I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(DSPSIZE(i9xx_plane), - ((crtc_h - 1) << 16) | (crtc_w - 1)); + intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), + ((crtc_h - 1) << 16) | (crtc_w - 1)); } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { - I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(PRIMSIZE(i9xx_plane), - ((crtc_h - 1) << 16) | (crtc_w - 1)); - I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0); + intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), + ((crtc_h - 1) << 16) | (crtc_w - 1)); + intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); } if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x); + intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), + (y << 16) | x); } else if (INTEL_GEN(dev_priv) >= 4) { - I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset); - I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x); + intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), + linear_offset); + intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), + (y << 16) | x); } /* @@ -4379,15 +4388,13 @@ static void i9xx_update_plane(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE_FW(DSPSURF(i9xx_plane), - intel_plane_ggtt_offset(plane_state) + - dspaddr_offset); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else - I915_WRITE_FW(DSPADDR(i9xx_plane), - intel_plane_ggtt_offset(plane_state) + - dspaddr_offset); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -4414,11 +4421,11 @@ static void i9xx_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE_FW(DSPSURF(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); else - I915_WRITE_FW(DSPADDR(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -4443,7 +4450,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - val = I915_READ(DSPCNTR(i9xx_plane)); + val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); ret = val & DISPLAY_PLANE_ENABLE; @@ -4463,9 +4470,9 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) struct drm_device *dev = intel_crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); - I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); - I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); + intel_de_write(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0); + intel_de_write(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); + intel_de_write(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); } /* @@ -4938,7 +4945,7 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc) enum pipe pipe = crtc->pipe; u32 tmp; - tmp = I915_READ(PIPE_CHICKEN(pipe)); + tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); /* * Display WA #1153: icl @@ -4953,7 +4960,7 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc) * across pipe */ tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; - I915_WRITE(PIPE_CHICKEN(pipe), tmp); + intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); } static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state) @@ -4982,8 +4989,9 @@ static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state /* Enable Transcoder Port Sync */ trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE; - I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder), - trans_ddi_func_ctl2_val); + intel_de_write(dev_priv, + TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder), + trans_ddi_func_ctl2_val); } static void intel_fdi_normal_train(struct intel_crtc *crtc) @@ -4996,7 +5004,7 @@ static void intel_fdi_normal_train(struct intel_crtc *crtc) /* enable normal train */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); if (IS_IVYBRIDGE(dev_priv)) { temp &= ~FDI_LINK_TRAIN_NONE_IVB; temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; @@ -5004,10 +5012,10 @@ static void intel_fdi_normal_train(struct intel_crtc *crtc) temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; } - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_NORMAL_CPT; @@ -5015,16 +5023,16 @@ static void intel_fdi_normal_train(struct intel_crtc *crtc) temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_NONE; } - I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); /* wait one idle pattern time */ - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(1000); /* IVB wants error correction enabled */ if (IS_IVYBRIDGE(dev_priv)) - I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | - FDI_FE_ERRC_ENABLE); + intel_de_write(dev_priv, reg, + intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); } /* The FDI link training functions for ILK/Ibexpeak. */ @@ -5043,44 +5051,45 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc, /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ reg = FDI_RX_IMR(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_RX_SYMBOL_LOCK; temp &= ~FDI_RX_BIT_LOCK; - I915_WRITE(reg, temp); - I915_READ(reg); + intel_de_write(dev_priv, reg, temp); + intel_de_read(dev_priv, reg); udelay(150); /* enable CPU FDI TX and PCH FDI RX */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; - I915_WRITE(reg, temp | FDI_TX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; - I915_WRITE(reg, temp | FDI_RX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); /* Ironlake workaround, enable clock pointer after FDI enable*/ - I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); - I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | - FDI_RX_PHASE_SYNC_POINTER_EN); + intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), + FDI_RX_PHASE_SYNC_POINTER_OVR); + intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), + FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN); reg = FDI_RX_IIR(pipe); for (tries = 0; tries < 5; tries++) { - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if ((temp & FDI_RX_BIT_LOCK)) { drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n"); - I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); + intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK); break; } } @@ -5089,27 +5098,28 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc, /* Train 2 */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); reg = FDI_RX_IIR(pipe); for (tries = 0; tries < 5; tries++) { - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_SYMBOL_LOCK) { - I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); + intel_de_write(dev_priv, reg, + temp | FDI_RX_SYMBOL_LOCK); drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n"); break; } @@ -5141,17 +5151,17 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ reg = FDI_RX_IMR(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_RX_SYMBOL_LOCK; temp &= ~FDI_RX_BIT_LOCK; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); /* enable CPU FDI TX and PCH FDI RX */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); temp &= ~FDI_LINK_TRAIN_NONE; @@ -5159,13 +5169,13 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; /* SNB-B */ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; - I915_WRITE(reg, temp | FDI_TX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); - I915_WRITE(FDI_RX_MISC(pipe), - FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); + intel_de_write(dev_priv, FDI_RX_MISC(pipe), + FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; @@ -5173,27 +5183,28 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; } - I915_WRITE(reg, temp | FDI_RX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); for (i = 0; i < 4; i++) { reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp |= snb_b_fdi_train_param[i]; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(500); for (retry = 0; retry < 5; retry++) { reg = FDI_RX_IIR(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_BIT_LOCK) { - I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); + intel_de_write(dev_priv, reg, + temp | FDI_RX_BIT_LOCK); drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n"); break; @@ -5208,7 +5219,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, /* Train 2 */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; if (IS_GEN(dev_priv, 6)) { @@ -5216,10 +5227,10 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, /* SNB-B */ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; } - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; @@ -5227,27 +5238,28 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; } - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); for (i = 0; i < 4; i++) { reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp |= snb_b_fdi_train_param[i]; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(500); for (retry = 0; retry < 5; retry++) { reg = FDI_RX_IIR(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_SYMBOL_LOCK) { - I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); + intel_de_write(dev_priv, reg, + temp | FDI_RX_SYMBOL_LOCK); drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n"); break; @@ -5276,64 +5288,65 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ reg = FDI_RX_IMR(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_RX_SYMBOL_LOCK; temp &= ~FDI_RX_BIT_LOCK; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n", - I915_READ(FDI_RX_IIR(pipe))); + intel_de_read(dev_priv, FDI_RX_IIR(pipe))); /* Try each vswing and preemphasis setting twice before moving on */ for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { /* disable first in case we need to retry */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); temp &= ~FDI_TX_ENABLE; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_AUTO; temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp &= ~FDI_RX_ENABLE; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); /* enable CPU FDI TX and PCH FDI RX */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp |= snb_b_fdi_train_param[j/2]; temp |= FDI_COMPOSITE_SYNC; - I915_WRITE(reg, temp | FDI_TX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); - I915_WRITE(FDI_RX_MISC(pipe), - FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); + intel_de_write(dev_priv, FDI_RX_MISC(pipe), + FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; temp |= FDI_COMPOSITE_SYNC; - I915_WRITE(reg, temp | FDI_RX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(1); /* should be 0.5us */ for (i = 0; i < 4; i++) { reg = FDI_RX_IIR(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_BIT_LOCK || - (I915_READ(reg) & FDI_RX_BIT_LOCK)) { - I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); + (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) { + intel_de_write(dev_priv, reg, + temp | FDI_RX_BIT_LOCK); drm_dbg_kms(&dev_priv->drm, "FDI train 1 done, level %i.\n", i); @@ -5349,28 +5362,29 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, /* Train 2 */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE_IVB; temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(2); /* should be 1.5us */ for (i = 0; i < 4; i++) { reg = FDI_RX_IIR(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_SYMBOL_LOCK || - (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { - I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); + (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) { + intel_de_write(dev_priv, reg, + temp | FDI_RX_SYMBOL_LOCK); drm_dbg_kms(&dev_priv->drm, "FDI train 2 done, level %i.\n", i); @@ -5397,29 +5411,29 @@ static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); - temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; - I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); + temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; + intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(200); /* Switch from Rawclk to PCDclk */ - temp = I915_READ(reg); - I915_WRITE(reg, temp | FDI_PCDCLK); + temp = intel_de_read(dev_priv, reg); + intel_de_write(dev_priv, reg, temp | FDI_PCDCL |