staging: et131x: Put all .c files into one big file

Created one big .c file for the driver, moving the contents of all
driver .c files into it.

Signed-off-by: Mark Einon <mark.einon@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

13 files changed, 5102 insertions, 5862 deletions

diff --git a/drivers/staging/et131x/Makefile b/drivers/staging/et131x/Makefile
index 5ea0272fc7ad..027ff9453fe1 100644
--- a/drivers/staging/et131x/Makefile
+++ b/drivers/staging/et131x/Makefile
@@ -3,14 +3,3 @@
 #
 
 obj-$(CONFIG_ET131X) += et131x.o
-
-et131x-y :=	et1310_eeprom.o \
-		et1310_mac.o \
-		et1310_phy.o \
-		et1310_pm.o \
-		et1310_rx.o \
-		et1310_tx.o \
-		et131x_initpci.o \
-		et131x_ethtool.o \
-		et131x_isr.o \
-		et131x_netdev.o
diff --git a/drivers/staging/et131x/et1310_eeprom.c b/drivers/staging/et131x/et1310_eeprom.c
deleted file mode 100644
index 20b96605e4c0..000000000000
--- a/drivers/staging/et131x/et1310_eeprom.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * Agere Systems Inc.
- * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *   http://www.agere.com
- *
- * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
- *
- *------------------------------------------------------------------------------
- *
- * et1310_eeprom.c - Code used to access the device's EEPROM
- *
- *------------------------------------------------------------------------------
- *
- * SOFTWARE LICENSE
- *
- * This software is provided subject to the following terms and conditions,
- * which you should read carefully before using the software.  Using this
- * software indicates your acceptance of these terms and conditions.  If you do
- * not agree with these terms and conditions, do not use the software.
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *
- * Redistribution and use in source or binary forms, with or without
- * modifications, are permitted provided that the following conditions are met:
- *
- * . Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following Disclaimer as comments in the code as
- *    well as in the documentation and/or other materials provided with the
- *    distribution.
- *
- * . Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following Disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * . Neither the name of Agere Systems Inc. nor the names of the contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * Disclaimer
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGE.
- *
- */
-
-#include "et131x_defs.h"
-
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include <linux/sched.h>
-#include <linux/ptrace.h>
-#include <linux/ctype.h>
-#include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/interrupt.h>
-#include <linux/in.h>
-#include <linux/delay.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <asm/system.h>
-
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/if_arp.h>
-#include <linux/ioport.h>
-
-#include "et1310_phy.h"
-#include "et131x_adapter.h"
-#include "et131x.h"
-
-/*
- * EEPROM Defines
- */
-
-/* LBCIF Register Groups (addressed via 32-bit offsets) */
-#define LBCIF_DWORD0_GROUP       0xAC
-#define LBCIF_DWORD1_GROUP       0xB0
-
-/* LBCIF Registers (addressed via 8-bit offsets) */
-#define LBCIF_ADDRESS_REGISTER   0xAC
-#define LBCIF_DATA_REGISTER      0xB0
-#define LBCIF_CONTROL_REGISTER   0xB1
-#define LBCIF_STATUS_REGISTER    0xB2
-
-/* LBCIF Control Register Bits */
-#define LBCIF_CONTROL_SEQUENTIAL_READ   0x01
-#define LBCIF_CONTROL_PAGE_WRITE        0x02
-#define LBCIF_CONTROL_EEPROM_RELOAD     0x08
-#define LBCIF_CONTROL_TWO_BYTE_ADDR     0x20
-#define LBCIF_CONTROL_I2C_WRITE         0x40
-#define LBCIF_CONTROL_LBCIF_ENABLE      0x80
-
-/* LBCIF Status Register Bits */
-#define LBCIF_STATUS_PHY_QUEUE_AVAIL    0x01
-#define LBCIF_STATUS_I2C_IDLE           0x02
-#define LBCIF_STATUS_ACK_ERROR          0x04
-#define LBCIF_STATUS_GENERAL_ERROR      0x08
-#define LBCIF_STATUS_CHECKSUM_ERROR     0x40
-#define LBCIF_STATUS_EEPROM_PRESENT     0x80
-
-/* Miscellaneous Constraints */
-#define MAX_NUM_REGISTER_POLLS          1000
-#define MAX_NUM_WRITE_RETRIES           2
-
-static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
-{
-	u32 reg;
-	int i;
-
-	/*
-	 * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
-	 *    bits 7,1:0 both equal to 1, at least once after reset.
-	 *    Subsequent operations need only to check that bits 1:0 are equal
-	 *    to 1 prior to starting a single byte read/write
-	 */
-
-	for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
-		/* Read registers grouped in DWORD1 */
-		if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, &reg))
-			return -EIO;
-
-		/* I2C idle and Phy Queue Avail both true */
-		if ((reg & 0x3000) == 0x3000) {
-			if (status)
-				*status = reg;
-			return reg & 0xFF;
-		}
-	}
-	return -ETIMEDOUT;
-}
-
-
-/**
- * eeprom_write - Write a byte to the ET1310's EEPROM
- * @adapter: pointer to our private adapter structure
- * @addr: the address to write
- * @data: the value to write
- *
- * Returns 1 for a successful write.
- */
-static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
-{
-	struct pci_dev *pdev = adapter->pdev;
-	int index = 0;
-	int retries;
-	int err = 0;
-	int i2c_wack = 0;
-	int writeok = 0;
-	u32 status;
-	u32 val = 0;
-
-	/*
-	 * For an EEPROM, an I2C single byte write is defined as a START
-	 * condition followed by the device address, EEPROM address, one byte
-	 * of data and a STOP condition.  The STOP condition will trigger the
-	 * EEPROM's internally timed write cycle to the nonvolatile memory.
-	 * All inputs are disabled during this write cycle and the EEPROM will
-	 * not respond to any access until the internal write is complete.
-	 */
-
-	err = eeprom_wait_ready(pdev, NULL);
-	if (err)
-		return err;
-
-	 /*
-	 * 2. Write to the LBCIF Control Register:  bit 7=1, bit 6=1, bit 3=0,
-	 *    and bits 1:0 both =0.  Bit 5 should be set according to the
-	 *    type of EEPROM being accessed (1=two byte addressing, 0=one
-	 *    byte addressing).
-	 */
-	if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
-			LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
-		return -EIO;
-
-	i2c_wack = 1;
-
-	/* Prepare EEPROM address for Step 3 */
-
-	for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
-		/* Write the address to the LBCIF Address Register */
-		if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
-			break;
-		/*
-		 * Write the data to the LBCIF Data Register (the I2C write
-		 * will begin).
-		 */
-		if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
-			break;
-		/*
-		 * Monitor bit 1:0 of the LBCIF Status Register.  When bits
-		 * 1:0 are both equal to 1, the I2C write has completed and the
-		 * internal write cycle of the EEPROM is about to start.
-		 * (bits 1:0 = 01 is a legal state while waiting from both
-		 * equal to 1, but bits 1:0 = 10 is invalid and implies that
-		 * something is broken).
-		 */
-		err = eeprom_wait_ready(pdev, &status);
-		if (err < 0)
-			return 0;
-
-		/*
-		 * Check bit 3 of the LBCIF Status Register.  If  equal to 1,
-		 * an error has occurred.Don't break here if we are revision
-		 * 1, this is so we do a blind write for load bug.
-		 */
-		if ((status & LBCIF_STATUS_GENERAL_ERROR)
-			&& adapter->pdev->revision == 0)
-			break;
-
-		/*
-		 * Check bit 2 of the LBCIF Status Register.  If equal to 1 an
-		 * ACK error has occurred on the address phase of the write.
-		 * This could be due to an actual hardware failure or the
-		 * EEPROM may still be in its internal write cycle from a
-		 * previous write. This write operation was ignored and must be
-		  *repeated later.
-		 */
-		if (status & LBCIF_STATUS_ACK_ERROR) {
-			/*
-			 * This could be due to an actual hardware failure
-			 * or the EEPROM may still be in its internal write
-			 * cycle from a previous write. This write operation
-			 * was ignored and must be repeated later.
-			 */
-			udelay(10);
-			continue;
-		}
-
-		writeok = 1;
-		break;
-	}
-
-	/*
-	 * Set bit 6 of the LBCIF Control Register = 0.
-	 */
-	udelay(10);
-
-	while (i2c_wack) {
-		if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
-			LBCIF_CONTROL_LBCIF_ENABLE))
-			writeok = 0;
-
-		/* Do read until internal ACK_ERROR goes away meaning write
-		 * completed
-		 */
-		do {
-			pci_write_config_dword(pdev,
-					       LBCIF_ADDRESS_REGISTER,
-					       addr);
-			do {
-				pci_read_config_dword(pdev,
-					LBCIF_DATA_REGISTER, &val);
-			} while ((val & 0x00010000) == 0);
-		} while (val & 0x00040000);
-
-		if ((val & 0xFF00) != 0xC000 || index == 10000)
-			break;
-		index++;
-	}
-	return writeok ? 0 : -EIO;
-}
-
-/**
- * eeprom_read - Read a byte from the ET1310's EEPROM
- * @adapter: pointer to our private adapter structure
- * @addr: the address from which to read
- * @pdata: a pointer to a byte in which to store the value of the read
- * @eeprom_id: the ID of the EEPROM
- * @addrmode: how the EEPROM is to be accessed
- *
- * Returns 1 for a successful read
- */
-static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
-{
-	struct pci_dev *pdev = adapter->pdev;
-	int err;
-	u32 status;
-
-	/*
-	 * A single byte read is similar to the single byte write, with the
-	 * exception of the data flow:
-	 */
-
-	err = eeprom_wait_ready(pdev, NULL);
-	if (err)
-		return err;
-	/*
-	 * Write to the LBCIF Control Register:  bit 7=1, bit 6=0, bit 3=0,
-	 * and bits 1:0 both =0.  Bit 5 should be set according to the type
-	 * of EEPROM being accessed (1=two byte addressing, 0=one byte
-	 * addressing).
-	 */
-	if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
-				  LBCIF_CONTROL_LBCIF_ENABLE))
-		return -EIO;
-	/*
-	 * Write the address to the LBCIF Address Register (I2C read will
-	 * begin).
-	 */
-	if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
-		return -EIO;
-	/*
-	 * Monitor bit 0 of the LBCIF Status Register.  When = 1, I2C read
-	 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
-	 * has occurred).
-	 */
-	err = eeprom_wait_ready(pdev, &status);
-	if (err < 0)
-		return err;
-	/*
-	 * Regardless of error status, read data byte from LBCIF Data
-	 * Register.
-	 */
-	*pdata = err;
-	/*
-	 * Check bit 2 of the LBCIF Status Register.  If = 1,
-	 * then an error has occurred.
-	 */
-	return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
-}
-
-int et131x_init_eeprom(struct et131x_adapter *adapter)
-{
-	struct pci_dev *pdev = adapter->pdev;
-	u8 eestatus;
-
-	/* We first need to check the EEPROM Status code located at offset
-	 * 0xB2 of config space
-	 */
-	pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
-				      &eestatus);
-
-	/* THIS IS A WORKAROUND:
-	 * I need to call this function twice to get my card in a
-	 * LG M1 Express Dual running. I tried also a msleep before this
-	 * function, because I thougth there could be some time condidions
-	 * but it didn't work. Call the whole function twice also work.
-	 */
-	if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
-		dev_err(&pdev->dev,
-		       "Could not read PCI config space for EEPROM Status\n");
-		return -EIO;
-	}
-
-	/* Determine if the error(s) we care about are present. If they are
-	 * present we need to fail.
-	 */
-	if (eestatus & 0x4C) {
-		int write_failed = 0;
-		if (pdev->revision == 0x01) {
-			int	i;
-			static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
-
-			/* Re-write the first 4 bytes if we have an eeprom
-			 * present and the revision id is 1, this fixes the
-			 * corruption seen with 1310 B Silicon
-			 */
-			for (i = 0; i < 3; i++)
-				if (eeprom_write(adapter, i, eedata[i]) < 0)
-					write_failed = 1;
-		}
-		if (pdev->revision  != 0x01 || write_failed) {
-			dev_err(&pdev->dev,
-			    "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
-
-			/* This error could mean that there was an error
-			 * reading the eeprom or that the eeprom doesn't exist.
-			 * We will treat each case the same and not try to
-			 * gather additional information that normally would
-			 * come from the eeprom, like MAC Address
-			 */
-			adapter->has_eeprom = 0;
-			return -EIO;
-		}
-	}
-	adapter->has_eeprom = 1;
-
-	/* Read the EEPROM for information regarding LED behavior. Refer to
-	 * ET1310_phy.c, et131x_xcvr_init(), for its use.
-	 */
-	eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
-	eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
-
-	if (adapter->eeprom_data[0] != 0xcd)
-		/* Disable all optional features */
-		adapter->eeprom_data[1] = 0x00;
-
-	return 0;
-}
diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c
deleted file mode 100644
index 65179a364b74..000000000000
--- a/drivers/staging/et131x/et1310_mac.c
+++ /dev/null
@@ -1,654 +0,0 @@
-/*
- * Agere Systems Inc.
- * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *   http://www.agere.com
- *
- * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
- *
- *------------------------------------------------------------------------------
- *
- * et1310_mac.c - All code and routines pertaining to the MAC
- *
- *------------------------------------------------------------------------------
- *
- * SOFTWARE LICENSE
- *
- * This software is provided subject to the following terms and conditions,
- * which you should read carefully before using the software.  Using this
- * software indicates your acceptance of these terms and conditions.  If you do
- * not agree with these terms and conditions, do not use the software.
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *
- * Redistribution and use in source or binary forms, with or without
- * modifications, are permitted provided that the following conditions are met:
- *
- * . Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following Disclaimer as comments in the code as
- *    well as in the documentation and/or other materials provided with the
- *    distribution.
- *
- * . Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following Disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * . Neither the name of Agere Systems Inc. nor the names of the contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * Disclaimer
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGE.
- *
- */
-
-#include "et131x_defs.h"
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include <linux/sched.h>
-#include <linux/ptrace.h>
-#include <linux/ctype.h>
-#include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/interrupt.h>
-#include <linux/in.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/bitops.h>
-#include <linux/pci.h>
-#include <asm/system.h>
-
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/if_arp.h>
-#include <linux/ioport.h>
-#include <linux/crc32.h>
-#include <linux/phy.h>
-
-#include "et1310_phy.h"
-#include "et131x_adapter.h"
-#include "et131x.h"
-
-#define COUNTER_WRAP_16_BIT 0x10000
-#define COUNTER_WRAP_12_BIT 0x1000
-
-/**
- * et1310_config_mac_regs1 - Initialize the first part of MAC regs
- * @adapter: pointer to our adapter structure
- */
-void et1310_config_mac_regs1(struct et131x_adapter *adapter)
-{
-	struct mac_regs __iomem *macregs = &adapter->regs->mac;
-	u32 station1;
-	u32 station2;
-	u32 ipg;
-
-	/* First we need to reset everything.  Write to MAC configuration
-	 * register 1 to perform reset.
-	 */
-	writel(0xC00F0000, &macregs->cfg1);
-
-	/* Next lets configure the MAC Inter-packet gap register */
-	ipg = 0x38005860;		/* IPG1 0x38 IPG2 0x58 B2B 0x60 */
-	ipg |= 0x50 << 8;		/* ifg enforce 0x50 */
-	writel(ipg, &macregs->ipg);
-
-	/* Next lets configure the MAC Half Duplex register */
-	/* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
-	writel(0x00A1F037, &macregs->hfdp);
-
-	/* Next lets configure the MAC Interface Control register */
-	writel(0, &macregs->if_ctrl);
-
-	/* Let's move on to setting up the mii management configuration */
-	writel(0x07, &macregs->mii_mgmt_cfg);	/* Clock reset 0x7 */
-
-	/* Next lets configure the MAC Station Address register.  These
-	 * values are read from the EEPROM during initialization and stored
-	 * in the adapter structure.  We write what is stored in the adapter
-	 * structure to the MAC Station Address registers high and low.  This
-	 * station address is used for generating and checking pause control
-	 * packets.
-	 */
-	station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
-		   (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
-	station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
-		   (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
-		   (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
-		    adapter->addr[2];
-	writel(station1, &macregs->station_addr_1);
-	writel(station2, &macregs->station_addr_2);
-
-	/* Max ethernet packet in bytes that will passed by the mac without
-	 * being truncated.  Allow the MAC to pass 4 more than our max packet
-	 * size.  This is 4 for the Ethernet CRC.
-	 *
-	 * Packets larger than (registry_jumbo_packet) that do not contain a
-	 * VLAN ID will be dropped by the Rx function.
-	 */
-	writel(adapter->registry_jumbo_packet + 4, &macregs->max_fm_len);
-
-	/* clear out MAC config reset */
-	writel(0, &macregs->cfg1);
-}
-
-/**
- * et1310_config_mac_regs2 - Initialize the second part of MAC regs
- * @adapter: pointer to our adapter structure
- */
-void et1310_config_mac_regs2(struct et131x_adapter *adapter)
-{
-	int32_t delay = 0;
-	struct mac_regs __iomem *mac = &adapter->regs->mac;
-	struct phy_device *phydev = adapter->phydev;
-	u32 cfg1;
-	u32 cfg2;
-	u32 ifctrl;
-	u32 ctl;
-
-	ctl = readl(&adapter->regs->txmac.ctl);
-	cfg1 = readl(&mac->cfg1);
-	cfg2 = readl(&mac->cfg2);
-	ifctrl = readl(&mac->if_ctrl);
-
-	/* Set up the if mode bits */
-	cfg2 &= ~0x300;
-	if (phydev && phydev->speed == SPEED_1000) {
-		cfg2 |= 0x200;
-		/* Phy mode bit */
-		ifctrl &= ~(1 << 24);
-	} else {
-		cfg2 |= 0x100;
-		ifctrl |= (1 << 24);
-	}
-
-	/* We need to enable Rx/Tx */
-	cfg1 |= CFG1_RX_ENABLE | CFG1_TX_ENABLE | CFG1_TX_FLOW;
-	/* Initialize loop back to off */
-	cfg1 &= ~(CFG1_LOOPBACK | CFG1_RX_FLOW);
-	if (adapter->flowcontrol == FLOW_RXONLY ||
-				adapter->flowcontrol == FLOW_BOTH)
-		cfg1 |= CFG1_RX_FLOW;
-	writel(cfg1, &mac->cfg1);
-
-	/* Now we need to initialize the MAC Configuration 2 register */
-	/* preamble 7, check length, huge frame off, pad crc, crc enable
-	   full duplex off */
-	cfg2 |= 0x7016;
-	cfg2 &= ~0x0021;
-
-	/* Turn on duplex if needed */
-	if (phydev && phydev->duplex == DUPLEX_FULL)
-		cfg2 |= 0x01;
-
-	ifctrl &= ~(1 << 26);
-	if (phydev && phydev->duplex == DUPLEX_HALF)
-		ifctrl |= (1<<26);	/* Enable ghd */
-
-	writel(ifctrl, &mac->if_ctrl);
-	writel(cfg2, &mac->cfg2);
-
-	do {
-		udelay(10);
-		delay++;
-		cfg1 = readl(&mac->cfg1);
-	} while ((cfg1 & CFG1_WAIT) != CFG1_WAIT && delay < 100);
-
-	if (delay == 100) {
-		dev_warn(&adapter->pdev->dev,
-		    "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
-			cfg1);
-	}
-
-	/* Enable txmac */
-	ctl |= 0x09;	/* TX mac enable, FC disable */
-	writel(ctl, &adapter->regs->txmac.ctl);
-
-	/* Ready to start the RXDMA/TXDMA engine */
-	if (adapter->flags & fMP_ADAPTER_LOWER_POWER) {
-		et131x_rx_dma_enable(adapter);
-		et131x_tx_dma_enable(adapter);
-	}
-}
-
-void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
-{
-	struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
-	struct phy_device *phydev = adapter->phydev;
-	u32 sa_lo;
-	u32 sa_hi = 0;
-	u32 pf_ctrl = 0;
-
-	/* Disable the MAC while it is being configured (also disable WOL) */
-	writel(0x8, &rxmac->ctrl);
-
-	/* Initialize WOL to disabled. */
-	writel(0, &rxmac->crc0);
-	writel(0, &rxmac->crc12);
-	writel(0, &rxmac->crc34);
-
-	/* We need to set the WOL mask0 - mask4 next.  We initialize it to
-	 * its default Values of 0x00000000 because there are not WOL masks
-	 * as of this time.
-	 */
-	writel(0, &rxmac->mask0_word0);
-	writel(0, &rxmac->mask0_word1);
-	writel(0, &rxmac->mask0_word2);
-	writel(0, &rxmac->mask0_word3);
-
-	writel(0, &rxmac->mask1_word0);
-	writel(0, &rxmac->mask1_word1);
-	writel(0, &rxmac->mask1_word2);
-	writel(0, &rxmac->mask1_word3);
-
-	writel(0, &rxmac->mask2_word0);
-	writel(0, &rxmac->mask2_word1);
-	writel(0, &rxmac->mask2_word2);
-	writel(0, &rxmac->mask2_word3);
-
-	writel(0, &rxmac->mask3_word0);
-	writel(0, &rxmac->mask3_word1);
-	writel(0, &rxmac->mask3_word2);
-	writel(0, &rxmac->mask3_word3);
-
-	writel(0, &rxmac->mask4_word0);
-	writel(0, &rxmac->mask4_word1);
-	writel(0, &rxmac->mask4_word2);
-	writel(0, &rxmac->mask4_word3);
-
-	/* Lets setup the WOL Source Address */
-	sa_lo = (adapter->addr[2] << ET_WOL_LO_SA3_SHIFT) |
-		(adapter->addr[3] << ET_WOL_LO_SA4_SHIFT) |
-		(adapter->addr[4] << ET_WOL_LO_SA5_SHIFT) |
-		 adapter->addr[5];
-	writel(sa_lo, &rxmac->sa_lo);
-
-	sa_hi = (u32) (adapter->addr[0] << ET_WOL_HI_SA1_SHIFT) |
-		       adapter->addr[1];
-	writel(sa_hi, &rxmac->sa_hi);
-
-	/* Disable all Packet Filtering */
-	writel(0, &rxmac->pf_ctrl);
-
-	/* Let's initialize the Unicast Packet filtering address */
-	if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
-		et1310_setup_device_for_unicast(adapter);
-		pf_ctrl |= 4;	/* Unicast filter */
-	} else {
-		writel(0, &rxmac->uni_pf_addr1);
-		writel(0, &rxmac->uni_pf_addr2);
-		writel(0, &rxmac->uni_pf_addr3);
-	}
-
-	/* Let's initialize the Multicast hash */
-	if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
-		pf_ctrl |= 2;	/* Multicast filter */
-		et1310_setup_device_for_multicast(adapter);
-	}
-
-	/* Runt packet filtering.  Didn't work in version A silicon. */
-	pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16;
-	pf_ctrl |= 8;	/* Fragment filter */
-
-	if (adapter->registry_jumbo_packet > 8192)
-		/* In order to transmit jumbo packets greater than 8k, the
-		 * FIFO between RxMAC and RxDMA needs to be reduced in size
-		 * to (16k - Jumbo packet size).  In order to implement this,
-		 * we must use "cut through" mode in the RxMAC, which chops
-		 * packets down into segments which are (max_size * 16).  In
-		 * this case we selected 256 bytes, since this is the size of
-		 * the PCI-Express TLP's that the 1310 uses.
-		 *
-		 * seg_en on, fc_en off, size 0x10
-		 */
-		writel(0x41, &rxmac->mcif_ctrl_max_seg);
-	else
-		writel(0, &rxmac->mcif_ctrl_max_seg);
-
-	/* Initialize the MCIF water marks */
-	writel(0, &rxmac->mcif_water_mark);
-
-	/*  Initialize the MIF control */
-	writel(0, &rxmac->mif_ctrl);
-
-	/* Initialize the Space Available Register */
-	writel(0, &rxmac->space_avail);
-
-	/* Initialize the the mif_ctrl register
-	 * bit 3:  Receive code error. One or more nibbles were signaled as
-	 *	   errors  during the reception of the packet.  Clear this
-	 *	   bit in Gigabit, set it in 100Mbit.  This was derived
-	 *	   experimentally at UNH.
-	 * bit 4:  Receive CRC error. The packet's CRC did not match the
-	 *	   internally generated CRC.
-	 * bit 5:  Receive length check error. Indicates that frame length
-	 *	   field value in the packet does not match the actual data
-	 *	   byte length and is not a type field.
-	 * bit 16: Receive frame truncated.
-	 * bit 17: Drop packet enable
-	 */
-	if (phydev && phydev->speed == SPEED_100)
-		writel(0x30038, &rxmac->mif_ctrl);
-	else
-		writel(0x30030, &rxmac->mif_ctrl);
-
-	/* Finally we initialize RxMac to be enabled & WOL disabled.  Packet
-	 * filter is always enabled since it is where the runt packets are
-	 * supposed to be dropped.  For version A silicon, runt packet
-	 * dropping doesn't work, so it is disabled in the pf_ctrl register,
-	 * but we still leave the packet filter on.
-	 */
-	writel(pf_ctrl, &rxmac->pf_ctrl);
-	writel(0x9, &rxmac->ctrl);
-}
-
-void et1310_config_txmac_regs(struct et131x_adapter *adapter)
-{
-	struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
-
-	/* We need to update the Control Frame Parameters
-	 * cfpt - control frame pause timer set to 64 (0x40)
-	 * cfep - control frame extended pause timer set to 0x0
-	 */
-	if (adapter->flowcontrol == FLOW_NONE)
-		writel(0, &txmac->cf_param);
-	else
-		writel(0x40, &txmac->cf_param);
-}
-
-void et1310_config_macstat_regs(struct et131x_adapter *adapter)
-{
-	struct macstat_regs __iomem *macstat =
-		&adapter->regs->macstat;
-
-	/* Next we need to initialize all the macstat registers to zero on
-	 * the device.
-	 */
-	writel(0, &macstat->txrx_0_64_byte_frames);
-	writel(0, &macstat->txrx_65_127_byte_frames);
-	writel(0, &macstat->txrx_128_255_byte_frames);
-	writel(0, &macstat->txrx_256_511_byte_frames);
-	writel(0, &macstat->txrx_512_1023_byte_frames);
-	writel(0, &macstat->txrx_1024_1518_byte_frames);
-	writel(0, &macstat->txrx_1519_1522_gvln_frames);
-
-	writel(0, &macstat->rx_bytes);
-	writel(0, &macstat->rx_packets);
-	writel(0, &macstat->rx_fcs_errs);
-	writel(0, &macstat->rx_multicast_packets);
-	writel(0, &macstat->rx_broadcast_packets);
-	writel(0, &macstat->rx_control_frames);
-	writel(0, &macstat->rx_pause_frames);
-	writel(0, &macstat->rx_unknown_opcodes);
-	writel(0, &macstat->rx_align_errs);
-	writel(0, &macstat->rx_frame_len_errs);
-	writel(0, &macstat->rx_code_errs);
-	writel(0, &macstat->rx_carrier_sense_errs);
-	writel(0, &macstat->rx_undersize_packets);
-	writel(0, &macstat->rx_oversize_packets);
-	writel(0, &macstat->rx_fragment_packets);
-	writel(0, &macstat->rx_jabbers);
-	writel(0, &macstat->rx_drops);
-
-	writel(0, &macstat->tx_bytes);
-	writel(0, &macstat->tx_packets);
-	writel(0, &macstat->tx_multicast_packets);
-	writel(0, &macstat->tx_broadcast_packets);
-	writel(0, &macstat->tx_pause_frames);
-	writel(0, &macstat->tx_deferred);
-	writel(0, &macstat->tx_excessive_deferred);
-	writel(0, &macstat->tx_single_collisions);
-	writel(0, &macstat->tx_multiple_collisions);
-	writel(0, &macstat->tx_late_collisions);
-	writel(0, &macstat->tx_excessive_collisions);
-	writel(0, &macstat->tx_total_collisions);
-	writel(0, &macstat->tx_pause_honored_frames);
-	writel(0, &macstat->tx_drops);
-	writel(0, &macstat->tx_jabbers);
-	writel(0, &macstat->tx_fcs_errs);
-	writel(0, &macstat->tx_control_frames);
-	writel(0, &macstat->tx_oversize_frames);
-	writel(0, &macstat->tx_undersize_frames);
-	writel(0, &macstat->tx_fragments);
-	writel(0, &macstat->carry_reg1);
-	writel(0, &macstat->carry_reg2);
-
-	/* Unmask any counters that we want to track the overflow of.
-	 * Initially this will be all counters.  It may become clear later
-	 * that we do not need to track all counters.
-	 */
-	writel(0xFFFFBE32, &macstat->carry_reg1_mask);
-	writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
-}
-
-void et1310_config_flow_control(struct et131x_adapter *adapter)
-{
-	struct phy_device *phydev = adapter->phydev;
-
-	if (phydev->duplex == DUPLEX_HALF) {
-		adapter->flowcontrol = FLOW_NONE;
-	} else {
-		char remote_pause, remote_async_pause;
-
-		et1310_phy_access_mii_bit(adapter,
-				TRUEPHY_BIT_READ, 5, 10, &remote_pause);
-		et1310_phy_access_mii_bit(adapter,
-				TRUEPHY_BIT_READ, 5, 11,
-				&remote_async_pause);
-
-		if ((remote_pause == TRUEPHY_BIT_SET) &&
-		    (remote_async_pause == TRUEPHY_BIT_SET)) {
-			adapter->flowcontrol = adapter->wanted_flow;
-		} else if ((remote_pause == TRUEPHY_BIT_SET) &&
-			   (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
-			if (adapter->wanted_flow == FLOW_BOTH)
-				adapter->flowcontrol = FLOW_BOTH;
-			else
-				adapter->flowcontrol = FLOW_NONE;
-		} else if ((remote_pause == TRUEPHY_BIT_CLEAR) &&
-			   (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
-			adapter->flowcontrol = FLOW_NONE;
-		} else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
-			       remote_async_pause == TRUEPHY_SET_BIT) */
-			if (adapter->wanted_flow == FLOW_BOTH)
-				adapter->flowcontrol = FLOW_RXONLY;
-			else
-				adapter->flowcontrol = FLOW_NONE;
-		}
-	}
-}
-
-/**
- * et1310_update_macstat_host_counters - Update the local copy of the statistics
- * @adapter: pointer to the adapter structure
- */
-void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
-{
-	struct ce_stats *stats = &adapter->stats;
-	struct macstat_regs __iomem *macstat =
-		&adapter->regs->macstat;
-
-	stats->tx_collisions	       += readl(&macstat->tx_total_collisions);
-	stats->tx_first_collisions     += readl(&macstat->tx_single_collisions);
-	stats->tx_deferred	       += readl(&macstat->tx_deferred);
-	stats->tx_excessive_collisions +=
-				readl(&macstat->tx_multiple_collisions);
-	stats->tx_late_collisions      += readl(&macstat->tx_late_collisions);
-	stats->tx_underflows	       += readl(&macstat->tx_undersize_frames);
-	stats->tx_max_pkt_errs	       += readl(&macstat->tx_oversize_frames);
-
-	stats->rx_align_errs        += readl(&macstat->rx_align_errs);
-	stats->rx_crc_errs          += readl(&macstat->rx_code_errs);
-	stats->rcvd_pkts_dropped    += readl(&macstat->rx_drops);
-	stats->rx_overflows         += readl(&macstat->rx_oversize_packets);
-	stats->rx_code_violations   += readl(&macstat->rx_fcs_errs);
-	st