diff options
| author | Senthil Balasubramanian <senthilkumar@atheros.com> | 2011-04-22 11:32:09 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-04-25 14:50:17 -0400 |
| commit | d1c038d620c45fbbc65bcadf813a86bca686dd31 (patch) | |
| tree | 7041ac78c80e58f43fb507c209608d8a3bab7756 /drivers | |
| parent | 353e5019e048562dc8f434c6237d41ef5e758922 (diff) | |
ath9k_hw: Fix incorrect baseband PLL phase shift for AR9485
we should program the AR9485 baseband PLL phase shift to 6 and
a redundant setting overwrites the correct value. Remove the
incorrect and unwnated register setting.
Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 577ca59b02bf..6166ba0bca54 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c @@ -686,7 +686,6 @@ unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) } EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); -#define DPLL3_PHASE_SHIFT_VAL 0x1 static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan) { @@ -723,9 +722,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_BB_DPLL2_PLL_PWD, 0x0); udelay(1000); - - REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, - AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL); } else if (AR_SREV_9340(ah)) { u32 regval, pll2_divint, pll2_divfrac, refdiv; |