diff options
author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-11-21 10:43:16 +0100 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-12-04 10:29:41 +0100 |
commit | b9c0ba6614bc19844c2ab345c10e8116c78de772 (patch) | |
tree | bf8f395a238f03f5b2df18f586a5373d390b14c5 /drivers | |
parent | f845b01d478a4d139fe3493f1e6ec8d9110ce56c (diff) |
clk: renesas: r8a7795: Add CPEX clock
Implement support for the CPEX clock on R-Car H3. This clock can be
selected as a clock source for CMT1 (Compare Match Timer Type 1).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 119c02440726..86842c9fd314 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -104,6 +104,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1), DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), |