staging: silicom: remove driver

The driver hasn't been cleaned up and it doesn't look like anyone is
working on it anymore (including the original author). So remove it.
If someone wants to work on cleaning the driver up and moving it out of
staging, this commit can be reverted.

In addition, since this removes the CONFIG_NET_VENDOR_SILICOM config
symbol, remove the symbol from all defconfig files that reference it.

Signed-off-by: Kristina Martšenko <kristina.martsenko@gmail.com>
Cc: Daniel Cotey <puff65537@bansheeslibrary.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

17 files changed, 0 insertions, 10573 deletions

diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index b08394cd9604..90624df0db6f 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -96,8 +96,6 @@ source "drivers/staging/gdm72xx/Kconfig"
 
 source "drivers/staging/gdm724x/Kconfig"
 
-source "drivers/staging/silicom/Kconfig"
-
 source "drivers/staging/imx-drm/Kconfig"
 
 source "drivers/staging/fwserial/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 962330817fa4..27f44cdde516 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -41,7 +41,6 @@ obj-$(CONFIG_STAGING_BOARD)	+= board/
 obj-$(CONFIG_USB_WPAN_HCD)	+= ozwpan/
 obj-$(CONFIG_WIMAX_GDM72XX)	+= gdm72xx/
 obj-$(CONFIG_LTE_GDM724X)	+= gdm724x/
-obj-$(CONFIG_NET_VENDOR_SILICOM)	+= silicom/
 obj-$(CONFIG_DRM_IMX)		+= imx-drm/
 obj-$(CONFIG_FIREWIRE_SERIAL)	+= fwserial/
 obj-$(CONFIG_GOLDFISH)		+= goldfish/
diff --git a/drivers/staging/silicom/Kconfig b/drivers/staging/silicom/Kconfig
deleted file mode 100644
index 6651bd819bc8..000000000000
--- a/drivers/staging/silicom/Kconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# Silicom device configuration
-#
-
-config NET_VENDOR_SILICOM
-	bool "Silicom devices"
-	default y
-	depends on PCI && NETDEVICES
-	---help---
-	  If you have a network card (Ethernet) belonging to this class,
-	  say Y.
-
-	  Note that the answer to this question does not directly affect
-	  the kernel: saying N will just case the configurator to skip all
-	  the questions regarding Silicom chipsets. If you say Y, you will be asked
-	  for your specific chipset/driver in the following questions.
-
-if NET_VENDOR_SILICOM
-
-config SBYPASS
-	tristate "Silicom BypassCTL library support"
-	depends on PCI
-	depends on m
-	---help---
-	  If you have a network (Ethernet) controller of this type, say Y
-
-	  To compile this driver as a module, choose M here. The module
-	  will be called bypass.
-
-config BPCTL
-	tristate "Silicom BypassCTL net support"
-	depends on PCI
-	depends on m
-	select SBYPASS
-	select MII
-	---help---
-	  If you have a network (Ethernet) controller of this type, say Y
-	  or M and read the Ethernet-HOWTO, available from
-	  <http://www.tldp.org/docs.html#howto>.
-
-	  To compile this driver as a module, choose M here. The module
-	  will be called bpctl_mod.
-
-
-endif # NET_VENDOR_SILICOM
diff --git a/drivers/staging/silicom/Makefile b/drivers/staging/silicom/Makefile
deleted file mode 100644
index ca8359481c48..000000000000
--- a/drivers/staging/silicom/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for the Bypass network device drivers.
-#
-
-obj-$(CONFIG_BPCTL) += bpctl_mod.o
-obj-$(CONFIG_SBYPASS) += bypasslib/
diff --git a/drivers/staging/silicom/README b/drivers/staging/silicom/README
deleted file mode 100644
index ae970b37fdc6..000000000000
--- a/drivers/staging/silicom/README
+++ /dev/null
@@ -1,14 +0,0 @@
-
-Theory of Operation:
-
-The Silicom Bypass Network Interface Cards (NICs) are network cards with paired ports (2 or 4). 
-The pairs either act as a "wire" allowing the network packets to pass or insert the device in 
-between the two ports.  When paired with the on-board hardware watchdog or other failsafe, 
-they provide high availability for the network in the face of software outages or maintenance.
-
-The software requirements are for a kernel level driver that interfaces with the bypass and watchdog,
-as well as for control software. User control can be either the provided standalone executable 
-(/bin/bpctl) or the API exposed by the Silicom library.
-
-
-
diff --git a/drivers/staging/silicom/TODO b/drivers/staging/silicom/TODO
deleted file mode 100644
index 09d07b0ea9c0..000000000000
--- a/drivers/staging/silicom/TODO
+++ /dev/null
@@ -1,8 +0,0 @@
-TODO:
-	- checkpatch.pl cleanups
-	- locking audit
-	- single module with all functionality
-	- userland 
-	- fix monolithic build.
-
-
diff --git a/drivers/staging/silicom/bits.h b/drivers/staging/silicom/bits.h
deleted file mode 100644
index 8c411d0d4ecd..000000000000
--- a/drivers/staging/silicom/bits.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/******************************************************************************/
-/*                                                                            */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2004 Broadcom  */
-/* Corporation.                                                               */
-/* All rights reserved.                                                       */
-/*                                                                            */
-/* This program is free software; you can redistribute it and/or modify       */
-/* it under the terms of the GNU General Public License as published by       */
-/* the Free Software Foundation, located in the file LICENSE.                 */
-/*                                                                            */
-/* History:                                                                   */
-/*    02/25/00 Hav Khauv        Initial version.                              */
-/******************************************************************************/
-
-#ifndef BITS_H
-#define BITS_H
-
-/******************************************************************************/
-/* Bit Mask definitions */
-/******************************************************************************/
-
-#define BIT_NONE            0x00
-#define BIT_0               0x01
-#define BIT_1               0x02
-#define BIT_2               0x04
-#define BIT_3               0x08
-#define BIT_4               0x10
-#define BIT_5               0x20
-#define BIT_6               0x40
-#define BIT_7               0x80
-#define BIT_8               0x0100
-#define BIT_9               0x0200
-#define BIT_10              0x0400
-#define BIT_11              0x0800
-#define BIT_12              0x1000
-#define BIT_13              0x2000
-#define BIT_14              0x4000
-#define BIT_15              0x8000
-#define BIT_16              0x010000
-#define BIT_17              0x020000
-#define BIT_18              0x040000
-#define BIT_19              0x080000
-#define BIT_20              0x100000
-#define BIT_21              0x200000
-#define BIT_22              0x400000
-#define BIT_23              0x800000
-#define BIT_24              0x01000000
-#define BIT_25              0x02000000
-#define BIT_26              0x04000000
-#define BIT_27              0x08000000
-#define BIT_28              0x10000000
-#define BIT_29              0x20000000
-#define BIT_30              0x40000000
-#define BIT_31              0x80000000
-
-#endif				/* BITS_H */
diff --git a/drivers/staging/silicom/bp_ioctl.h b/drivers/staging/silicom/bp_ioctl.h
deleted file mode 100644
index 57de34a69e8e..000000000000
--- a/drivers/staging/silicom/bp_ioctl.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/******************************************************************************/
-/*                                                                            */
-/* Silicom Bypass Control Utility, Copyright (c) 2005-2007 Silicom            */
-/* All rights reserved.                                                       */
-/*                                                                            */
-/* This program is free software; you can redistribute it and/or modify       */
-/* it under the terms of the GNU General Public License as published by       */
-/* the Free Software Foundation, located in the file LICENSE.                 */
-/*                                                                            */
-/*                                                                            */
-/******************************************************************************/
-
-#ifndef BP_IOCTL_H
-#define BP_IOCTL_H
-
-#define BP_CAP                   0x01	/* BIT_0 */
-#define BP_STATUS_CAP            0x02
-#define BP_STATUS_CHANGE_CAP     0x04
-#define SW_CTL_CAP               0x08
-#define BP_DIS_CAP               0x10
-#define BP_DIS_STATUS_CAP        0x20
-#define STD_NIC_CAP              0x40
-#define BP_PWOFF_ON_CAP          0x80
-#define BP_PWOFF_OFF_CAP         0x0100
-#define BP_PWOFF_CTL_CAP         0x0200
-#define BP_PWUP_ON_CAP           0x0400
-#define BP_PWUP_OFF_CAP          0x0800
-#define BP_PWUP_CTL_CAP          0x1000
-#define WD_CTL_CAP               0x2000
-#define WD_STATUS_CAP            0x4000
-#define WD_TIMEOUT_CAP           0x8000
-#define TX_CTL_CAP               0x10000
-#define TX_STATUS_CAP            0x20000
-#define TAP_CAP                  0x40000
-#define TAP_STATUS_CAP           0x80000
-#define TAP_STATUS_CHANGE_CAP    0x100000
-#define TAP_DIS_CAP              0x200000
-#define TAP_DIS_STATUS_CAP       0x400000
-#define TAP_PWUP_ON_CAP          0x800000
-#define TAP_PWUP_OFF_CAP         0x1000000
-#define TAP_PWUP_CTL_CAP         0x2000000
-#define NIC_CAP_NEG              0x4000000
-#define TPL_CAP                  0x8000000
-#define DISC_CAP                 0x10000000
-#define DISC_DIS_CAP             0x20000000
-#define DISC_PWUP_CTL_CAP        0x40000000
-
-#define TPL2_CAP_EX              0x01
-#define DISC_PORT_CAP_EX         0x02
-
-#define WD_MIN_TIME_MASK(val)      (val & 0xf)
-#define WD_STEP_COUNT_MASK(val)    ((val & 0xf) << 5)
-#define WDT_STEP_TIME              0x10	/* BIT_4 */
-
-#define WD_MIN_TIME_GET(desc)   (desc & 0xf)
-#define WD_STEP_COUNT_GET(desc) ((desc>>5) & 0xf)
-
-typedef enum {
-	IF_SCAN,
-	GET_DEV_NUM,
-	IS_BYPASS,
-	GET_BYPASS_SLAVE,
-	GET_BYPASS_CAPS,
-	GET_WD_SET_CAPS,
-	SET_BYPASS,
-	GET_BYPASS,
-	GET_BYPASS_CHANGE,
-	SET_BYPASS_WD,
-	GET_BYPASS_WD,
-	GET_WD_EXPIRE_TIME,
-	RESET_BYPASS_WD_TIMER,
-	SET_DIS_BYPASS,
-	GET_DIS_BYPASS,
-	SET_BYPASS_PWOFF,
-	GET_BYPASS_PWOFF,
-	SET_BYPASS_PWUP,
-	GET_BYPASS_PWUP,
-	SET_STD_NIC,
-	GET_STD_NIC,
-	SET_TX,
-	GET_TX,
-	SET_TAP,
-	GET_TAP,
-	GET_TAP_CHANGE,
-	SET_DIS_TAP,
-	GET_DIS_TAP,
-	SET_TAP_PWUP,
-	GET_TAP_PWUP,
-	SET_WD_EXP_MODE,
-	GET_WD_EXP_MODE,
-	SET_WD_AUTORESET,
-	GET_WD_AUTORESET,
-	SET_TPL,
-	GET_TPL,
-	SET_DISC,
-	GET_DISC,
-	GET_DISC_CHANGE,
-	SET_DIS_DISC,
-	GET_DIS_DISC,
-	SET_DISC_PWUP,
-	GET_DISC_PWUP,
-	GET_BYPASS_INFO = 100,
-	GET_BP_WAIT_AT_PWUP,
-	SET_BP_WAIT_AT_PWUP,
-	GET_BP_HW_RESET,
-	SET_BP_HW_RESET,
-	SET_DISC_PORT,
-	GET_DISC_PORT,
-	SET_DISC_PORT_PWUP,
-	GET_DISC_PORT_PWUP,
-	SET_BP_FORCE_LINK,
-	GET_BP_FORCE_LINK,
-#ifdef BP_SELF_TEST
-	SET_BP_SELF_TEST = 200,
-	GET_BP_SELF_TEST,
-#endif
-
-} CMND_TYPE_SD;
-
-/*
-* The major device number. We can't rely on dynamic
-* registration any more, because ioctls need to know
-* it.
-*/
-
-#define MAGIC_NUM 'J'
-
-/* for passing single values */
-struct bpctl_cmd {
-	int status;
-	int data[8];
-	int in_param[8];
-	int out_param[8];
-};
-
-#define IOCTL_TX_MSG(cmd) _IOWR(MAGIC_NUM, cmd, struct bpctl_cmd)
-
-#define DEVICE_NAME "bpctl"
-
-#endif
diff --git a/drivers/staging/silicom/bp_mod.h b/drivers/staging/silicom/bp_mod.h
deleted file mode 100644
index 82b4963e97b6..000000000000
--- a/drivers/staging/silicom/bp_mod.h
+++ /dev/null
@@ -1,711 +0,0 @@
-/******************************************************************************/
-/*                                                                            */
-/* Bypass Control utility, Copyright (c) 2005 Silicom                         */
-/*                                                                            */
-/* This program is free software; you can redistribute it and/or modify       */
-/* it under the terms of the GNU General Public License as published by       */
-/* the Free Software Foundation, located in the file LICENSE.                 */
-/*                                                                            */
-/*                                                                            */
-/* bp_mod.h                                                                   */
-/*                                                                            */
-/******************************************************************************/
-
-#ifndef BP_MOD_H
-#define BP_MOD_H
-#include "bits.h"
-
-#define usec_delay(x) udelay(x)
-#ifndef msec_delay_bp
-#define msec_delay_bp(x)			\
-do {						\
-	int  i;					\
-	if (1) {				\
-		for (i = 0; i < 1000; i++) {	\
-			udelay(x);		\
-		}				\
-	} else {				\
-		msleep(x);			\
-	}					\
-} while (0)
-
-#endif
-
-#include <linux/param.h>
-
-#ifndef jiffies_to_msecs
-#define jiffies_to_msecs(x) _kc_jiffies_to_msecs(x)
-static inline unsigned int jiffies_to_msecs(const unsigned long j)
-{
-#if HZ <= 1000 && !(1000 % HZ)
-	return (1000 / HZ) * j;
-#elif HZ > 1000 && !(HZ % 1000)
-	return (j + (HZ / 1000) - 1) / (HZ / 1000);
-#else
-	return (j * 1000) / HZ;
-#endif
-}
-#endif
-
-#define SILICOM_VID              0x1374
-#define SILICOM_SVID             0x1374
-
-#define SILICOM_PXG2BPFI_SSID    0x0026
-#define SILICOM_PXG2BPFILX_SSID  0x0027
-#define SILICOM_PXGBPI_SSID      0x0028
-#define SILICOM_PXGBPIG_SSID     0x0029
-#define SILICOM_PXG2TBFI_SSID    0x002a
-#define SILICOM_PXG4BPI_SSID     0x002c
-#define SILICOM_PXG4BPFI_SSID    0x002d
-#define SILICOM_PXG4BPFILX_SSID  0x002e
-#define SILICOM_PXG2BPFIL_SSID   0x002F
-#define SILICOM_PXG2BPFILLX_SSID 0x0030
-#define SILICOM_PEG4BPI_SSID     0x0031
-#define SILICOM_PEG2BPI_SSID     0x0037
-#define SILICOM_PEG4BPIN_SSID    0x0038
-#define SILICOM_PEG2BPFI_SSID    0x0039
-#define SILICOM_PEG2BPFILX_SSID  0x003A
-#define SILICOM_PMCXG2BPFI_SSID  0x003B
-#define NOKIA_PMCXG2BPFIN_SSID   0x0510
-#define NOKIA_PMCXG2BPIN_SSID    0x0513
-#define NOKIA_PMCXG4BPIN_SSID    0x0514
-#define NOKIA_PMCXG2BPFIN_SVID   0x13B8
-#define NOKIA_PMCXG2BPIN2_SSID    0x0515
-#define NOKIA_PMCXG4BPIN2_SSID    0x0516
-#define SILICOM_PMCX2BPI_SSID       0x041
-#define SILICOM_PMCX4BPI_SSID       0x042
-#define SILICOM_PXG2BISC1_SSID   0x003d
-#define SILICOM_PEG2TBFI_SSID    0x003E
-#define SILICOM_PXG2TBI_SSID     0x003f
-#define SILICOM_PXG4BPFID_SSID   0x0043
-#define SILICOM_PEG4BPFI_SSID    0x0040
-#define SILICOM_PEG4BPIPT_SSID   0x0044
-#define SILICOM_PXG6BPI_SSID     0x0045
-#define SILICOM_PEG4BPIL_SSID    0x0046
-#define SILICOM_PEG2BPI5_SSID    0x0052
-#define SILICOM_PEG6BPI_SSID    0x0053
-#define SILICOM_PEG4BPFI5_SSID   0x0050
-#define SILICOM_PEG4BPFI5LX_SSID   0x0051
-#define SILICOM_PEG2BISC6_SSID 0x54
-
-#define SILICOM_PEG6BPIFC_SSID 0x55
-
-#define SILICOM_PEG2BPFI5_SSID   0x0056
-#define SILICOM_PEG2BPFI5LX_SSID   0x0057
-
-#define SILICOM_PXEG4BPFI_SSID    0x0058
-
-#define SILICOM_PEG2BPFID_SSID   0x0047
-#define SILICOM_PEG2BPFIDLX_SSID  0x004C
-#define SILICOM_MEG2BPFILN_SSID  0x0048
-#define SILICOM_MEG2BPFINX_SSID  0x0049
-#define SILICOM_PEG4BPFILX_SSID  0x004A
-#define SILICOM_MHIO8AD_SSID    0x004F
-
-#define SILICOM_MEG2BPFILXLN_SSID 0x004b
-#define SILICOM_PEG2BPIX1_SSID    0x004d
-#define SILICOM_MEG2BPFILXNX_SSID 0x004e
-
-#define SILICOM_PE10G2BPISR_SSID  0x0102
-#define SILICOM_PE10G2BPILR_SSID  0x0103
-#define SILICOM_PE10G2BPICX4_SSID  0x0101
-
-#define SILICOM_XE10G2BPILR_SSID 0x0163
-#define SILICOM_XE10G2BPISR_SSID 0x0162
-#define SILICOM_XE10G2BPICX4_SSID 0x0161
-#define SILICOM_XE10G2BPIT_SSID   0x0160
-
-#define SILICOM_PE10GDBISR_SSID   0x0181
-#define SILICOM_PE10GDBILR_SSID   0x0182
-
-#define SILICOM_PE210G2DBi9SR_SSID	    0x0188
-#define SILICOM_PE210G2DBi9SRRB_SSID	0x0188
-#define SILICOM_PE210G2DBi9LR_SSID	    0x0189
-#define SILICOM_PE210G2DBi9LRRB_SSID	0x0189
-#define SILICOM_PE310G4DBi940SR_SSID	0x018C
-
-#define SILICOM_PE310G4BPi9T_SSID       0x130
-#define SILICOM_PE310G4BPi9SR_SSID        0x132
-#define SILICOM_PE310G4BPi9LR_SSID        0x133
-
-#define NOKIA_XE10G2BPIXR_SVID   0x13B8
-#define NOKIA_XE10G2BPIXR_SSID   0x051C
-
-#define INTEL_PEG4BPII_PID   0x10A0
-#define INTEL_PEG4BPFII_PID   0x10A1
-#define INTEL_PEG4BPII_SSID   0x11A0
-#define INTEL_PEG4BPFII_SSID   0x11A1
-
-#define INTEL_PEG4BPIIO_SSID   0x10A0
-#define INTEL_PEG4BPIIO_PID   0x105e
-
-#define BROADCOM_VID         0x14e4
-#define BROADCOM_PE10G2_PID  0x164e
-
-#define SILICOM_PE10G2BPTCX4_SSID 0x0141
-#define SILICOM_PE10G2BPTSR_SSID  0x0142
-#define SILICOM_PE10G2BPTLR_SSID  0x0143
-#define SILICOM_PE10G2BPTT_SSID   0x0140
-
-#define SILICOM_PEG4BPI6_SSID     0x0320
-#define SILICOM_PEG4BPFI6_SSID    0x0321
-#define SILICOM_PEG4BPFI6LX_SSID    0x0322
-#define SILICOM_PEG4BPFI6ZX_SSID    0x0323
-
-#define SILICOM_PEG2BPI6_SSID    0x0300
-#define SILICOM_PEG2BPFI6_SSID    0x0301
-#define SILICOM_PEG2BPFI6LX_SSID    0x0302
-#define SILICOM_PEG2BPFI6ZX_SSID    0x0303
-#define SILICOM_PEG2BPFI6FLXM_SSID  0x0304
-
-#define SILICOM_PEG2DBI6_SSID    0x0308
-#define SILICOM_PEG2DBFI6_SSID    0x0309
-#define SILICOM_PEG2DBFI6LX_SSID    0x030A
-#define SILICOM_PEG2DBFI6ZX_SSID    0x030B
-
-#define SILICOM_MEG2BPI6_SSID     0x0310
-#define SILICOM_XEG2BPI6_SSID    0x0318
-#define SILICOM_PEG4BPI6FC_SSID     0x0328
-#define SILICOM_PEG4BPFI6FC_SSID    0x0329
-#define SILICOM_PEG4BPFI6FCLX_SSID    0x032A
-#define SILICOM_PEG4BPFI6FCZX_SSID    0x032B
-
-#define SILICOM_PEG6BPI6_SSID     0x0340
-
-#define SILICOM_PEG2BPI6SC6_SSID     0x0360
-
-#define SILICOM_MEG2BPI6_SSID     0x0310
-#define SILICOM_XEG2BPI6_SSID     0x0318
-#define SILICOM_MEG4BPI6_SSID     0x0330
-
-#define SILICOM_PE2G4BPi80L_SSID    0x0380
-
-#define SILICOM_M6E2G8BPi80A_SSID    0x0474
-
-#define SILICOM_PE2G4BPi35_SSID    0x03d8
-
-#define SILICOM_PE2G4BPFi80_SSID    0x0381
-#define SILICOM_PE2G4BPFi80LX_SSID    0x0382
-#define SILICOM_PE2G4BPFi80ZX_SSID    0x0383
-
-#define SILICOM_PE2G4BPi80_SSID    0x0388
-
-#define SILICOM_PE2G2BPi80_SSID    0x0390
-#define SILICOM_PE2G2BPFi80_SSID    0x0391
-#define SILICOM_PE2G2BPFi80LX_SSID    0x0392
-#define SILICOM_PE2G2BPFi80ZX_SSID    0x0393
-
-#define SILICOM_PE2G4BPi35L_SSID    0x03D0
-#define SILICOM_PE2G4BPFi35_SSID    0x03D1
-#define SILICOM_PE2G4BPFi35LX_SSID    0x03D2
-#define SILICOM_PE2G4BPFi35ZX_SSID    0x03D3
-
-#define SILICOM_PE2G2BPi35_SSID    0x03c0
-#define SILICOM_PAC1200BPi35_SSID    0x03cc
-#define SILICOM_PE2G2BPFi35_SSID    0x03C1
-#define SILICOM_PE2G2BPFi35LX_SSID    0x03C2
-#define SILICOM_PE2G2BPFi35ZX_SSID    0x03C3
-
-#define SILICOM_PE2G6BPi35_SSID    0x03E0
-#define SILICOM_PE2G6BPi35CX_SSID  0x0AA0
-
-#define INTEL_PE210G2SPI9_SSID     0x00C
-
-#define SILICOM_M1EG2BPI6_SSID     0x400
-
-#define SILICOM_M1EG2BPFI6_SSID     0x0401
-#define SILICOM_M1EG2BPFI6LX_SSID     0x0402
-#define SILICOM_M1EG2BPFI6ZX_SSID     0x0403
-
-#define SILICOM_M1EG4BPI6_SSID     0x0420
-
-#define SILICOM_M1EG4BPFI6_SSID       0x0421
-#define SILICOM_M1EG4BPFI6LX_SSID     0x0422
-#define SILICOM_M1EG4BPFI6ZX_SSID     0x0423
-
-#define SILICOM_M1EG6BPI6_SSID     0x0440
-
-#define SILICOM_M1E2G4BPi80_SSID     0x0460
-#define SILICOM_M1E2G4BPFi80_SSID       0x0461
-#define SILICOM_M1E2G4BPFi80LX_SSID     0x0462
-#define SILICOM_M1E2G4BPFi80ZX_SSID     0x0463
-
-#define SILICOM_M6E2G8BPi80_SSID        0x0470
-#define SILICOM_PE210G2BPi40_SSID       0x01a0
-
-#define PEG540_IF_SERIES(pid) \
-	((pid == SILICOM_PE210G2BPi40_SSID))
-
-#define OLD_IF_SERIES(pid)\
-	((pid == SILICOM_PXG2BPFI_SSID) || \
-	 (pid == SILICOM_PXG2BPFILX_SSID))
-
-#define P2BPFI_IF_SERIES(pid) \
-	((pid == SILICOM_PXG2BPFI_SSID) || \
-	 (pid == SILICOM_PXG2BPFILX_SSID) || \
-	 (pid == SILICOM_PEG2BPFI_SSID) || \
-	 (pid == SILICOM_PEG2BPFID_SSID) || \
-	 (pid == SILICOM_PEG2BPFIDLX_SSID) || \
-	 (pid == SILICOM_MEG2BPFILN_SSID) || \
-	 (pid == SILICOM_MEG2BPFINX_SSID) || \
-	 (pid == SILICOM_PEG4BPFILX_SSID) || \
-	 (pid == SILICOM_PEG4BPFI_SSID) || \
-	 (pid == SILICOM_PXEG4BPFI_SSID) || \
-	 (pid == SILICOM_PXG4BPFID_SSID) || \
-	 (pid == SILICOM_PEG2TBFI_SSID) || \
-	 (pid == SILICOM_PE10G2BPISR_SSID) || \
-	 (pid == SILICOM_PE10G2BPILR_SSID) || \
-	 (pid == SILICOM_PEG2BPFILX_SSID) || \
-	 (pid == SILICOM_PMCXG2BPFI_SSID) || \
-	 (pid == SILICOM_MHIO8AD_SSID) || \
-	 (pid == SILICOM_PEG4BPFI5LX_SSID) || \
-	 (pid == SILICOM_PEG4BPFI5_SSID) || \
-	 (pid == SILICOM_PEG4BPFI6FC_SSID) || \
-	 (pid == SILICOM_PEG4BPFI6FCLX_SSID) || \
-	 (pid == SILICOM_PEG4BPFI6FCZX_SSID) || \
-	 (pid == NOKIA_PMCXG2BPFIN_SSID) || \
-	 (pid == SILICOM_MEG2BPFILXLN_SSID) || \
-	 (pid == SILICOM_MEG2BPFILXNX_SSID) || \
-	 (pid == SILICOM_XE10G2BPIT_SSID) || \
-	 (pid == SILICOM_XE10G2BPICX4_SSID) || \
-	 (pid == SILICOM_XE10G2BPISR_SSID) || \
-	 (pid == NOKIA_XE10G2BPIXR_SSID) || \
-	 (pid == SILICOM_PE10GDBISR_SSID) || \
-	 (pid == SILICOM_PE10GDBILR_SSID) || \
-	 (pid == SILICOM_XE10G2BPILR_SSID))
-
-#define INTEL_IF_SERIES(pid) \
-	((pid == INTEL_PEG4BPII_SSID) || \
-	 (pid == INTEL_PEG4BPIIO_SSID) || \
-	 (pid == INTEL_PEG4BPFII_SSID))
-
-#define NOKIA_SERIES(pid) \
-	((pid == NOKIA_PMCXG2BPIN_SSID) || \
-	 (pid == NOKIA_PMCXG4BPIN_SSID) || \
-	 (pid == SILICOM_PMCX4BPI_SSID) || \
-	 (pid == NOKIA_PMCXG2BPFIN_SSID) || \
-	 (pid == SILICOM_PMCXG2BPFI_SSID) || \
-	 (pid == NOKIA_PMCXG2BPIN2_SSID) || \
-	 (pid == NOKIA_PMCXG4BPIN2_SSID) || \
-	 (pid == SILICOM_PMCX2BPI_SSID))
-
-#define DISCF_IF_SERIES(pid) \
-	(pid == SILICOM_PEG2TBFI_SSID)
-
-#define PEGF_IF_SERIES(pid) \
-	((pid == SILICOM_PEG2BPFI_SSID) || \
-	 (pid == SILICOM_PEG2BPFID_SSID) || \
-	 (pid == SILICOM_PEG2BPFIDLX_SSID) || \
-	 (pid == SILICOM_PEG2BPFILX_SSID) || \
-	 (pid == SILICOM_PEG4BPFI_SSID) || \
-	 (pid == SILICOM_PXEG4BPFI_SSID) || \
-	 (pid == SILICOM_MEG2BPFILN_SSID) || \
-	 (pid == SILICOM_MEG2BPFINX_SSID) || \
-	 (pid == SILICOM_PEG4BPFILX_SSID) || \
-	 (pid == SILICOM_PEG2TBFI_SSID) || \
-	 (pid == SILICOM_MEG2BPFILXLN_SSID) || \
-	 (pid == SILICOM_MEG2BPFILXNX_SSID))
-
-#define TPL_IF_SERIES(pid) \
-	((pid == SILICOM_PXG2BPFIL_SSID) || \
-	 (pid == SILICOM_PXG2BPFILLX_SSID) || \
-	 (pid == SILICOM_PXG2TBFI_SSID) || \
-	 (pid == SILICOM_PXG4BPFID_SSID) || \
-	 (pid == SILICOM_PXG4BPFI_SSID))
-
-#define BP10G_IF_SERIES(pid) \
-	((pid == SILICOM_PE10G2BPISR_SSID) || \
-	 (pid == SILICOM_PE10G2BPICX4_SSID) || \
-	 (pid == SILICOM_PE10G2BPILR_SSID) || \
-	 (pid == SILICOM_XE10G2BPIT_SSID) || \
-	 (pid == SILICOM_XE10G2BPICX4_SSID) || \
-	 (pid == SILICOM_XE10G2BPISR_SSID) || \
-	 (pid == NOKIA_XE10G2BPIXR_SSID) || \
-	 (pid == SILICOM_PE10GDBISR_SSID) || \
-	 (pid == SILICOM_PE10GDBILR_SSID) || \
-	 (pid == SILICOM_XE10G2BPILR_SSID))
-
-#define BP10GB_IF_SERIES(pid) \
-	((pid == SILICOM_PE10G2BPTCX4_SSID) || \
-	 (pid == SILICOM_PE10G2BPTSR_SSID) || \
-	 (pid == SILICOM_PE10G2BPTLR_SSID) || \
-	 (pid == SILICOM_PE10G2BPTT_SSID))
-
-#define BP10G_CX4_SERIES(pid) \
-	(pid == SILICOM_PE10G2BPICX4_SSID)
-
-#define BP10GB_CX4_SERIES(pid) \
-	(pid == SILICOM_PE10G2BPTCX4_SSID)
-
-#define SILICOM_M2EG2BPFI6_SSID       0x0501
-#define SILICOM_M2EG2BPFI6LX_SSID     0x0502
-#define SILICOM_M2EG2BPFI6ZX_SSID     0x0503
-#define SILICOM_M2EG4BPI6_SSID        0x0520
-
-#define SILICOM_M2EG4BPFI6_SSID       0x0521
-#define SILICOM_M2EG4BPFI6LX_SSID     0x0522
-#define SILICOM_M2EG4BPFI6ZX_SSID     0x0523
-
-#define SILICOM_M2EG6BPI6_SSID     0x0540
-
-#define SILICOM_M1E10G2BPI9CX4_SSID  0x481
-#define SILICOM_M1E10G2BPI9SR_SSID   0x482
-#define SILICOM_M1E10G2BPI9LR_SSID   0x483
-#define SILICOM_M1E10G2BPI9T_SSID    0x480
-
-#define SILICOM_M2E10G2BPI9CX4_SSID  0x581
-#define SILICOM_M2E10G2BPI9SR_SSID   0x582
-#define SILICOM_M2E10G2BPI9LR_SSID   0x583
-#define SILICOM_M2E10G2BPI9T_SSID    0x580
-
-#define SILICOM_PE210G2BPI9CX4_SSID  0x121
-#define SILICOM_PE210G2BPI9SR_SSID   0x122
-#define SILICOM_PE210G2BPI9LR_SSID   0x123
-#define SILICOM_PE210G2BPI9T_SSID    0x120
-
-#define DBI_IF_SERIES(pid) \
-	((pid == SILICOM_PE10GDBISR_SSID) || \
-	 (pid == SILICOM_PE10GDBILR_SSID) || \
-	 (pid == SILICOM_XE10G2BPILR_SSID) || \
-	 (pid == SILICOM_PE210G2DBi9LR_SSID))
-
-#define PEGF5_IF_SERIES(pid) \
-	((pid == SILICOM_PEG2BPFI5_SSID) || \
-	 (pid == SILICOM_PEG2BPFI5LX_SSID) || \
-	 (pid == SILICOM_PEG4BPFI6_SSID) || \
-	 (pid == SILICOM_PEG4BPFI6LX_SSID) || \
-	 (pid == SILICOM_PEG4BPFI6ZX_SSID) || \
-	 (pid == SILICOM_PEG2BPFI6_SSID) || \
-	 (pid == SILICOM_PEG2BPFI6LX_SSID) || \
-	 (pid == SILICOM_PEG2BPFI6ZX_SSID) || \
-	 (pid == SILICOM_PEG2BPFI6FLXM_SSID) || \
-	 (pid == SILICOM_PEG2DBFI6_SSID) || \
-	 (pid == SILICOM_PEG2DBFI6LX_SSID) || \
-	 (pid == SILICOM_PEG2DBFI6ZX_SSID) || \
-	 (pid == SILICOM_PEG4BPI6FC_SSID) || \
-	 (pid == SILICOM_PEG4BPFI6FCLX_SSID) || \
-	 (pid == SILICOM_PEG4BPI6FC_SSID) || \
-	 (pid == SILICOM_M1EG2BPFI6_SSID) || \
-	 (pid == SILICOM_M1EG2BPFI6LX_SSID) || \
-	 (pid == SILICOM_M1EG2BPFI6ZX_SSID) || \
-	 (pid == SILICOM_M1EG4BPFI6_SSID) || \
-	 (pid == SILICOM_M1EG4BPFI6LX_SSID) || \
-	 (pid == SILICOM_M1EG4BPFI6ZX_SSID) || \
-	 (pid == SILICOM_M2EG2BPFI6_SSID) || \
-	 (pid == SILICOM_M2EG2BPFI6LX_SSID) || \
-	 (pid == SILICOM_M2EG2BPFI6ZX_SSID) || \
-	 (pid == SILICOM_M2EG4BPFI6_SSID) || \
-	 (pid == SILICOM_M2EG4BPFI6LX_SSID) || \
-	 (pid == SILICOM_M2EG4BPFI6ZX_SSID) || \
-	 (pid == SILICOM_PEG4BPFI6FCZX_SSID))
-
-#define PEG5_IF_SERIES(pid) \
-	((pid == SILICOM_PEG4BPI6_SSID) || \
-	 (pid == SILICOM_PEG2BPI6_SSID) || \
-	 (pid == SILICOM_PEG4BPI6FC_SSID) || \
-	 (pid == SILICOM_PEG6BPI6_SSID) || \
-	 (pid == SILICOM_PEG2BPI6SC6_SSID) || \
-	 (pid == SILICOM_MEG2BPI6_SSID) || \
-	 (pid == SILICOM_XEG2BPI6_SSID) || \
-	 (pid == SILICOM_MEG4BPI6_SSID) || \
-	 (pid == SILICOM_M1EG2BPI6_SSID) || \
-	 (pid == SILICOM_M1EG4BPI6_SSID) || \
-	 (pid == SILICOM_M1EG6BPI6_SSID) || \
-	 (pid == SILICOM_PEG6BPI_SSID) || \
-	 (pid == SILICOM_PEG4BPIL_SSID) || \
-	 (pid == SILICOM_PEG2BISC6_SSID) || \
-	 (pid == SILICOM_PEG2BPI5_SSID))
-
-#define PEG80_IF_SERIES(pid) \
-	((pid == SILICOM_M1E2G4BPi80_SSID) || \
-	 (pid == SILICOM_M6E2G8BPi80_SSID) || \
-	 (pid == SILICOM_PE2G4BPi80L_SSID) || \
-	 (pid == SILICOM_M6E2G8BPi80A_SSID) || \
-	 (pid == SILICOM_PE2G2BPi35_SSID) || \
-	 (pid == SILICOM_PAC1200BPi35_SSID) || \
-	 (pid == SILICOM_PE2G4BPi35_SSID) || \
-	 (pid == SILICOM_PE2G4BPi35L_SSID) || \
-	 (pid == SILICOM_PE2G6BPi35_SSID) || \
-	 (pid == SILICOM_PE2G2BPi80_SSID) || \
-	 (pid == SILICOM_PE2G4BPi80_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi80_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi80LX_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi80_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi80LX_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi80ZX_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi35_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi35LX_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi35ZX_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi35_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi35LX_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi35ZX_SSID))
-
-#define PEGF80_IF_SERIES(pid) \
-	((pid == SILICOM_PE2G4BPFi80_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi80LX_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
-	 (pid == SILICOM_M1E2G4BPFi80_SSID) || \
-	 (pid == SILICOM_M1E2G4BPFi80LX_SSID) || \
-	 (pid == SILICOM_M1E2G4BPFi80ZX_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi80_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi80LX_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi80ZX_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi35_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi35LX_SSID) || \
-	 (pid == SILICOM_PE2G2BPFi35ZX_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi35_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi35LX_SSID) || \
-	 (pid == SILICOM_PE2G4BPFi35ZX_SSID))
-
-#define BP10G9_IF_SERIES(pid) \
-	((pid == INTEL_PE210G2SPI9_SSID) || \
-	 (pid == SILICOM_M1E10G2BPI9CX4_SSID) || \
-	 (pid == SILICOM_M1E10G2BPI9SR_SSID) || \
-	 (pid == SILICOM_M1E10G2BPI9LR_SSID) || \
-	 (pid == SILICOM_M1E10G2BPI9T_SSID) || \
-	 (pid == SILICOM_M2E10G2BPI9CX4_SSID) || \
-	 (pid == SILICOM_M2E10G2BPI9SR_SSID) || \
-	 (pid == SILICOM_M2E10G2BPI9LR_SSID) || \
-	 (pid == SILICOM_M2E10G2BPI9T_SSID) || \
-	 (pid == SILICOM_PE210G2BPI9CX4_SSID) || \
-	 (pid == SILICOM_PE210G2BPI9SR_SSID) || \
-	 (pid == SILICOM_PE210G2BPI9LR_SSID) || \
-	 (pid == SILICOM_PE210G2DBi9SR_SSID) || \
-	 (pid == SILICOM_PE210G2DBi9SRRB_SSID) || \
-	 (pid == SILICOM_PE210G2DBi9LR_SSID) || \
-	 (pid == SILICOM_PE210G2DBi9LRRB_SSID) || \
-	 (pid == SILICOM_PE310G4DBi940SR_SSID) || \
-	 (pid == SILICOM_PEG2BISC6_SSID) || \
-	 (pid == SILICOM_PE310G4BPi9T_SSID) || \
-	 (pid == SILICOM_PE310G4BPi9SR_SSID) || \
-	 (pid == SILICOM_PE310G4BPi9LR_SSID) || \
-	 (pid == SILICOM_PE210G2BPI9T_SSID))
-
-/*******************************************************/
-/* 1G INTERFACE ****************************************/
-/*******************************************************/
-
-/* Intel Registers */
-#define BPCTLI_CTRL          0x00000
-#define BPCTLI_CTRL_SWDPIO0  0x00400000
-#define BPCTLI_CTRL_SWDPIN0  0x00040000
-
-#define BPCTLI_CTRL_EXT 0x00018	/* Extended Device Control - RW */
-#define BPCTLI_STATUS   0x00008	/* Device Status - RO */
-
-/* HW related */
-#define BPCTLI_CTRL_EXT_SDP6_DATA 0x00000040	/* Value of SW
-										     * Defineable Pin 6
-										     */
-#define BPCTLI_CTRL_EXT_SDP7_DATA 0x00000080	/* Value of SW
-										     * Defineable Pin 7
-										     */
-#define BPCTLI_CTRL_SDP0_DATA     0x00040000	/* SWDPIN 0 value */
-#define BPCTLI_CTRL_EXT_SDP6_DIR  0x00000400	/* Direction of SDP6
-										   * 0=in 1=out
-										   */
-#define BPCTLI_CTRL_EXT_SDP7_DIR  0x00000800	/* Direction of SDP7
-										   * 0=in 1=out
-										   */
-#define BPCTLI_CTRL_SDP0_DIR      0x00400000	/* SDP0 Input or output */
-#define BPCTLI_CTRL_SWDPIN1       0x00080000
-#define BPCTLI_CTRL_SDP1_DIR      0x00800000
-
-#define BPCTLI_STATUS_LU          0x00000002	/* Link up.0=no,1=link */
-
-#define BPCTLI_CTRL_SDP0_SHIFT     18
-#define BPCTLI_CTRL_EXT_SDP6_SHIFT 6
-
-#define BPCTLI_STATUS_TBIMODE     0x00000020
-#define BPCTLI_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
-#define BPCTLI_CTRL_EXT_LINK_MODE_MASK         0x00C00000
-
-#define BPCTLI_CTRL_EXT_MCLK_DIR  BPCTLI_CTRL_EXT_SDP7_DIR
-#define BPCTLI_CTRL_EXT_MCLK_DATA BPCTLI_CTRL_EXT_SDP7_DATA
-#define BPCTLI_CTRL_EXT_MDIO_DIR  BPCTLI_CTRL_EXT_SDP6_DIR
-#define BPCTLI_CTRL_EXT_MDIO_DATA BPCTLI_CTRL_EXT_SDP6_DATA
-
-#define BPCTLI_CTRL_EXT_MCLK_DIR5  BPCTLI_CTRL_SDP1_DIR
-#define BPCTLI_CTRL_EXT_MCLK_DATA5 BPCTLI_CTRL_SWDPIN1
-#define BPCTLI_CTRL_EXT_MCLK_DIR80  BPCTLI_CTRL_EXT_SDP6_DIR
-#define BPCTLI_CTRL_EXT_MCLK_DATA80 BPCTLI_CTRL_EXT_SDP6_DATA
-#define BPCTLI_CTRL_EXT_MDIO_DIR5  BPCTLI_CTRL_SWDPIO0
-#define BPCTLI_CTRL_EXT_MDIO_DATA5 BPCTLI_CTRL_SWDPIN0
-#define BPCTLI_CTRL_EXT_MDIO_DIR80  BPCTLI_CTRL_SWDPIO0
-#define BPCTLI_CTRL_EXT_MDIO_DATA80 BPCTLI_CTRL_SWDPIN0
-
-#define BPCTL_WRITE_REG(a, reg, value) \
-	(writel((value), (void *)(((a)->mem_map) + BPCTLI_##reg)))
-
-#define BPCTL_READ_REG(a, reg) ( \
-	readl((void *)((a)->mem_map) + BPCTLI_##reg))
-
-#define BPCTL_WRITE_FLUSH(a) BPCTL_READ_REG(a, STATUS)
-
-#define BPCTL_BP_WRITE_REG(a, reg, value) ({ \
-	BPCTL_WRITE_REG(a, reg, value); \
-	BPCTL_WRITE_FLUSH(a); })
-
-/**************************************************************/
-/************** 82575 Interface********************************/
-/**************************************************************/
-
-#define BPCTLI_MII_CR_POWER_DOWN       0x0800
-#define BPCTLI_PHY_CONTROL      0x00	/* Control Register */
-#define BPCTLI_MDIC     0x00020	/* MDI Control - RW */
-#define BPCTLI_IGP01E1000_PHY_PAGE_SELECT        0x1F	/* Page Select */
-#define BPCTLI_MAX_PHY_REG_ADDRESS    0x1F	/* 5 bit address bus (0-0x1F) */
-
-#define BPCTLI_MDIC_DATA_MASK 0x0000FFFF
-#define BPCTLI_MDIC_REG_MASK  0x001F0000
-#define BPCTLI_MDIC_REG_SHIFT 16
-#define BPCTLI_MDIC_PHY_MASK  0x