diff options
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-02-13 15:31:38 +0200 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-04-17 08:10:19 +0300 |
| commit | f7018c21350204c4cf628462f229d44d03545254 (patch) | |
| tree | 408787177164cf51cc06f7aabdb04fcff8d2b6aa /drivers/video/amifb.c | |
| parent | c26ef3eb3c11274bad1b64498d0a134f85755250 (diff) | |
video: move fbdev to drivers/video/fbdev
The drivers/video directory is a mess. It contains generic video related
files, directories for backlight, console, linux logo, lots of fbdev
device drivers, fbdev framework files.
Make some order into the chaos by creating drivers/video/fbdev
directory, and move all fbdev related files there.
No functionality is changed, although I guess it is possible that some
subtle Makefile build order related issue could be created by this
patch.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/video/amifb.c')
| -rw-r--r-- | drivers/video/amifb.c | 3792 |
1 files changed, 0 insertions, 3792 deletions
diff --git a/drivers/video/amifb.c b/drivers/video/amifb.c deleted file mode 100644 index 518f790ef88a..000000000000 --- a/drivers/video/amifb.c +++ /dev/null @@ -1,3792 +0,0 @@ -/* - * linux/drivers/video/amifb.c -- Amiga builtin chipset frame buffer device - * - * Copyright (C) 1995-2003 Geert Uytterhoeven - * - * with work by Roman Zippel - * - * - * This file is based on the Atari frame buffer device (atafb.c): - * - * Copyright (C) 1994 Martin Schaller - * Roman Hodek - * - * with work by Andreas Schwab - * Guenther Kelleter - * - * and on the original Amiga console driver (amicon.c): - * - * Copyright (C) 1993 Hamish Macdonald - * Greg Harp - * Copyright (C) 1994 David Carter [carter@compsci.bristol.ac.uk] - * - * with work by William Rucklidge (wjr@cs.cornell.edu) - * Geert Uytterhoeven - * Jes Sorensen (jds@kom.auc.dk) - * - * - * History: - * - * - 24 Jul 96: Copper generates now vblank interrupt and - * VESA Power Saving Protocol is fully implemented - * - 14 Jul 96: Rework and hopefully last ECS bugs fixed - * - 7 Mar 96: Hardware sprite support by Roman Zippel - * - 18 Feb 96: OCS and ECS support by Roman Zippel - * Hardware functions completely rewritten - * - 2 Dec 95: AGA version by Geert Uytterhoeven - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/delay.h> -#include <linux/interrupt.h> -#include <linux/fb.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/platform_device.h> -#include <linux/uaccess.h> - -#include <asm/irq.h> -#include <asm/amigahw.h> -#include <asm/amigaints.h> -#include <asm/setup.h> - -#include "c2p.h" - - -#define DEBUG - -#if !defined(CONFIG_FB_AMIGA_OCS) && !defined(CONFIG_FB_AMIGA_ECS) && !defined(CONFIG_FB_AMIGA_AGA) -#define CONFIG_FB_AMIGA_OCS /* define at least one fb driver, this will change later */ -#endif - -#if !defined(CONFIG_FB_AMIGA_OCS) -# define IS_OCS (0) -#elif defined(CONFIG_FB_AMIGA_ECS) || defined(CONFIG_FB_AMIGA_AGA) -# define IS_OCS (chipset == TAG_OCS) -#else -# define CONFIG_FB_AMIGA_OCS_ONLY -# define IS_OCS (1) -#endif - -#if !defined(CONFIG_FB_AMIGA_ECS) -# define IS_ECS (0) -#elif defined(CONFIG_FB_AMIGA_OCS) || defined(CONFIG_FB_AMIGA_AGA) -# define IS_ECS (chipset == TAG_ECS) -#else -# define CONFIG_FB_AMIGA_ECS_ONLY -# define IS_ECS (1) -#endif - -#if !defined(CONFIG_FB_AMIGA_AGA) -# define IS_AGA (0) -#elif defined(CONFIG_FB_AMIGA_OCS) || defined(CONFIG_FB_AMIGA_ECS) -# define IS_AGA (chipset == TAG_AGA) -#else -# define CONFIG_FB_AMIGA_AGA_ONLY -# define IS_AGA (1) -#endif - -#ifdef DEBUG -# define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args) -#else -# define DPRINTK(fmt, args...) -#endif - -/******************************************************************************* - - - Generic video timings - --------------------- - - Timings used by the frame buffer interface: - - +----------+---------------------------------------------+----------+-------+ - | | ^ | | | - | | |upper_margin | | | - | | v | | | - +----------###############################################----------+-------+ - | # ^ # | | - | # | # | | - | # | # | | - | # | # | | - | left # | # right | hsync | - | margin # | xres # margin | len | - |<-------->#<---------------+--------------------------->#<-------->|<----->| - | # | # | | - | # | # | | - | # | # | | - | # |yres # | | - | # | # | | - | # | # | | - | # | # | | - | # | # | | - | # | # | | - | # | # | | - | # | # | | - | # | # | | - | # v # | | - +----------###############################################----------+-------+ - | | ^ | | | - | | |lower_margin | | | - | | v | | | - +----------+---------------------------------------------+----------+-------+ - | | ^ | | | - | | |vsync_len | | | - | | v | | | - +----------+---------------------------------------------+----------+-------+ - - - Amiga video timings - ------------------- - - The Amiga native chipsets uses another timing scheme: - - - hsstrt: Start of horizontal synchronization pulse - - hsstop: End of horizontal synchronization pulse - - htotal: Last value on the line (i.e. line length = htotal + 1) - - vsstrt: Start of vertical synchronization pulse - - vsstop: End of vertical synchronization pulse - - vtotal: Last line value (i.e. number of lines = vtotal + 1) - - hcenter: Start of vertical retrace for interlace - - You can specify the blanking timings independently. Currently I just set - them equal to the respective synchronization values: - - - hbstrt: Start of horizontal blank - - hbstop: End of horizontal blank - - vbstrt: Start of vertical blank - - vbstop: End of vertical blank - - Horizontal values are in color clock cycles (280 ns), vertical values are in - scanlines. - - (0, 0) is somewhere in the upper-left corner :-) - - - Amiga visible window definitions - -------------------------------- - - Currently I only have values for AGA, SHRES (28 MHz dotclock). Feel free to - make corrections and/or additions. - - Within the above synchronization specifications, the visible window is - defined by the following parameters (actual register resolutions may be - different; all horizontal values are normalized with respect to the pixel - clock): - - - diwstrt_h: Horizontal start of the visible window - - diwstop_h: Horizontal stop + 1(*) of the visible window - - diwstrt_v: Vertical start of the visible window - - diwstop_v: Vertical stop of the visible window - - ddfstrt: Horizontal start of display DMA - - ddfstop: Horizontal stop of display DMA - - hscroll: Horizontal display output delay - - Sprite positioning: - - - sprstrt_h: Horizontal start - 4 of sprite - - sprstrt_v: Vertical start of sprite - - (*) Even Commodore did it wrong in the AGA monitor drivers by not adding 1. - - Horizontal values are in dotclock cycles (35 ns), vertical values are in - scanlines. - - (0, 0) is somewhere in the upper-left corner :-) - - - Dependencies (AGA, SHRES (35 ns dotclock)) - ------------------------------------------- - - Since there are much more parameters for the Amiga display than for the - frame buffer interface, there must be some dependencies among the Amiga - display parameters. Here's what I found out: - - - ddfstrt and ddfstop are best aligned to 64 pixels. - - the chipset needs 64 + 4 horizontal pixels after the DMA start before - the first pixel is output, so diwstrt_h = ddfstrt + 64 + 4 if you want - to display the first pixel on the line too. Increase diwstrt_h for - virtual screen panning. - - the display DMA always fetches 64 pixels at a time (fmode = 3). - - ddfstop is ddfstrt+#pixels - 64. - - diwstop_h = diwstrt_h + xres + 1. Because of the additional 1 this can - be 1 more than htotal. - - hscroll simply adds a delay to the display output. Smooth horizontal - panning needs an extra 64 pixels on the left to prefetch the pixels that - `fall off' on the left. - - if ddfstrt < 192, the sprite DMA cycles are all stolen by the bitplane - DMA, so it's best to make the DMA start as late as possible. - - you really don't want to make ddfstrt < 128, since this will steal DMA - cycles from the other DMA channels (audio, floppy and Chip RAM refresh). - - I make diwstop_h and diwstop_v as large as possible. - - General dependencies - -------------------- - - - all values are SHRES pixel (35ns) - - table 1:fetchstart table 2:prefetch table 3:fetchsize - ------------------ ---------------- ----------------- - Pixclock # SHRES|HIRES|LORES # SHRES|HIRES|LORES # SHRES|HIRES|LORES - -------------#------+-----+------#------+-----+------#------+-----+------ - Bus width 1x # 16 | 32 | 64 # 16 | 32 | 64 # 64 | 64 | 64 - Bus width 2x # 32 | 64 | 128 # 32 | 64 | 64 # 64 | 64 | 128 - Bus width 4x # 64 | 128 | 256 # 64 | 64 | 64 # 64 | 128 | 256 - - - chipset needs 4 pixels before the first pixel is output - - ddfstrt must be aligned to fetchstart (table 1) - - chipset needs also prefetch (table 2) to get first pixel data, so - ddfstrt = ((diwstrt_h - 4) & -fetchstart) - prefetch - - for horizontal panning decrease diwstrt_h - - the length of a fetchline must be aligned to fetchsize (table 3) - - if fetchstart is smaller than fetchsize, then ddfstrt can a little bit - moved to optimize use of dma (useful for OCS/ECS overscan displays) - - ddfstop is ddfstrt + ddfsize - fetchsize - - If C= didn't change anything for AGA, then at following positions the - dma bus is already used: - ddfstrt < 48 -> memory refresh - < 96 -> disk dma - < 160 -> audio dma - < 192 -> sprite 0 dma - < 416 -> sprite dma (32 per sprite) - - in accordance with the hardware reference manual a hardware stop is at - 192, but AGA (ECS?) can go below this. - - DMA priorities - -------------- - - Since there are limits on the earliest start value for display DMA and the - display of sprites, I use the following policy on horizontal panning and - the hardware cursor: - - - if you want to start display DMA too early, you lose the ability to - do smooth horizontal panning (xpanstep 1 -> 64). - - if you want to go even further, you lose the hardware cursor too. - - IMHO a hardware cursor is more important for X than horizontal scrolling, - so that's my motivation. - - - Implementation - -------------- - - ami_decode_var() converts the frame buffer values to the Amiga values. It's - just a `straightforward' implementation of the above rules. - - - Standard VGA timings - -------------------- - - xres yres left right upper lower hsync vsync - ---- ---- ---- ----- ----- ----- ----- ----- - 80x25 720 400 27 45 35 12 108 2 - 80x30 720 480 27 45 30 9 108 2 - - These were taken from a XFree86 configuration file, recalculated for a 28 MHz - dotclock (Amigas don't have a 25 MHz dotclock) and converted to frame buffer - generic timings. - - As a comparison, graphics/monitor.h suggests the following: - - xres yres left right upper lower hsync vsync - ---- ---- ---- ----- ----- ----- ----- ----- - - VGA 640 480 52 112 24 19 112 - 2 + - VGA70 640 400 52 112 27 21 112 - 2 - - - - Sync polarities - --------------- - - VSYNC HSYNC Vertical size Vertical total - ----- ----- ------------- -------------- - + + Reserved Reserved - + - 400 414 - - + 350 362 - - - 480 496 - - Source: CL-GD542X Technical Reference Manual, Cirrus Logic, Oct 1992 - - - Broadcast video timings - ----------------------- - - According to the CCIR and RETMA specifications, we have the following values: - - CCIR -> PAL - ----------- - - - a scanline is 64 µs long, of which 52.48 µs are visible. This is about - 736 visible 70 ns pixels per line. - - we have 625 scanlines, of which 575 are visible (interlaced); after - rounding this becomes 576. - - RETMA -> NTSC - ------------- - - - a scanline is 63.5 µs long, of which 53.5 µs are visible. This is about - 736 visible 70 ns pixels per line. - - we have 525 scanlines, of which 485 are visible (interlaced); after - rounding this becomes 484. - - Thus if you want a PAL compatible display, you have to do the following: - - - set the FB_SYNC_BROADCAST flag to indicate that standard broadcast - timings are to be used. - - make sure upper_margin + yres + lower_margin + vsync_len = 625 for an - interlaced, 312 for a non-interlaced and 156 for a doublescanned - display. - - make sure left_margin + xres + right_margin + hsync_len = 1816 for a - SHRES, 908 for a HIRES and 454 for a LORES display. - - the left visible part begins at 360 (SHRES; HIRES:180, LORES:90), - left_margin + 2 * hsync_len must be greater or equal. - - the upper visible part begins at 48 (interlaced; non-interlaced:24, - doublescanned:12), upper_margin + 2 * vsync_len must be greater or - equal. - - ami_encode_var() calculates margins with a hsync of 5320 ns and a vsync - of 4 scanlines - - The settings for a NTSC compatible display are straightforward. - - Note that in a strict sense the PAL and NTSC standards only define the - encoding of the color part (chrominance) of the video signal and don't say - anything about horizontal/vertical synchronization nor refresh rates. - - - -- Geert -- - -*******************************************************************************/ - - - /* - * Custom Chipset Definitions - */ - -#define CUSTOM_OFS(fld) ((long)&((struct CUSTOM*)0)->fld) - - /* - * BPLCON0 -- Bitplane Control Register 0 - */ - -#define BPC0_HIRES (0x8000) -#define BPC0_BPU2 (0x4000) /* Bit plane used count */ -#define BPC0_BPU1 (0x2000) -#define BPC0_BPU0 (0x1000) -#define BPC0_HAM (0x0800) /* HAM mode */ -#define BPC0_DPF (0x0400) /* Double playfield */ -#define BPC0_COLOR (0x0200) /* Enable colorburst */ -#define BPC0_GAUD (0x0100) /* Genlock audio enable */ -#define BPC0_UHRES (0x0080) /* Ultrahi res enable */ -#define BPC0_SHRES (0x0040) /* Super hi res mode */ -#define BPC0_BYPASS (0x0020) /* Bypass LUT - AGA */ -#define BPC0_BPU3 (0x0010) /* AGA */ -#define BPC0_LPEN (0x0008) /* Light pen enable */ -#define BPC0_LACE (0x0004) /* Interlace */ -#define BPC0_ERSY (0x0002) /* External resync */ -#define BPC0_ECSENA (0x0001) /* ECS enable */ - - /* - * BPLCON2 -- Bitplane Control Register 2 - */ - -#define BPC2_ZDBPSEL2 (0x4000) /* Bitplane to be used for ZD - AGA */ -#define BPC2_ZDBPSEL1 (0x2000) -#define BPC2_ZDBPSEL0 (0x1000) -#define BPC2_ZDBPEN (0x0800) /* Enable ZD with ZDBPSELx - AGA */ -#define BPC2_ZDCTEN (0x0400) /* Enable ZD with palette bit #31 - AGA */ -#define BPC2_KILLEHB (0x0200) /* Kill EHB mode - AGA */ -#define BPC2_RDRAM (0x0100) /* Color table accesses read, not write - AGA */ -#define BPC2_SOGEN (0x0080) /* SOG output pin high - AGA */ -#define BPC2_PF2PRI (0x0040) /* PF2 priority over PF1 */ -#define BPC2_PF2P2 (0x0020) /* PF2 priority wrt sprites */ -#define BPC2_PF2P1 (0x0010) -#define BPC2_PF2P0 (0x0008) -#define BPC2_PF1P2 (0x0004) /* ditto PF1 */ -#define BPC2_PF1P1 (0x0002) -#define BPC2_PF1P0 (0x0001) - - /* - * BPLCON3 -- Bitplane Control Register 3 (AGA) - */ - -#define BPC3_BANK2 (0x8000) /* Bits to select color register bank */ -#define BPC3_BANK1 (0x4000) -#define BPC3_BANK0 (0x2000) -#define BPC3_PF2OF2 (0x1000) /* Bits for color table offset when PF2 */ -#define BPC3_PF2OF1 (0x0800) -#define BPC3_PF2OF0 (0x0400) -#define BPC3_LOCT (0x0200) /* Color register writes go to low bits */ -#define BPC3_SPRES1 (0x0080) /* Sprite resolution bits */ -#define BPC3_SPRES0 (0x0040) -#define BPC3_BRDRBLNK (0x0020) /* Border blanked? */ -#define BPC3_BRDRTRAN (0x0010) /* Border transparent? */ -#define BPC3_ZDCLKEN (0x0004) /* ZD pin is 14 MHz (HIRES) clock output */ -#define BPC3_BRDRSPRT (0x0002) /* Sprites in border? */ -#define BPC3_EXTBLKEN (0x0001) /* BLANK programmable */ - - /* - * BPLCON4 -- Bitplane Control Register 4 (AGA) - */ - -#define BPC4_BPLAM7 (0x8000) /* bitplane color XOR field */ -#define BPC4_BPLAM6 (0x4000) -#define BPC4_BPLAM5 (0x2000) -#define BPC4_BPLAM4 (0x1000) -#define BPC4_BPLAM3 (0x0800) -#define BPC4_BPLAM2 (0x0400) -#define BPC4_BPLAM1 (0x0200) -#define BPC4_BPLAM0 (0x0100) -#define BPC4_ESPRM7 (0x0080) /* 4 high bits for even sprite colors */ -#define BPC4_ESPRM6 (0x0040) -#define BPC4_ESPRM5 (0x0020) -#define BPC4_ESPRM4 (0x0010) -#define BPC4_OSPRM7 (0x0008) /* 4 high bits for odd sprite colors */ -#define BPC4_OSPRM6 (0x0004) -#define BPC4_OSPRM5 (0x0002) -#define BPC4_OSPRM4 (0x0001) - - /* - * BEAMCON0 -- Beam Control Register - */ - -#define BMC0_HARDDIS (0x4000) /* Disable hardware limits */ -#define BMC0_LPENDIS (0x2000) /* Disable light pen latch */ -#define BMC0_VARVBEN (0x1000) /* Enable variable vertical blank */ -#define BMC0_LOLDIS (0x0800) /* Disable long/short line toggle */ -#define BMC0_CSCBEN (0x0400) /* Composite sync/blank */ -#define BMC0_VARVSYEN (0x0200) /* Enable variable vertical sync */ -#define BMC0_VARHSYEN (0x0100) /* Enable variable horizontal sync */ -#define BMC0_VARBEAMEN (0x0080) /* Enable variable beam counters */ -#define BMC0_DUAL (0x0040) /* Enable alternate horizontal beam counter */ -#define BMC0_PAL (0x0020) /* Set decodes for PAL */ -#define BMC0_VARCSYEN (0x0010) /* Enable variable composite sync */ -#define BMC0_BLANKEN (0x0008) /* Blank enable (no longer used on AGA) */ -#define BMC0_CSYTRUE (0x0004) /* CSY polarity */ -#define BMC0_VSYTRUE (0x0002) /* VSY polarity */ -#define BMC0_HSYTRUE (0x0001) /* HSY polarity */ - - - /* - * FMODE -- Fetch Mode Control Register (AGA) - */ - -#define FMODE_SSCAN2 (0x8000) /* Sprite scan-doubling */ -#define FMODE_BSCAN2 (0x4000) /* Use PF2 modulus every other line */ -#define FMODE_SPAGEM (0x0008) /* Sprite page mode */ -#define FMODE_SPR32 (0x0004) /* Sprite 32 bit fetch */ -#define FMODE_BPAGEM (0x0002) /* Bitplane page mode */ -#define FMODE_BPL32 (0x0001) /* Bitplane 32 bit fetch */ - - /* - * Tags used to indicate a specific Pixel Clock - * - * clk_shift is the shift value to get the timings in 35 ns units - */ - -enum { TAG_SHRES, TAG_HIRES, TAG_LORES }; - - /* - * Tags used to indicate the specific chipset - */ - -enum { TAG_OCS, TAG_ECS, TAG_AGA }; - - /* - * Tags used to indicate the memory bandwidth - */ - -enum { TAG_FMODE_1, TAG_FMODE_2, TAG_FMODE_4 }; - - - /* - * Clock Definitions, Maximum Display Depth - * - * These depend on the E-Clock or the Chipset, so they are filled in - * dynamically - */ - -static u_long pixclock[3]; /* SHRES/HIRES/LORES: index = clk_shift */ -static u_short maxdepth[3]; /* SHRES/HIRES/LORES: index = clk_shift */ -static u_short maxfmode, chipset; - - - /* - * Broadcast Video Timings - * - * Horizontal values are in 35 ns (SHRES) units - * Vertical values are in interlaced scanlines - */ - -#define PAL_DIWSTRT_H (360) /* PAL Window Limits */ -#define PAL_DIWSTRT_V (48) -#define PAL_HTOTAL (1816) -#define PAL_VTOTAL (625) - -#define NTSC_DIWSTRT_H (360) /* NTSC Window Limits */ -#define NTSC_DIWSTRT_V (40) -#define NTSC_HTOTAL (1816) -#define NTSC_VTOTAL (525) - - - /* - * Various macros - */ - -#define up2(v) (((v) + 1) & -2) -#define down2(v) ((v) & -2) -#define div2(v) ((v)>>1) -#define mod2(v) ((v) & 1) - -#define up4(v) (((v) + 3) & -4) -#define down4(v) ((v) & -4) -#define mul4(v) ((v) << 2) -#define div4(v) ((v)>>2) -#define mod4(v) ((v) & 3) - -#define up8(v) (((v) + 7) & -8) -#define down8(v) ((v) & -8) -#define div8(v) ((v)>>3) -#define mod8(v) ((v) & 7) - -#define up16(v) (((v) + 15) & -16) -#define down16(v) ((v) & -16) -#define div16(v) ((v)>>4) -#define mod16(v) ((v) & 15) - -#define up32(v) (((v) + 31) & -32) -#define down32(v) ((v) & -32) -#define div32(v) ((v)>>5) -#define mod32(v) ((v) & 31) - -#define up64(v) (((v) + 63) & -64) -#define down64(v) ((v) & -64) -#define div64(v) ((v)>>6) -#define mod64(v) ((v) & 63) - -#define upx(x, v) (((v) + (x) - 1) & -(x)) -#define downx(x, v) ((v) & -(x)) -#define modx(x, v) ((v) & ((x) - 1)) - -/* if x1 is not a constant, this macro won't make real sense :-) */ -#ifdef __mc68000__ -#define DIVUL(x1, x2) ({int res; asm("divul %1,%2,%3": "=d" (res): \ - "d" (x2), "d" ((long)((x1) / 0x100000000ULL)), "0" ((long)(x1))); res;}) -#else -/* We know a bit about the numbers, so we can do it this way */ -#define DIVUL(x1, x2) ((((long)((unsigned long long)x1 >> 8) / x2) << 8) + \ - ((((long)((unsigned long long)x1 >> 8) % x2) << 8) / x2)) -#endif - -#define highw(x) ((u_long)(x)>>16 & 0xffff) -#define loww(x) ((u_long)(x) & 0xffff) - -#define custom amiga_custom - -#define VBlankOn() custom.intena = IF_SETCLR|IF_COPER -#define VBlankOff() custom.intena = IF_COPER - - - /* - * Chip RAM we reserve for the Frame Buffer - * - * This defines the Maximum Virtual Screen Size - * (Setable per kernel options?) - */ - -#define VIDEOMEMSIZE_AGA_2M (1310720) /* AGA (2MB) : max 1280*1024*256 */ -#define VIDEOMEMSIZE_AGA_1M (786432) /* AGA (1MB) : max 1024*768*256 */ -#define VIDEOMEMSIZE_ECS_2M (655360) /* ECS (2MB) : max 1280*1024*16 */ -#define VIDEOMEMSIZE_ECS_1M (393216) /* ECS (1MB) : max 1024*768*16 */ -#define VIDEOMEMSIZE_OCS (262144) /* OCS : max ca. 800*600*16 */ - -#define SPRITEMEMSIZE (64 * 64 / 4) /* max 64*64*4 */ -#define DUMMYSPRITEMEMSIZE (8) -static u_long spritememory; - -#define CHIPRAM_SAFETY_LIMIT (16384) - -static u_long videomemory; - - /* - * This is the earliest allowed start of fetching display data. - * Only if you really want no hardware cursor and audio, - * set this to 128, but let it better at 192 - */ - -static u_long min_fstrt = 192; - -#define assignchunk(name, type, ptr, size) \ -{ \ - (name) = (type)(ptr); \ - ptr += size; \ -} - - - /* - * Copper Instructions - */ - -#define CMOVE(val, reg) (CUSTOM_OFS(reg) << 16 | (val)) -#define CMOVE2(val, reg) ((CUSTOM_OFS(reg) + 2) << 16 | (val)) -#define CWAIT(x, y) (((y) & 0x1fe) << 23 | ((x) & 0x7f0) << 13 | 0x0001fffe) -#define CEND (0xfffffffe) - - -typedef union { - u_long l; - u_short w[2]; -} copins; - -static struct copdisplay { - copins *init; - copins *wait; - copins *list[2][2]; - copins *rebuild[2]; -} copdisplay; - -static u_short currentcop = 0; - - /* - * Hardware Cursor API Definitions - * These used to be in linux/fb.h, but were preliminary and used by - * amifb only anyway - */ - -#define FBIOGET_FCURSORINFO 0x4607 -#define FBIOGET_VCURSORINFO 0x4608 -#define FBIOPUT_VCURSORINFO 0x4609 -#define FBIOGET_CURSORSTATE 0x460A -#define FBIOPUT_CURSORSTATE 0x460B - - -struct fb_fix_cursorinfo { - __u16 crsr_width; /* width and height of the cursor in */ - __u16 crsr_height; /* pixels (zero if no cursor) */ - __u16 crsr_xsize; /* cursor size in display pixels */ - __u16 crsr_ysize; - __u16 crsr_color1; /* colormap entry for cursor color1 */ - __u16 crsr_color2; /* colormap entry for cursor color2 */ -}; - -struct fb_var_cursorinfo { - __u16 width; - __u16 height; - __u16 xspot; - __u16 yspot; - __u8 data[1]; /* field with [height][width] */ -}; - -struct fb_cursorstate { - __s16 xoffset; - __s16 yoffset; - __u16 mode; -}; - -#define FB_CURSOR_OFF 0 -#define FB_CURSOR_ON 1 -#define FB_CURSOR_FLASH 2 - - - /* - * Hardware Cursor - */ - -static int cursorrate = 20; /* Number of frames/flash toggle */ -static u_short cursorstate = -1; -static u_short cursormode = FB_CURSOR_OFF; - -static u_short *lofsprite, *shfsprite, *dummysprite; - - /* - * Current Video Mode - */ - -struct amifb_par { - - /* General Values */ - - int xres; /* vmode */ - int yres; /* vmode */ - int vxres; /* vmode */ - int vyres; /* vmode */ - int xoffset; /* vmode */ - int yoffset; /* vmode */ - u_short bpp; /* vmode */ - u_short clk_shift; /* vmode */ - u_short line_shift; /* vmode */ - int vmode; /* vmode */ - u_short diwstrt_h; /* vmode */ - u_short diwstop_h; /* vmode */ - u_short diwstrt_v; /* vmode */ - u_short diwstop_v; /* vmode */ - u_long next_line; /* modulo for next line */ - u_long next_plane; /* modulo for next plane */ - - /* Cursor Values */ - - struct { - short crsr_x; /* movecursor */ - short crsr_y; /* movecursor */ - short spot_x; - short spot_y; - u_short height; - u_short width; - u_short fmode; - } crsr; - - /* OCS Hardware Registers */ - - u_long bplpt0; /* vmode, pan (Note: physical address) */ - u_long bplpt0wrap; /* vmode, pan (Note: physical address) */ - u_short ddfstrt; - u_short ddfstop; - u_short bpl1mod; - u_short bpl2mod; - u_short bplcon0; /* vmode */ - u_short bplcon1; /* vmode */ - u_short htotal; /* vmode */ - u_short vtotal; /* vmode */ - - /* Additional ECS Hardware Registers */ - - u_short bplcon3; /* vmode */ - u_short beamcon0; /* vmode */ - u_short hsstrt; /* vmode */ - u_short hsstop; /* vmode */ - u_short hbstrt; /* vmode */ - u_short hbstop; /* vmode */ - u_short vsstrt; /* vmode */ - u_short vsstop; /* vmode */ - u_short vbstrt; /* vmode */ - u_short vbstop; /* vmode */ - u_short hcenter; /* vmode */ - - /* Additional AGA Hardware Registers */ - - u_short fmode; /* vmode */ -}; - - - /* - * Saved color entry 0 so we can restore it when unblanking - */ - -static u_char red0, green0, blue0; - - -#if defined(CONFIG_FB_AMIGA_ECS) -static u_short ecs_palette[32]; -#endif - - - /* - * Latches for Display Changes during VBlank - */ - -static u_short do_vmode_full = 0; /* Change the Video Mode */ -static u_short do_vmode_pan = 0; /* Update the Video Mode */ -static short do_blank = 0; /* (Un)Blank the Screen (±1) */ -static u_short do_cursor = 0; /* Move the Cursor */ - - - /* - * Various Flags - */ - -static u_short is_blanked = 0; /* Screen is Blanked */ -static u_short is_lace = 0; /* Screen is laced */ - - /* - * Predefined Video Modes - * - */ - -static struct fb_videomode ami_modedb[] __initdata = { - - /* - * AmigaOS Video Modes - * - * If you change these, make sure to update DEFMODE_* as well! - */ - - { - /* 640x200, 15 kHz, 60 Hz (NTSC) */ - "ntsc", 60, 640, 200, TAG_HIRES, 106, 86, 44, 16, 76, 2, - FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, { - /* 640x400, 15 kHz, 60 Hz interlaced (NTSC) */ - "ntsc-lace", 60, 640, 400, TAG_HIRES, 106, 86, 88, 33, 76, 4, - FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP - }, { - /* 640x256, 15 kHz, 50 Hz (PAL) */ - "pal", 50, 640, 256, TAG_HIRES, 106, 86, 40, 14, 76, 2, - FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, { - /* 640x512, 15 kHz, 50 Hz interlaced (PAL) */ - "pal-lace", 50, 640, 512, TAG_HIRES, 106, 86, 80, 29, 76, 4, - FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP - }, { - /* 640x480, 29 kHz, 57 Hz */ - "multiscan", 57, 640, 480, TAG_SHRES, 96, 112, 29, 8, 72, 8, - 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, { - /* 640x960, 29 kHz, 57 Hz interlaced */ - "multiscan-lace", 57, 640, 960, TAG_SHRES, 96, 112, 58, 16, 72, - 16, - 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP - }, { - /* 640x200, 15 kHz, 72 Hz */ - "euro36", 72, 640, 200, TAG_HIRES, 92, 124, 6, 6, 52, 5, - 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, { - /* 640x400, 15 kHz, 72 Hz interlaced */ - "euro36-lace", 72, 640, 400, TAG_HIRES, 92, 124, 12, 12, 52, - 10, - 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP - }, { - /* 640x400, 29 kHz, 68 Hz */ - "euro72", 68, 640, 400, TAG_SHRES, 164, 92, 9, 9, 80, 8, - 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, { - /* 640x800, 29 kHz, 68 Hz interlaced */ - "euro72-lace", 68, 640, 800, TAG_SHRES, 164, 92, 18, 18, 80, - 16, - 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP - }, { - /* 800x300, 23 kHz, 70 Hz */ - "super72", 70, 800, 300, TAG_SHRES, 212, 140, 10, 11, 80, 7, - 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, { - /* 800x600, 23 kHz, 70 Hz interlaced */ - "super72-lace", 70, 800, 600, TAG_SHRES, 212, 140, 20, 22, 80, - 14, - 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP - }, { - /* 640x200, 27 kHz, 57 Hz doublescan */ - "dblntsc", 57, 640, 200, TAG_SHRES, 196, 124, 18, 17, 80, 4, - 0, FB_VMODE_DOUBLE | FB_VMODE_YWRAP - }, { - /* 640x400, 27 kHz, 57 Hz */ - "dblntsc-ff", 57, 640, 400, TAG_SHRES, 196, 124, 36, 35, 80, 7, - 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, { - /* 640x800, 27 kHz, 57 Hz interlaced */ - "dblntsc-lace", 57, 640, 800, TAG_SHRES, 196, 124, 72, 70, 80, - 14, - 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP - }, { - /* 640x256, 27 kHz, 47 Hz doublescan */ - "dblpal", 47, 640, 256, TAG_SHRES, 196, 124, 14, 13, 80, 4, - 0, FB_VMODE_DOUBLE | FB_VMODE_YWRAP - }, { - /* 640x512, 27 kHz, 47 Hz */ - "dblpal-ff", 47, 640, 512, TAG_SHRES, 196, 124, 28, 27, 80, 7, - 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, { - /* 640x1024, 27 kHz, 47 Hz interlaced */ - "dblpal-lace", 47, 640, 1024, TAG_SHRES, 196, 124, 56, 54, 80, - 14, - 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP - }, - - /* - * VGA Video Modes - */ - - { - /* 640x480, 31 kHz, 60 Hz (VGA) */ - "vga", 60, 640, 480, TAG_SHRES, 64, 96, 30, 9, 112, 2, - 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, { - /* 640x400, 31 kHz, 70 Hz (VGA) */ - "vga70", 70, 640, 400, TAG_SHRES, 64, 96, 35, 12, 112, 2, - FB_SYNC_VERT_HIGH_ACT | FB_SYNC_COMP_HIGH_ACT, - FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, - -#if 0 - - /* - * A2024 video modes - * These modes don't work yet because there's no A2024 driver. - */ - - { - /* 1024x800, 10 Hz */ - "a2024-10", 10, 1024, 800, TAG_HIRES, 0, 0, 0, 0, 0, 0, - 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - }, { - /* 1024x800, 15 Hz */ - "a2024-15", 15, 1024, 800, TAG_HIRES, 0, 0, 0, 0, 0, 0, - 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP - } -#endif -}; - -#define NUM_TOTAL_MODES ARRAY_SIZE(ami_modedb) - -static char *mode_option __initdata = NULL; -static int round_down_bpp = 1; /* for mode probing */ - - /* - * Some default modes - */ - - -#define DEFMODE_PAL 2 /* "pal" for PAL OCS/ECS */ -#define DEFMODE_NTSC 0 /* "ntsc" for NTSC OCS/ECS */ -#define DEFMODE_AMBER_PAL 3 /* "pal-lace" for flicker fixed PAL (A3000) */ -#define DEFMODE_AMBER_NTSC 1 /* "ntsc-lace" for flicker fixed NTSC (A3000) */ -#define DEFMODE_AGA 19 /* "vga70" for AGA */ - - -static int amifb_ilbm = 0; /* interleaved or normal bitplanes */ - -static u32 amifb_hfmin __initdata; /* monitor hfreq lower limit (Hz) */ -static u32 amifb_hfmax __initdata; /* monitor hfreq upper limit (Hz) */ -static u16 amifb_vfmin __initdata; /* monitor vfreq lower limit (Hz) */ -static u16 amifb_vfmax __initdata; /* monitor vfreq upper limit (Hz) */ - - - /* - * Macros for the conversion from real world values to hardware register - * values - * - * This helps us to keep our attention on the real stuff... - * - * Hardware limits for AGA: - * - * parameter min max step - * --------- --- ---- ---- - * diwstrt_h 0 2047 1 - * diwstrt_v 0 2047 1 - * diwstop_h 0 4095 1 - * diwstop_v 0 4095 1 - * - * ddfstrt 0 2032 16 - * ddfstop 0 2032 16 - * - * htotal 8 2048 8 - * hsstrt 0 2040 8 - * hsstop 0 2040 8 - * vtotal 1 4096 1 - * vsstrt 0 4095 1 - * vsstop 0 4095 1 - * hcenter 0 2040 8 - * - * hbstrt 0 2047 1 - * hbstop 0 2047 1 - * vbstrt 0 4095 1 - * vbstop 0 4095 1 - * - * Horizontal values are in 35 ns (SHRES) pixels - * Vertical values are in half scanlines - */ - -/* bplcon1 (smooth scrolling) */ - -#define hscroll2hw(hscroll) \ - (((hscroll) << 12 & 0x3000) | ((hscroll) << 8 & 0xc300) | \ - ((hscroll) << 4 & 0x0c00) | ((hscroll) << 2 & 0x00f0) | \ - ((hscroll)>>2 & 0x000f)) - -/* diwstrt/diwstop/diwhigh (visible display window) */ - -#define diwstrt2hw(diwstrt_h, diwstrt_v) \ - (((diwstrt_v) << 7 & 0xff00) | ((diwstrt_h)>>2 & 0x00ff)) -#define diwstop2hw(diwstop_h, diwstop_v) \ - (((diwstop_v) << 7 & 0xff00) | ((diwstop_h)>>2 & 0x00ff)) -#define diwhigh2hw(diwstrt_h, diwstrt_v, diwstop_h, diwstop_v) \ - (((diwstop_h) << 3 & 0x2000) | ((diwstop_h) << 11 & 0x1800) | \ - ((diwstop_v)>>1 & 0x0700) | ((diwstrt_h)>>5 & 0x0020) | \ - ((diwstrt_h) << 3 & 0x0018) | ((diwstrt_v)>>9 & 0x0007)) - -/* ddfstrt/ddfstop (display DMA) */ - -#define ddfstrt2hw(ddfstrt) div8(ddfstrt) -#define ddfstop2hw(ddfstop) div8(ddfstop) - -/* hsstrt/hsstop/htotal/vsstrt/vsstop/vtotal/hcenter (sync timings) */ - -#define hsstrt2hw(hsstrt) (div8(hsstrt)) -#define hsstop2hw(hsstop) (div8(hsstop)) -#define htotal2hw(htotal) (div8(htotal) - 1) -#define vsstrt2hw(vsstrt) (div2(vsstrt)) -#define vsstop2hw(vsstop) (div2(vsstop)) -#define vtotal2hw(vtotal) (div2(vtotal) - 1) -#define hcenter2hw(htotal) (div8(htotal)) - -/* hbstrt/hbstop/vbstrt/vbstop (blanking timings) */ - -#define hbstrt2hw(hbstrt) (((hbstrt) << 8 & 0x0700) | ((hbstrt)>>3 & 0x00ff)) -#define hbstop2hw(hbstop) (((hbstop) << 8 & 0x0700) | ((hbstop)>>3 & 0x00ff)) -#define vbstrt2hw(vbstrt) (div2(vbs |