diff options
| author | Andiry Xu <andiry.xu@amd.com> | 2011-01-06 15:43:39 +0800 |
|---|---|---|
| committer | Sarah Sharp <sarah.a.sharp@linux.intel.com> | 2011-03-13 18:07:09 -0700 |
| commit | bdfca5025a159c8bb966e3b87b0c084dd1f831a9 (patch) | |
| tree | c49bd0a596410686480933ac60beb2360c8a8ee9 /drivers/usb/host | |
| parent | 019a35f1142b1cd153c8a38338515e633ec0cf77 (diff) | |
xHCI: prolong host controller halt time limit
xHCI 1.0 spec specifies the xHC shall halt within 16ms after software clears
Run/Stop bit. In xHCI 0.96 spec the time limit is 16 microframes (2ms), it's
too short and often cause dmesg shows "Host controller not halted, aborting
reset." message when rmmod xhci-hcd.
Modify the time limit to comply with xHCI 1.0 specification and prevents the
warning message showing when remove xhci-hcd.
Signed-off-by: Andiry Xu <andiry.xu@amd.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Diffstat (limited to 'drivers/usb/host')
| -rw-r--r-- | drivers/usb/host/xhci-ext-caps.h | 4 | ||||
| -rw-r--r-- | drivers/usb/host/xhci.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h index 78c4edac1db1..ce5c9e51748e 100644 --- a/drivers/usb/host/xhci-ext-caps.h +++ b/drivers/usb/host/xhci-ext-caps.h @@ -19,8 +19,8 @@ * along with this program; if not, write to the Free Software Foundation, * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -/* Up to 16 microframes to halt an HC - one microframe is 125 microsectonds */ -#define XHCI_MAX_HALT_USEC (16*125) +/* Up to 16 ms to halt an HC */ +#define XHCI_MAX_HALT_USEC (16*1000) /* HC not running - set to 1 when run/stop bit is cleared. */ #define XHCI_STS_HALT (1<<0) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 023175eab07d..8dfa67ff5fac 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -93,7 +93,7 @@ void xhci_quiesce(struct xhci_hcd *xhci) * * Disable any IRQs and clear the run/stop bit. * HC will complete any current and actively pipelined transactions, and - * should halt within 16 microframes of the run/stop bit being cleared. + * should halt within 16 ms of the run/stop bit being cleared. * Read HC Halted bit in the status register to see when the HC is finished. * XXX: shouldn't we set HC_STATE_HALT here somewhere? */ |