diff options
author | Sudip Mukherjee <sudipm.mukherjee@gmail.com> | 2019-11-17 20:24:35 +0000 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-11-18 18:49:11 +0100 |
commit | 55ed51fff224a51dfb768cfac3e4498888474c87 (patch) | |
tree | a407967a88c81f483a5a19bf9eae86bf66e382d3 /drivers/tty/serial/samsung_tty.c | |
parent | 50b2b571c5f3df721fc81bf9a12c521dfbe019ba (diff) |
{tty: serial, nand: onenand}: samsung: rename to fix build warning
Any arm config which has 'CONFIG_MTD_ONENAND_SAMSUNG=m' and
'CONFIG_SERIAL_SAMSUNG=m' gives a build warning:
warning: same module names found:
drivers/tty/serial/samsung.ko
drivers/mtd/nand/onenand/samsung.ko
Rename both drivers/tty/serial/samsung.c to
drivers/tty/serial/samsung_tty.c and drivers/mtd/nand/onenand/samsung.c
drivers/mtd/nand/onenand/samsung_mtd.c to fix the warning.
Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
Acked-by: Richard Weinberger <richard@nod.at>
Link: https://lore.kernel.org/r/20191117202435.28127-1-sudipm.mukherjee@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial/samsung_tty.c')
-rw-r--r-- | drivers/tty/serial/samsung_tty.c | 2595 |
1 files changed, 2595 insertions, 0 deletions
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c new file mode 100644 index 000000000000..83fd51607741 --- /dev/null +++ b/drivers/tty/serial/samsung_tty.c @@ -0,0 +1,2595 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver core for Samsung SoC onboard UARTs. + * + * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ +*/ + +/* Hote on 2410 error handling + * + * The s3c2410 manual has a love/hate affair with the contents of the + * UERSTAT register in the UART blocks, and keeps marking some of the + * error bits as reserved. Having checked with the s3c2410x01, + * it copes with BREAKs properly, so I am happy to ignore the RESERVED + * feature from the latter versions of the manual. + * + * If it becomes aparrent that latter versions of the 2410 remove these + * bits, then action will have to be taken to differentiate the versions + * and change the policy on BREAK + * + * BJD, 04-Nov-2004 +*/ + +#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include <linux/dmaengine.h> +#include <linux/dma-mapping.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/ioport.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/sysrq.h> +#include <linux/console.h> +#include <linux/tty.h> +#include <linux/tty_flip.h> +#include <linux/serial_core.h> +#include <linux/serial.h> +#include <linux/serial_s3c.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/cpufreq.h> +#include <linux/of.h> + +#include <asm/irq.h> + +#include "samsung.h" + +#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \ + !defined(MODULE) + +extern void printascii(const char *); + +__printf(1, 2) +static void dbg(const char *fmt, ...) +{ + va_list va; + char buff[256]; + + va_start(va, fmt); + vscnprintf(buff, sizeof(buff), fmt, va); + va_end(va); + + printascii(buff); +} + +#else +#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0) +#endif + +/* UART name and device definitions */ + +#define S3C24XX_SERIAL_NAME "ttySAC" +#define S3C24XX_SERIAL_MAJOR 204 +#define S3C24XX_SERIAL_MINOR 64 + +#define S3C24XX_TX_PIO 1 +#define S3C24XX_TX_DMA 2 +#define S3C24XX_RX_PIO 1 +#define S3C24XX_RX_DMA 2 +/* macros to change one thing to another */ + +#define tx_enabled(port) ((port)->unused[0]) +#define rx_enabled(port) ((port)->unused[1]) + +/* flag to ignore all characters coming in */ +#define RXSTAT_DUMMY_READ (0x10000000) + +static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) +{ + return container_of(port, struct s3c24xx_uart_port, port); +} + +/* translate a port to the device name */ + +static inline const char *s3c24xx_serial_portname(struct uart_port *port) +{ + return to_platform_device(port->dev)->name; +} + +static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) +{ + return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; +} + +/* + * s3c64xx and later SoC's include the interrupt mask and status registers in + * the controller itself, unlike the s3c24xx SoC's which have these registers + * in the interrupt controller. Check if the port type is s3c64xx or higher. + */ +static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port) +{ + return to_ourport(port)->info->type == PORT_S3C6400; +} + +static void s3c24xx_serial_rx_enable(struct uart_port *port) +{ + unsigned long flags; + unsigned int ucon, ufcon; + int count = 10000; + + spin_lock_irqsave(&port->lock, flags); + + while (--count && !s3c24xx_serial_txempty_nofifo(port)) + udelay(100); + + ufcon = rd_regl(port, S3C2410_UFCON); + ufcon |= S3C2410_UFCON_RESETRX; + wr_regl(port, S3C2410_UFCON, ufcon); + + ucon = rd_regl(port, S3C2410_UCON); + ucon |= S3C2410_UCON_RXIRQMODE; + wr_regl(port, S3C2410_UCON, ucon); + + rx_enabled(port) = 1; + spin_unlock_irqrestore(&port->lock, flags); +} + +static void s3c24xx_serial_rx_disable(struct uart_port *port) +{ + unsigned long flags; + unsigned int ucon; + + spin_lock_irqsave(&port->lock, flags); + + ucon = rd_regl(port, S3C2410_UCON); + ucon &= ~S3C2410_UCON_RXIRQMODE; + wr_regl(port, S3C2410_UCON, ucon); + + rx_enabled(port) = 0; + spin_unlock_irqrestore(&port->lock, flags); +} + +static void s3c24xx_serial_stop_tx(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + struct s3c24xx_uart_dma *dma = ourport->dma; + struct circ_buf *xmit = &port->state->xmit; + struct dma_tx_state state; + int count; + + if (!tx_enabled(port)) + return; + + if (s3c24xx_serial_has_interrupt_mask(port)) + s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); + else + disable_irq_nosync(ourport->tx_irq); + + if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) { + dmaengine_pause(dma->tx_chan); + dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); + dmaengine_terminate_all(dma->tx_chan); + dma_sync_single_for_cpu(ourport->port.dev, + dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE); + async_tx_ack(dma->tx_desc); + count = dma->tx_bytes_requested - state.residue; + xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); + port->icount.tx += count; + } + + tx_enabled(port) = 0; + ourport->tx_in_progress = 0; + + if (port->flags & UPF_CONS_FLOW) + s3c24xx_serial_rx_enable(port); + + ourport->tx_mode = 0; +} + +static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport); + +static void s3c24xx_serial_tx_dma_complete(void *args) +{ + struct s3c24xx_uart_port *ourport = args; + struct uart_port *port = &ourport->port; + struct circ_buf *xmit = &port->state->xmit; + struct s3c24xx_uart_dma *dma = ourport->dma; + struct dma_tx_state state; + unsigned long flags; + int count; + + + dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); + count = dma->tx_bytes_requested - state.residue; + async_tx_ack(dma->tx_desc); + + dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr, + dma->tx_size, DMA_TO_DEVICE); + + spin_lock_irqsave(&port->lock, flags); + + xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); + port->icount.tx += count; + ourport->tx_in_progress = 0; + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); + + s3c24xx_serial_start_next_tx(ourport); + spin_unlock_irqrestore(&port->lock, flags); +} + +static void enable_tx_dma(struct s3c24xx_uart_port *ourport) +{ + struct uart_port *port = &ourport->port; + u32 ucon; + + /* Mask Tx interrupt */ + if (s3c24xx_serial_has_interrupt_mask(port)) + s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); + else + disable_irq_nosync(ourport->tx_irq); + + /* Enable tx dma mode */ + ucon = rd_regl(port, S3C2410_UCON); + ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK); + ucon |= (dma_get_cache_alignment() >= 16) ? + S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1; + ucon |= S3C64XX_UCON_TXMODE_DMA; + wr_regl(port, S3C2410_UCON, ucon); + + ourport->tx_mode = S3C24XX_TX_DMA; +} + +static void enable_tx_pio(struct s3c24xx_uart_port *ourport) +{ + struct uart_port *port = &ourport->port; + u32 ucon, ufcon; + + /* Set ufcon txtrig */ + ourport->tx_in_progress = S3C24XX_TX_PIO; + ufcon = rd_regl(port, S3C2410_UFCON); + wr_regl(port, S3C2410_UFCON, ufcon); + + /* Enable tx pio mode */ + ucon = rd_regl(port, S3C2410_UCON); + ucon &= ~(S3C64XX_UCON_TXMODE_MASK); + ucon |= S3C64XX_UCON_TXMODE_CPU; + wr_regl(port, S3C2410_UCON, ucon); + + /* Unmask Tx interrupt */ + if (s3c24xx_serial_has_interrupt_mask(port)) + s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD, + S3C64XX_UINTM); + else + enable_irq(ourport->tx_irq); + + ourport->tx_mode = S3C24XX_TX_PIO; +} + +static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport) +{ + if (ourport->tx_mode != S3C24XX_TX_PIO) + enable_tx_pio(ourport); +} + +static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport, + unsigned int count) +{ + struct uart_port *port = &ourport->port; + struct circ_buf *xmit = &port->state->xmit; + struct s3c24xx_uart_dma *dma = ourport->dma; + + + if (ourport->tx_mode != S3C24XX_TX_DMA) + enable_tx_dma(ourport); + + dma->tx_size = count & ~(dma_get_cache_alignment() - 1); + dma->tx_transfer_addr = dma->tx_addr + xmit->tail; + + dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr, + dma->tx_size, DMA_TO_DEVICE); + + dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan, + dma->tx_transfer_addr, dma->tx_size, + DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); + if (!dma->tx_desc) { + dev_err(ourport->port.dev, "Unable to get desc for Tx\n"); + return -EIO; + } + + dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete; + dma->tx_desc->callback_param = ourport; + dma->tx_bytes_requested = dma->tx_size; + + ourport->tx_in_progress = S3C24XX_TX_DMA; + dma->tx_cookie = dmaengine_submit(dma->tx_desc); + dma_async_issue_pending(dma->tx_chan); + return 0; +} + +static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport) +{ + struct uart_port *port = &ourport->port; + struct circ_buf *xmit = &port->state->xmit; + unsigned long count; + + /* Get data size up to the end of buffer */ + count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); + + if (!count) { + s3c24xx_serial_stop_tx(port); + return; + } + + if (!ourport->dma || !ourport->dma->tx_chan || + count < ourport->min_dma_size || + xmit->tail & (dma_get_cache_alignment() - 1)) + s3c24xx_serial_start_tx_pio(ourport); + else + s3c24xx_serial_start_tx_dma(ourport, count); +} + +static void s3c24xx_serial_start_tx(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + struct circ_buf *xmit = &port->state->xmit; + + if (!tx_enabled(port)) { + if (port->flags & UPF_CONS_FLOW) + s3c24xx_serial_rx_disable(port); + + tx_enabled(port) = 1; + if (!ourport->dma || !ourport->dma->tx_chan) + s3c24xx_serial_start_tx_pio(ourport); + } + + if (ourport->dma && ourport->dma->tx_chan) { + if (!uart_circ_empty(xmit) && !ourport->tx_in_progress) + s3c24xx_serial_start_next_tx(ourport); + } +} + +static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport, + struct tty_port *tty, int count) +{ + struct s3c24xx_uart_dma *dma = ourport->dma; + int copied; + + if (!count) + return; + + dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr, + dma->rx_size, DMA_FROM_DEVICE); + + ourport->port.icount.rx += count; + if (!tty) { + dev_err(ourport->port.dev, "No tty port\n"); + return; + } + copied = tty_insert_flip_string(tty, + ((unsigned char *)(ourport->dma->rx_buf)), count); + if (copied != count) { + WARN_ON(1); + dev_err(ourport->port.dev, "RxData copy to tty layer failed\n"); + } +} + +static void s3c24xx_serial_stop_rx(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + struct s3c24xx_uart_dma *dma = ourport->dma; + struct tty_port *t = &port->state->port; + struct dma_tx_state state; + enum dma_status dma_status; + unsigned int received; + + if (rx_enabled(port)) { + dbg("s3c24xx_serial_stop_rx: port=%p\n", port); + if (s3c24xx_serial_has_interrupt_mask(port)) + s3c24xx_set_bit(port, S3C64XX_UINTM_RXD, + S3C64XX_UINTM); + else + disable_irq_nosync(ourport->rx_irq); + rx_enabled(port) = 0; + } + if (dma && dma->rx_chan) { + dmaengine_pause(dma->tx_chan); + dma_status = dmaengine_tx_status(dma->rx_chan, + dma->rx_cookie, &state); + if (dma_status == DMA_IN_PROGRESS || + dma_status == DMA_PAUSED) { + received = dma->rx_bytes_requested - state.residue; + dmaengine_terminate_all(dma->rx_chan); + s3c24xx_uart_copy_rx_to_tty(ourport, t, received); + } + } +} + +static inline struct s3c24xx_uart_info + *s3c24xx_port_to_info(struct uart_port *port) +{ + return to_ourport(port)->info; +} + +static inline struct s3c2410_uartcfg + *s3c24xx_port_to_cfg(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport; + + if (port->dev == NULL) + return NULL; + + ourport = container_of(port, struct s3c24xx_uart_port, port); + return ourport->cfg; +} + +static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, + unsigned long ufstat) +{ + struct s3c24xx_uart_info *info = ourport->info; + + if (ufstat & info->rx_fifofull) + return ourport->port.fifosize; + + return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; +} + +static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport); +static void s3c24xx_serial_rx_dma_complete(void *args) +{ + struct s3c24xx_uart_port *ourport = args; + struct uart_port *port = &ourport->port; + + struct s3c24xx_uart_dma *dma = ourport->dma; + struct tty_port *t = &port->state->port; + struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); + + struct dma_tx_state state; + unsigned long flags; + int received; + + dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); + received = dma->rx_bytes_requested - state.residue; + async_tx_ack(dma->rx_desc); + + spin_lock_irqsave(&port->lock, flags); + + if (received) + s3c24xx_uart_copy_rx_to_tty(ourport, t, received); + + if (tty) { + tty_flip_buffer_push(t); + tty_kref_put(tty); + } + + s3c64xx_start_rx_dma(ourport); + + spin_unlock_irqrestore(&port->lock, flags); +} + +static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport) +{ + struct s3c24xx_uart_dma *dma = ourport->dma; + + dma_sync_single_for_device(ourport->port.dev, dma->rx_addr, + dma->rx_size, DMA_FROM_DEVICE); + + dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan, + dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT); + if (!dma->rx_desc) { + dev_err(ourport->port.dev, "Unable to get desc for Rx\n"); + return; + } + + dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete; + dma->rx_desc->callback_param = ourport; + dma->rx_bytes_requested = dma->rx_size; + + dma->rx_cookie = dmaengine_submit(dma->rx_desc); + dma_async_issue_pending(dma->rx_chan); +} + +/* ? - where has parity gone?? */ +#define S3C2410_UERSTAT_PARITY (0x1000) + +static void enable_rx_dma(struct s3c24xx_uart_port *ourport) +{ + struct uart_port *port = &ourport->port; + unsigned int ucon; + + /* set Rx mode to DMA mode */ + ucon = rd_regl(port, S3C2410_UCON); + ucon &= ~(S3C64XX_UCON_RXBURST_MASK | + S3C64XX_UCON_TIMEOUT_MASK | + S3C64XX_UCON_EMPTYINT_EN | + S3C64XX_UCON_DMASUS_EN | + S3C64XX_UCON_TIMEOUT_EN | + S3C64XX_UCON_RXMODE_MASK); + ucon |= S3C64XX_UCON_RXBURST_16 | + 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | + S3C64XX_UCON_EMPTYINT_EN | + S3C64XX_UCON_TIMEOUT_EN | + S3C64XX_UCON_RXMODE_DMA; + wr_regl(port, S3C2410_UCON, ucon); + + ourport->rx_mode = S3C24XX_RX_DMA; +} + +static void enable_rx_pio(struct s3c24xx_uart_port *ourport) +{ + struct uart_port *port = &ourport->port; + unsigned int ucon; + + /* set Rx mode to DMA mode */ + ucon = rd_regl(port, S3C2410_UCON); + ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK | + S3C64XX_UCON_EMPTYINT_EN | + S3C64XX_UCON_DMASUS_EN | + S3C64XX_UCON_TIMEOUT_EN | + S3C64XX_UCON_RXMODE_MASK); + ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | + S3C64XX_UCON_TIMEOUT_EN | + S3C64XX_UCON_RXMODE_CPU; + wr_regl(port, S3C2410_UCON, ucon); + + ourport->rx_mode = S3C24XX_RX_PIO; +} + +static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport); + +static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id) +{ + unsigned int utrstat, ufstat, received; + struct s3c24xx_uart_port *ourport = dev_id; + struct uart_port *port = &ourport->port; + struct s3c24xx_uart_dma *dma = ourport->dma; + struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); + struct tty_port *t = &port->state->port; + unsigned long flags; + struct dma_tx_state state; + + utrstat = rd_regl(port, S3C2410_UTRSTAT); + ufstat = rd_regl(port, S3C2410_UFSTAT); + + spin_lock_irqsave(&port->lock, flags); + + if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) { + s3c64xx_start_rx_dma(ourport); + if (ourport->rx_mode == S3C24XX_RX_PIO) + enable_rx_dma(ourport); + goto finish; + } + + if (ourport->rx_mode == S3C24XX_RX_DMA) { + dmaengine_pause(dma->rx_chan); + dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); + dmaengine_terminate_all(dma->rx_chan); + received = dma->rx_bytes_requested - state.residue; + s3c24xx_uart_copy_rx_to_tty(ourport, t, received); + + enable_rx_pio(ourport); + } + + s3c24xx_serial_rx_drain_fifo(ourport); + + if (tty) { + tty_flip_buffer_push(t); + tty_kref_put(tty); + } + + wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); + +finish: + spin_unlock_irqrestore(&port->lock, flags); + + return IRQ_HANDLED; +} + +static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) +{ + struct uart_port *port = &ourport->port; + unsigned int ufcon, ch, flag, ufstat, uerstat; + unsigned int fifocnt = 0; + int max_count = port->fifosize; + + while (max_count-- > 0) { + /* + * Receive all characters known to be in FIFO + * before reading FIFO level again + */ + if (fifocnt == 0) { + ufstat = rd_regl(port, S3C2410_UFSTAT); + fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat); + if (fifocnt == 0) + break; + } + fifocnt--; + + uerstat = rd_regl(port, S3C2410_UERSTAT); + ch = rd_regb(port, S3C2410_URXH); + + if (port->flags & UPF_CONS_FLOW) { + int txe = s3c24xx_serial_txempty_nofifo(port); + + if (rx_enabled(port)) { + if (!txe) { + rx_enabled(port) = 0; + continue; + } + } else { + if (txe) { + ufcon = rd_regl(port, S3C2410_UFCON); + ufcon |= S3C2410_UFCON_RESETRX; + wr_regl(port, S3C2410_UFCON, ufcon); + rx_enabled(port) = 1; + return; + } + continue; + } + } + + /* insert the character into the buffer */ + + flag = TTY_NORMAL; + port->icount.rx++; + + if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { + dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n", + ch, uerstat); + + /* check for break */ + if (uerstat & S3C2410_UERSTAT_BREAK) { + dbg("break!\n"); + port->icount.brk++; + if (uart_handle_break(port)) + continue; /* Ignore character */ + } + + if (uerstat & S3C2410_UERSTAT_FRAME) + port->icount.frame++; + if (uerstat & S3C2410_UERSTAT_OVERRUN) + port->icount.overrun++; + + uerstat &= port->read_status_mask; + + if (uerstat & S3C2410_UERSTAT_BREAK) + flag = TTY_BREAK; + else if (uerstat & S3C2410_UERSTAT_PARITY) + flag = TTY_PARITY; + else if (uerstat & (S3C2410_UERSTAT_FRAME | + S3C2410_UERSTAT_OVERRUN)) + flag = TTY_FRAME; + } + + if (uart_handle_sysrq_char(port, ch)) + continue; /* Ignore character */ + + uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, + ch, flag); + } + + tty_flip_buffer_push(&port->state->port); +} + +static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id) +{ + struct s3c24xx_uart_port *ourport = dev_id; + struct uart_port *port = &ourport->port; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + s3c24xx_serial_rx_drain_fifo(ourport); + spin_unlock_irqrestore(&port->lock, flags); + + return IRQ_HANDLED; +} + + +static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id) +{ + struct s3c24xx_uart_port *ourport = dev_id; + + if (ourport->dma && ourport->dma->rx_chan) + return s3c24xx_serial_rx_chars_dma(dev_id); + return s3c24xx_serial_rx_chars_pio(dev_id); +} + +static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) +{ + struct s3c24xx_uart_port *ourport = id; + struct uart_port *port = &ourport->port; + struct circ_buf *xmit = &port->state->xmit; + unsigned long flags; + int count, dma_count = 0; + + spin_lock_irqsave(&port->lock, flags); + + count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); + + if (ourport->dma && ourport->dma->tx_chan && + count >= ourport->min_dma_size) { + int align = dma_get_cache_alignment() - + (xmit->tail & (dma_get_cache_alignment() - 1)); + if (count-align >= ourport->min_dma_size) { + dma_count = count-align; + count = align; + } + } + + if (port->x_char) { + wr_regb(port, S3C2410_UTXH, port->x_char); + port->icount.tx++; + port->x_char = 0; + goto out; + } + + /* if there isn't anything more to transmit, or the uart is now + * stopped, disable the uart and exit + */ + + if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { + s3c24xx_serial_stop_tx(port); + goto out; + } + + /* try and drain the buffer... */ + + if (count > port->fifosize) { + count = port->fifosize; + dma_count = 0; + } + + while (!uart_circ_empty(xmit) && count > 0) { + if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) + break; + + wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + count--; + } + + if (!count && dma_count) { + s3c24xx_serial_start_tx_dma(ourport, dma_count); + goto out; + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { + spin_unlock(&port->lock); + uart_write_wakeup(port); + spin_lock(&port->lock); + } + + if (uart_circ_empty(xmit)) + s3c24xx_serial_stop_tx(port); + +out: + spin_unlock_irqrestore(&port->lock, flags); + return IRQ_HANDLED; +} + +/* interrupt handler for s3c64xx and later SoC's.*/ +static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) +{ + struct s3c24xx_uart_port *ourport = id; + struct uart_port *port = &ourport->port; + unsigned int pend = rd_regl(port, S3C64XX_UINTP); + irqreturn_t ret = IRQ_HANDLED; + + if (pend & S3C64XX_UINTM_RXD_MSK) { + ret = s3c24xx_serial_rx_chars(irq, id); + wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); + } + if (pend & S3C64XX_UINTM_TXD_MSK) { + ret = s3c24xx_serial_tx_chars(irq, id); + wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); + } + return ret; +} + +static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) +{ + struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); + unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); + unsigned long ufcon = rd_regl(port, S3C2410_UFCON); + + if (ufcon & S3C2410_UFCON_FIFOMODE) { + if ((ufstat & info->tx_fifomask) != 0 || + (ufstat & info->tx_fifofull)) + return 0; + + return 1; + } + + return s3c24xx_serial_txempty_nofifo(port); +} + +/* no modem control lines */ +static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) +{ + unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); + + if (umstat & S3C2410_UMSTAT_CTS) + return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; + else + return TIOCM_CAR | TIOCM_DSR; +} + +static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + unsigned int umcon = rd_regl(port, S3C2410_UMCON); + + if (mctrl & TIOCM_RTS) + umcon |= S3C2410_UMCOM_RTS_LOW; + else + umcon &= ~S3C2410_UMCOM_RTS_LOW; + + wr_regl(port, S3C2410_UMCON, umcon); +} + +static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) +{ + unsigned long flags; + unsigned int ucon; + + spin_lock_irqsave(&port->lock, flags); + + ucon = rd_regl(port, S3C2410_UCON); + + if (break_state) + ucon |= S3C2410_UCON_SBREAK; + else + ucon &= ~S3C2410_UCON_SBREAK; + + wr_regl(port, S3C2410_UCON, ucon); + + spin_unlock_irqrestore(&port->lock, flags); +} + +static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) +{ + struct s3c24xx_uart_dma *dma = p->dma; + struct dma_slave_caps dma_caps; + const char *reason = NULL; + int ret; + + /* Default slave configuration parameters */ + dma->rx_conf.direction = DMA_DEV_TO_MEM; + dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; + dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH; + dma->rx_conf.src_maxburst = 1; + + dma->tx_conf.direction = DMA_MEM_TO_DEV; + dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; + dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH; + dma->tx_conf.dst_maxburst = 1; + + dma->rx_chan = dma_request_chan(p->port.dev, "rx"); + + if (IS_ERR(dma->rx_chan)) { + reason = "DMA RX channel request failed"; + ret = PTR_ERR(dma->rx_chan); + goto err_warn; + } + + ret = dma_get_slave_caps(dma->rx_chan, &dma_caps); + if (ret < 0 || + dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { + reason = "insufficient DMA RX engine capabilities"; + ret = -EOPNOTSUPP; + goto err_release_rx; + } + + dmaengine_slave_config(dma->rx_chan, &dma->rx_conf); + + dma->tx_chan = dma_request_chan(p->port.dev, "tx"); + if (IS_ERR(dma->tx_chan)) { + reason = "DMA TX channel request failed"; + ret = PTR_ERR(dma->tx_chan); + goto err_release_rx; + } + + ret = dma_get_slave_caps(dma->tx_chan, &dma_caps); + if (ret < 0 || + dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { + reason = "insufficient DMA TX engine capabilities"; + ret = -EOPNOTSUPP; + goto err_release_tx; + } + + dmaengine_slave_config(dma->tx_chan, &dma->tx_conf); + + /* RX buffer */ + dma->rx_size = PAGE_SIZE; + + dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL); + if (!dma->rx_buf) { + ret = -ENOMEM; + goto err_release_tx; + } + + dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf, + dma->rx_size, DMA_FROM_DEVICE); + if (dma_mapping_error(p->port.dev, dma->rx_addr)) { + reason = "DMA mapping error for RX buffer"; + ret = -EIO; + goto err_free_rx; + } + + /* TX buffer */ + dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf, + UART_XMIT_SIZE, DMA_TO_DEVICE); + if (dma_mapping_error(p->port.dev, dma->tx_addr)) { + reason = "DMA mapping error for TX buffer"; + ret = -EIO; + goto err_unmap_rx; + } + + return 0; + +err_unmap_rx: + dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size, + DMA_FROM_DEVICE); +err_free_rx: + kfree(dma->rx_buf); +err_release_tx: + dma_release_channel(dma->tx_chan); +err_release_rx: + dma_release_channel(dma->rx_chan); +err_warn: + if (reason) + dev_warn(p->port.dev, "%s, DMA will not be used\n", reason); + return ret; +} + +static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p) +{ + struct s3c24xx_uart_dma *dma = p->dma; + + if (dma->rx_chan) { + dmaengine_terminate_all(dma->rx_chan); + dma_unmap_single(p->port.dev, dma->rx_addr, + dma->rx_size, DMA_FROM_DEVICE); + kfree(dma->rx_buf); + dma_release_channel(dma->rx_chan); + dma->rx_chan = NULL; + } + + if (dma->tx_chan) { + dmaengine_terminate_all(dma->tx_chan); + dma_unmap_single(p->port.dev, dma->tx_addr, + UART_XMIT_SIZE, DMA_TO_DEVICE); + dma_release_channel(dma->tx_chan); + dma->tx_chan = NULL; + } +} + +static void s3c24xx_serial_shutdown(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + + if (ourport->tx_claimed) { + if (!s3c24xx_serial_has_interrupt_mask(port)) + free_irq(ourport->tx_irq, ourport); + tx_enabled(port) = 0; + ourport->tx_claimed = 0; + ourport->tx_mode = 0; + } + + if (ourport->rx_claimed) { + if (!s3c24xx_serial_has_interrupt_mask(port)) + free_irq(ourport->rx_irq, ourport); + ourport->rx_claimed = 0; + rx_enabled(port) = 0; + } + + /* Clear pending interrupts and mask all interrupts */ + if (s3c24xx_serial_has_interrupt_mask(port)) { + free_irq(port->irq, ourport); + + wr_regl(port, S3C64XX_UINTP, 0xf); + wr_regl(port, S3C64XX_UINTM, 0xf); + } + + if (ourport->dma) + s3c24xx_serial_release_dma(ourport); + + ourport->tx_in_progress = 0; +} + +static int s3c24xx_serial_startup(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + int ret; + + dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n", + port, (unsigned long long)port->mapbase, port->membase); + + rx_enabled(port) = 1; + + ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0, + s3c24xx_serial_portname(port), ourport); + + if (ret != 0) { + dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq); + return ret; + } + + ourport->rx_claimed = 1; + + dbg("requesting tx irq...\n"); + + tx_enabled(port) = 1; + + ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0, + s3c24xx_serial_portname(port), ourport); + + if (ret) { + dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq); + goto err; + } + + ourport->tx_claimed = 1; + + dbg("s3c24xx_serial_startup ok\n"); + + /* the port reset code should have done the correct + * register setup for the port controls */ + + return ret; + +err: + s3c24xx_serial_shutdown(port); + return ret; +} + +static int s3c64xx_serial_startup(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + unsigned long flags; + unsigned int ufcon; + int ret; + + dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n", + port, (unsigned long long)port->mapbase, port->membase); + + wr_regl(port, S3C64XX_UINTM, 0xf); + if (ourport->dma) { + ret = s3c24xx_serial_request_dma(ourport); + if (ret < 0) { + devm_kfree(port->dev, ourport->dma); + ourport->dma = NULL; + } + } + + ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, + s3c24xx_serial_portname(port), ourport); + if (ret) { + dev_err(port->dev, "cannot get irq %d\n", port->irq); + return ret; + } + + /* For compatibility with s3c24xx Soc's */ + rx_enabled(port) = 1; + ourport->rx_claimed = 1; + tx_enabled(port) = 0; + ourport->tx_claimed = 1; + + spin_lock_irqsave(&port->lock, flags); + + ufcon = rd_regl(port, S3C2410_UFCON); + ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; + if (!uart_console(port)) + ufcon |= S3C2410_UFCON_RESETTX; + wr_regl(port, S3C2410_UFCON, ufcon); + + enable_rx_pio(ourport); + + spin_unlock_irqrestore(&port->lock, flags); + + /* Enable Rx Interrupt */ + s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM); + + dbg("s3c64xx_serial_startup ok\n"); + return ret; +} + +/* power power management control */ + +static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, + unsigned int old) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + int timeout = 10000; + + ourport->pm_level = level; + + switch (level) { + case 3: + while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) + udelay(100); + + if (!IS_ERR(ourport->baudclk)) + clk_disable_unprepare(ourport->baudclk); + + clk_disable_unprepare(ourport->clk); + break; + + case 0: + clk_prepare_enable(ourport->clk); + + if (!IS_ERR(ourport->baudclk)) + clk_prepare_enable(ourport->baudclk); + + break; + default: + dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); + } +} + +/* baud rate calculation + * + * The UARTs on the S3C2410/S3C2440 can take their clocks from a number + * of different sources, including the peripheral clock ("pclk") and an + * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") + * with a programmable extra divisor. + * + * The following code goes through the clock sources, and calculates the + * baud clocks (and the resultant actual baud rates) and then tries to + * pick the closest one and select that. + * +*/ + +#define MAX_CLK_NAME_LENGTH 15 + +static inline int s3c24xx_serial_getsource(struct uart_port * |