diff options
| author | Arushi Singhal <arushisinghal19971997@gmail.com> | 2017-03-29 11:13:20 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-05-29 16:39:52 -0400 |
| commit | f42292040d31922ee4e4ea68e2f287fbc3bb2053 (patch) | |
| tree | 2c2593bc2281a2db741eb681d27f3ada4cdfbaf8 /drivers/staging | |
| parent | 6995a659101bd4effa41cebb067f9dc18d77520d (diff) | |
media: staging: media: davinci_vpfe: Replace a bit shift
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
[mchehab+samsung@kernel.org: rebase on the top of upstream]
Signed-off-by: Arushi Singhal <arushisinghal19971997@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'drivers/staging')
| -rw-r--r-- | drivers/staging/media/davinci_vpfe/dm365_isif.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/staging/media/davinci_vpfe/dm365_isif.c b/drivers/staging/media/davinci_vpfe/dm365_isif.c index 46fd8184fc77..05a997f7aa5d 100644 --- a/drivers/staging/media/davinci_vpfe/dm365_isif.c +++ b/drivers/staging/media/davinci_vpfe/dm365_isif.c @@ -816,7 +816,7 @@ isif_config_dfc(struct vpfe_isif_device *isif, struct vpfe_isif_dfc *vdfc) /* Correct whole line or partial */ if (vdfc->corr_whole_line) - val |= 1 << ISIF_VDFC_CORR_WHOLE_LN_SHIFT; + val |= BIT(ISIF_VDFC_CORR_WHOLE_LN_SHIFT); /* level shift value */ val |= (vdfc->def_level_shift & ISIF_VDFC_LEVEL_SHFT_MASK) << @@ -844,7 +844,7 @@ isif_config_dfc(struct vpfe_isif_device *isif, struct vpfe_isif_dfc *vdfc) val = isif_read(isif->isif_cfg.base_addr, DFCMEMCTL); /* set DFCMARST and set DFCMWR */ - val |= 1 << ISIF_DFCMEMCTL_DFCMARST_SHIFT; + val |= BIT(ISIF_DFCMEMCTL_DFCMARST_SHIFT); val |= 1; isif_write(isif->isif_cfg.base_addr, val, DFCMEMCTL); @@ -875,7 +875,7 @@ isif_config_dfc(struct vpfe_isif_device *isif, struct vpfe_isif_dfc *vdfc) } val = isif_read(isif->isif_cfg.base_addr, DFCMEMCTL); /* clear DFCMARST and set DFCMWR */ - val &= ~(1 << ISIF_DFCMEMCTL_DFCMARST_SHIFT); + val &= ~BIT(ISIF_DFCMEMCTL_DFCMARST_SHIFT); val |= 1; isif_write(isif->isif_cfg.base_addr, val, DFCMEMCTL); @@ -1135,7 +1135,7 @@ static int isif_config_raw(struct v4l2_subdev *sd, int mode) isif_write(isif->isif_cfg.base_addr, val, CGAMMAWD); /* Configure DPCM compression settings */ if (params->v4l2_pix_fmt == V4L2_PIX_FMT_SGRBG10DPCM8) { - val = 1 << ISIF_DPCM_EN_SHIFT; + val = BIT(ISIF_DPCM_EN_SHIFT); val |= (params->dpcm_predictor & ISIF_DPCM_PREDICTOR_MASK) << ISIF_DPCM_PREDICTOR_SHIFT; } |