diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-10-26 15:39:02 +0200 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-10-26 15:39:02 +0200 |
commit | aa77677e0a288e08073620db5d2a31df83ca4788 (patch) | |
tree | 0d14b995a21c43f365d66b9ad101a334109fc4e4 /drivers/staging/et131x | |
parent | efb8d21b2c6db3497655cc6a033ae8a9883e4063 (diff) | |
parent | 43a3beb6da994549ec28a9f31727b997a025f958 (diff) |
Merge branch 'staging-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
* 'staging-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (1519 commits)
staging: et131x: Remove redundant check and return statement
staging: et131x: Mainly whitespace changes to appease checkpatch
staging: et131x: Remove last of the forward declarations
staging: et131x: Remove even more forward declarations
staging: et131x: Remove yet more forward declarations
staging: et131x: Remove more forward declarations
staging: et131x: Remove forward declaration of et131x_adapter_setup
staging: et131x: Remove some forward declarations
staging: et131x: Remove unused rx_ring.recv_packet_pool
staging: et131x: Remove call to find pci pm capability
staging: et131x: Remove redundant et131x_reset_recv() call
staging: et131x: Remove unused rx_ring.recv_buffer_pool
Staging: bcm: Fix three initialization errors in InterfaceDld.c
Staging: bcm: Fix coding style issues in InterfaceDld.c
staging:iio:dac: Add AD5360 driver
staging:iio:trigger:bfin-timer: Fix compile error
Staging: vt6655: add some range checks before memcpy()
Staging: vt6655: whitespace fixes to iotcl.c
Staging: vt6656: add some range checks before memcpy()
Staging: vt6656: whitespace cleanups in ioctl.c
...
Fix up conflicts in:
- drivers/{Kconfig,Makefile}, drivers/staging/{Kconfig,Makefile}:
vg driver movement
- drivers/staging/brcm80211/brcmfmac/{dhd_linux.c,mac80211_if.c}:
driver removal vs now stale changes
- drivers/staging/rtl8192e/r8192E_core.c:
driver removal vs now stale changes
- drivers/staging/et131x/et131*:
driver consolidation into one file, tried to do fixups
Diffstat (limited to 'drivers/staging/et131x')
21 files changed, 7134 insertions, 9046 deletions
diff --git a/drivers/staging/et131x/Kconfig b/drivers/staging/et131x/Kconfig index e11cf340856a..f0ed08d6a977 100644 --- a/drivers/staging/et131x/Kconfig +++ b/drivers/staging/et131x/Kconfig @@ -7,12 +7,3 @@ config ET131X To compile this driver as a module, choose M here. The module will be called et131x. - -config ET131X_DEBUG - bool "Enable et131x debugging" - depends on ET131X - default n - ---help--- - Say Y for detailed debug information. - - If in doubt, say N. diff --git a/drivers/staging/et131x/Makefile b/drivers/staging/et131x/Makefile index dfcd2bfcb94e..027ff9453fe1 100644 --- a/drivers/staging/et131x/Makefile +++ b/drivers/staging/et131x/Makefile @@ -3,13 +3,3 @@ # obj-$(CONFIG_ET131X) += et131x.o - -et131x-y := et1310_eeprom.o \ - et1310_mac.o \ - et1310_phy.o \ - et1310_pm.o \ - et1310_rx.o \ - et1310_tx.o \ - et131x_initpci.o \ - et131x_isr.o \ - et131x_netdev.o diff --git a/drivers/staging/et131x/README b/drivers/staging/et131x/README index 28752a502312..3458aa713a33 100644 --- a/drivers/staging/et131x/README +++ b/drivers/staging/et131x/README @@ -2,24 +2,15 @@ This is a driver for the ET1310 network device. Based on the driver found at https://sourceforge.net/projects/et131x/ -Cleaned up immensely by Olaf Hartman <o.hartmann@telovital.com> and Christoph -Hellwig <hch@infradead.org> +Cleaned up immensely by Olaf Hartman and Christoph Hellwig <hch@infradead.org> Note, the powermanagement options were removed from the vendor provided driver as they did not build properly at the time. TODO: - - kernel coding style cleanups - - forward port for latest network driver changes - - kill useless typecasts (e.g. in et1310_phy.c) - - alloc_etherdev is initializing memory with zero?!? - - add_timer call in et131x_netdev.c is correct? - - Add power saving functionality (suspend, sleep, resume) - - Implement a few more kernel Parameter (set mac ) + - Use of kmem_cache seems a bit unusual Please send patches to: Greg Kroah-Hartman <gregkh@suse.de> - -And Cc: Olaf Hartmann <o.hartmann@telovital.com> as he has this device and can -test any changes. + Mark Einon <mark.einon@gmail.com> diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h deleted file mode 100644 index 410677ee22b7..000000000000 --- a/drivers/staging/et131x/et1310_address_map.h +++ /dev/null @@ -1,1434 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et1310_address_map.h - Contains the register mapping for the ET1310 - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef _ET1310_ADDRESS_MAP_H_ -#define _ET1310_ADDRESS_MAP_H_ - - -/* START OF GLOBAL REGISTER ADDRESS MAP */ - -/* - * 10bit registers - * - * Tx queue start address reg in global address map at address 0x0000 - * tx queue end address reg in global address map at address 0x0004 - * rx queue start address reg in global address map at address 0x0008 - * rx queue end address reg in global address map at address 0x000C - */ - -/* - * structure for power management control status reg in global address map - * located at address 0x0010 - * jagcore_rx_rdy bit 9 - * jagcore_tx_rdy bit 8 - * phy_lped_en bit 7 - * phy_sw_coma bit 6 - * rxclk_gate bit 5 - * txclk_gate bit 4 - * sysclk_gate bit 3 - * jagcore_rx_en bit 2 - * jagcore_tx_en bit 1 - * gigephy_en bit 0 - */ - -#define ET_PM_PHY_SW_COMA 0x40 -#define ET_PMCSR_INIT 0x38 - -/* - * Interrupt status reg at address 0x0018 - */ - -#define ET_INTR_TXDMA_ISR 0x00000008 -#define ET_INTR_TXDMA_ERR 0x00000010 -#define ET_INTR_RXDMA_XFR_DONE 0x00000020 -#define ET_INTR_RXDMA_FB_R0_LOW 0x00000040 -#define ET_INTR_RXDMA_FB_R1_LOW 0x00000080 -#define ET_INTR_RXDMA_STAT_LOW 0x00000100 -#define ET_INTR_RXDMA_ERR 0x00000200 -#define ET_INTR_WATCHDOG 0x00004000 -#define ET_INTR_WOL 0x00008000 -#define ET_INTR_PHY 0x00010000 -#define ET_INTR_TXMAC 0x00020000 -#define ET_INTR_RXMAC 0x00040000 -#define ET_INTR_MAC_STAT 0x00080000 -#define ET_INTR_SLV_TIMEOUT 0x00100000 - -/* - * Interrupt mask register at address 0x001C - * Interrupt alias clear mask reg at address 0x0020 - * Interrupt status alias reg at address 0x0024 - * - * Same masks as above - */ - -/* - * Software reset reg at address 0x0028 - * 0: txdma_sw_reset - * 1: rxdma_sw_reset - * 2: txmac_sw_reset - * 3: rxmac_sw_reset - * 4: mac_sw_reset - * 5: mac_stat_sw_reset - * 6: mmc_sw_reset - *31: selfclr_disable - */ - -/* - * SLV Timer reg at address 0x002C (low 24 bits) - */ - -/* - * MSI Configuration reg at address 0x0030 - */ - -#define ET_MSI_VECTOR 0x0000001F -#define ET_MSI_TC 0x00070000 - -/* - * Loopback reg located at address 0x0034 - */ - -#define ET_LOOP_MAC 0x00000001 -#define ET_LOOP_DMA 0x00000002 - -/* - * GLOBAL Module of JAGCore Address Mapping - * Located at address 0x0000 - */ -struct global_regs { /* Location: */ - u32 txq_start_addr; /* 0x0000 */ - u32 txq_end_addr; /* 0x0004 */ - u32 rxq_start_addr; /* 0x0008 */ - u32 rxq_end_addr; /* 0x000C */ - u32 pm_csr; /* 0x0010 */ - u32 unused; /* 0x0014 */ - u32 int_status; /* 0x0018 */ - u32 int_mask; /* 0x001C */ - u32 int_alias_clr_en; /* 0x0020 */ - u32 int_status_alias; /* 0x0024 */ - u32 sw_reset; /* 0x0028 */ - u32 slv_timer; /* 0x002C */ - u32 msi_config; /* 0x0030 */ - u32 loopback; /* 0x0034 */ - u32 watchdog_timer; /* 0x0038 */ -}; - - -/* START OF TXDMA REGISTER ADDRESS MAP */ - -/* - * txdma control status reg at address 0x1000 - */ - -#define ET_TXDMA_CSR_HALT 0x00000001 -#define ET_TXDMA_DROP_TLP 0x00000002 -#define ET_TXDMA_CACHE_THRS 0x000000F0 -#define ET_TXDMA_CACHE_SHIFT 4 -#define ET_TXDMA_SNGL_EPKT 0x00000100 -#define ET_TXDMA_CLASS 0x00001E00 - -/* - * structure for txdma packet ring base address hi reg in txdma address map - * located at address 0x1004 - * Defined earlier (u32) - */ - -/* - * structure for txdma packet ring base address low reg in txdma address map - * located at address 0x1008 - * Defined earlier (u32) - */ - -/* - * structure for txdma packet ring number of descriptor reg in txdma address - * map. Located at address 0x100C - * - * 31-10: unused - * 9-0: pr ndes - */ - -#define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */ -#define ET_DMA12_WRAP 0x1000 -#define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */ -#define ET_DMA10_WRAP 0x0400 -#define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */ -#define ET_DMA4_WRAP 0x0010 - -#define INDEX12(x) ((x) & ET_DMA12_MASK) -#define INDEX10(x) ((x) & ET_DMA10_MASK) -#define INDEX4(x) ((x) & ET_DMA4_MASK) - -extern inline void add_10bit(u32 *v, int n) -{ - *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP); -} - -extern inline void add_12bit(u32 *v, int n) -{ - *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP); -} - -/* - * 10bit DMA with wrap - * txdma tx queue write address reg in txdma address map at 0x1010 - * txdma tx queue write address external reg in txdma address map at 0x1014 - * txdma tx queue read address reg in txdma address map at 0x1018 - * - * u32 - * txdma status writeback address hi reg in txdma address map at0x101C - * txdma status writeback address lo reg in txdma address map at 0x1020 - * - * 10bit DMA with wrap - * txdma service request reg in txdma address map at 0x1024 - * structure for txdma service complete reg in txdma address map at 0x1028 - * - * 4bit DMA with wrap - * txdma tx descriptor cache read index reg in txdma address map at 0x102C - * txdma tx descriptor cache write index reg in txdma address map at 0x1030 - * - * txdma error reg in txdma address map at address 0x1034 - * 0: PyldResend - * 1: PyldRewind - * 4: DescrResend - * 5: DescrRewind - * 8: WrbkResend - * 9: WrbkRewind - */ - -/* - * Tx DMA Module of JAGCore Address Mapping - * Located at address 0x1000 - */ -struct txdma_regs { /* Location: */ - u32 csr; /* 0x1000 */ - u32 pr_base_hi; /* 0x1004 */ - u32 pr_base_lo; /* 0x1008 */ - u32 pr_num_des; /* 0x100C */ - u32 txq_wr_addr; /* 0x1010 */ - u32 txq_wr_addr_ext; /* 0x1014 */ - u32 txq_rd_addr; /* 0x1018 */ - u32 dma_wb_base_hi; /* 0x101C */ - u32 dma_wb_base_lo; /* 0x1020 */ - u32 service_request; /* 0x1024 */ - u32 service_complete; /* 0x1028 */ - u32 cache_rd_index; /* 0x102C */ - u32 cache_wr_index; /* 0x1030 */ - u32 tx_dma_error; /* 0x1034 */ - u32 desc_abort_cnt; /* 0x1038 */ - u32 payload_abort_cnt; /* 0x103c */ - u32 writeback_abort_cnt; /* 0x1040 */ - u32 desc_timeout_cnt; /* 0x1044 */ - u32 payload_timeout_cnt; /* 0x1048 */ - u32 writeback_timeout_cnt; /* 0x104c */ - u32 desc_error_cnt; /* 0x1050 */ - u32 payload_error_cnt; /* 0x1054 */ - u32 writeback_error_cnt; /* 0x1058 */ - u32 dropped_tlp_cnt; /* 0x105c */ - u32 new_service_complete; /* 0x1060 */ - u32 ethernet_packet_cnt; /* 0x1064 */ -}; - -/* END OF TXDMA REGISTER ADDRESS MAP */ - - -/* START OF RXDMA REGISTER ADDRESS MAP */ - -/* - * structure for control status reg in rxdma address map - * Located at address 0x2000 - * - * CSR - * 0: halt - * 1-3: tc - * 4: fbr_big_endian - * 5: psr_big_endian - * 6: pkt_big_endian - * 7: dma_big_endian - * 8-9: fbr0_size - * 10: fbr0_enable - * 11-12: fbr1_size - * 13: fbr1_enable - * 14: unused - * 15: pkt_drop_disable - * 16: pkt_done_flush - * 17: halt_status - * 18-31: unused - */ - - -/* - * structure for dma writeback lo reg in rxdma address map - * located at address 0x2004 - * Defined earlier (u32) - */ - -/* - * structure for dma writeback hi reg in rxdma address map - * located at address 0x2008 - * Defined earlier (u32) - */ - -/* - * structure for number of packets done reg in rxdma address map - * located at address 0x200C - * - * 31-8: unused - * 7-0: num done - */ - -/* - * structure for max packet time reg in rxdma address map - * located at address 0x2010 - * - * 31-18: unused - * 17-0: time done - */ - -/* - * structure for rx queue read address reg in rxdma address map - * located at address 0x2014 - * Defined earlier (u32) - */ - -/* - * structure for rx queue read address external reg in rxdma address map - * located at address 0x2018 - * Defined earlier (u32) - */ - -/* - * structure for rx queue write address reg in rxdma address map - * located at address 0x201C - * Defined earlier (u32) - */ - -/* - * structure for packet status ring base address lo reg in rxdma address map - * located at address 0x2020 - * Defined earlier (u32) - */ - -/* - * structure for packet status ring base address hi reg in rxdma address map - * located at address 0x2024 - * Defined earlier (u32) - */ - -/* - * structure for packet status ring number of descriptors reg in rxdma address - * map. Located at address 0x2028 - * - * 31-12: unused - * 11-0: psr ndes - */ - -/* - * structure for packet status ring available offset reg in rxdma address map - * located at address 0x202C - * - * 31-13: unused - * 12: psr avail wrap - * 11-0: psr avail - */ - -/* - * structure for packet status ring full offset reg in rxdma address map - * located at address 0x2030 - * - * 31-13: unused - * 12: psr full wrap - * 11-0: psr full - */ - -/* - * structure for packet status ring access index reg in rxdma address map - * located at address 0x2034 - * - * 31-5: unused - * 4-0: psr_ai - */ - -/* - * structure for packet status ring minimum descriptors reg in rxdma address - * map. Located at address 0x2038 - * - * 31-12: unused - * 11-0: psr_min - */ - -/* - * structure for free buffer ring base lo address reg in rxdma address map - * located at address 0x203C - * Defined earlier (u32) - */ - -/* - * structure for free buffer ring base hi address reg in rxdma address map - * located at address 0x2040 - * Defined earlier (u32) - */ - -/* - * structure for free buffer ring number of descriptors reg in rxdma address - * map. Located at address 0x2044 - * - * 31-10: unused - * 9-0: fbr ndesc - */ - -/* - * structure for free buffer ring 0 available offset reg in rxdma address map - * located at address 0x2048 - * Defined earlier (u32) - */ - -/* - * structure for free buffer ring 0 full offset reg in rxdma address map - * located at address 0x204C - * Defined earlier (u32) - */ - -/* - * structure for free buffer cache 0 full offset reg in rxdma address map - * located at address 0x2050 - * - * 31-5: unused - * 4-0: fbc rdi - */ - -/* - * structure for free buffer ring 0 minimum descriptor reg in rxdma address map - * located at address 0x2054 - * - * 31-10: unused - * 9-0: fbr min - */ - -/* - * structure for free buffer ring 1 base address lo reg in rxdma address map - * located at address 0x2058 - 0x205C - * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t) - */ - -/* - * structure for free buffer ring 1 number of descriptors reg in rxdma address - * map. Located at address 0x2060 - * Defined earlier (RXDMA_FBR_NUM_DES_t) - */ - -/* - * structure for free buffer ring 1 available offset reg in rxdma address map - * located at address 0x2064 - * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t) - */ - -/* - * structure for free buffer ring 1 full offset reg in rxdma address map - * located at address 0x2068 - * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t) - */ - -/* - * structure for free buffer cache 1 read index reg in rxdma address map - * located at address 0x206C - * Defined Earlier (RXDMA_FBC_RD_INDEX_t) - */ - -/* - * structure for free buffer ring 1 minimum descriptor reg in rxdma address map - * located at address 0x2070 - * Defined Earlier (RXDMA_FBR_MIN_DES_t) - */ - -/* - * Rx DMA Module of JAGCore Address Mapping - * Located at address 0x2000 - */ -struct rxdma_regs { /* Location: */ - u32 csr; /* 0x2000 */ - u32 dma_wb_base_lo; /* 0x2004 */ - u32 dma_wb_base_hi; /* 0x2008 */ - u32 num_pkt_done; /* 0x200C */ - u32 max_pkt_time; /* 0x2010 */ - u32 rxq_rd_addr; /* 0x2014 */ - u32 rxq_rd_addr_ext; /* 0x2018 */ - u32 rxq_wr_addr; /* 0x201C */ - u32 psr_base_lo; /* 0x2020 */ - u32 psr_base_hi; /* 0x2024 */ - u32 psr_num_des; /* 0x2028 */ - u32 psr_avail_offset; /* 0x202C */ - u32 psr_full_offset; /* 0x2030 */ - u32 psr_access_index; /* 0x2034 */ - u32 psr_min_des; /* 0x2038 */ - u32 fbr0_base_lo; /* 0x203C */ - u32 fbr0_base_hi; /* 0x2040 */ - u32 fbr0_num_des; /* 0x2044 */ - u32 fbr0_avail_offset; /* 0x2048 */ - u32 fbr0_full_offset; /* 0x204C */ - u32 fbr0_rd_index; /* 0x2050 */ - u32 fbr0_min_des; /* 0x2054 */ - u32 fbr1_base_lo; /* 0x2058 */ - u32 fbr1_base_hi; /* 0x205C */ - u32 fbr1_num_des; /* 0x2060 */ - u32 fbr1_avail_offset; /* 0x2064 */ - u32 fbr1_full_offset; /* 0x2068 */ - u32 fbr1_rd_index; /* 0x206C */ - u32 fbr1_min_des; /* 0x2070 */ -}; - -/* END OF RXDMA REGISTER ADDRESS MAP */ - - -/* START OF TXMAC REGISTER ADDRESS MAP */ - -/* - * structure for control reg in txmac address map - * located at address 0x3000 - * - * bits - * 31-8: unused - * 7: cklseg_disable - * 6: ckbcnt_disable - * 5: cksegnum - * 4: async_disable - * 3: fc_disable - * 2: mcif_disable - * 1: mif_disable - * 0: txmac_en - */ - -/* - * structure for shadow pointer reg in txmac address map - * located at address 0x3004 - * 31-27: reserved - * 26-16: txq rd ptr - * 15-11: reserved - * 10-0: txq wr ptr - */ - -/* - * structure for error count reg in txmac address map - * located at address 0x3008 - * - * 31-12: unused - * 11-8: reserved - * 7-4: txq_underrun - * 3-0: fifo_underrun - */ - -/* - * structure for max fill reg in txmac address map - * located at address 0x300C - * 31-12: unused - * 11-0: max fill - */ - -/* - * structure for cf parameter reg in txmac address map - * located at address 0x3010 - * 31-16: cfep - * 15-0: cfpt - */ - -/* - * structure for tx test reg in txmac address map - * located at address 0x3014 - * 31-17: unused - * 16: reserved1 - * 15: txtest_en - * 14-11: unused - * 10-0: txq test pointer - */ - -/* - * structure for error reg in txmac address map - * located at address 0x3018 - * - * 31-9: unused - * 8: fifo_underrun - * 7-6: unused - * 5: ctrl2_err - * 4: txq_underrun - * 3: bcnt_err - * 2: lseg_err - * 1: segnum_err - * 0: seg0_err - */ - -/* - * structure for error interrupt reg in txmac address map - * located at address 0x301C - * - * 31-9: unused - * 8: fifo_underrun - * 7-6: unused - * 5: ctrl2_err - * 4: txq_underrun - * 3: bcnt_err - * 2: lseg_err - * 1: segnum_err - * 0: seg0_err - */ - -/* - * structure for error interrupt reg in txmac address map - * located at address 0x3020 - * - * 31-2: unused - * 1: bp_req - * 0: bp_xonxoff - */ - -/* - * Tx MAC Module of JAGCore Address Mapping - */ -struct txmac_regs { /* Location: */ - u32 ctl; /* 0x3000 */ - u32 shadow_ptr; /* 0x3004 */ - u32 err_cnt; /* 0x3008 */ - u32 max_fill; /* 0x300C */ - u32 cf_param; /* 0x3010 */ - u32 tx_test; /* 0x3014 */ - u32 err; /* 0x3018 */ - u32 err_int; /* 0x301C */ - u32 bp_ctrl; /* 0x3020 */ -}; - -/* END OF TXMAC REGISTER ADDRESS MAP */ - -/* START OF RXMAC REGISTER ADDRESS MAP */ - -/* - * structure for rxmac control reg in rxmac address map - * located at address 0x4000 - * - * 31-7: reserved - * 6: rxmac_int_disable - * 5: async_disable - * 4: mif_disable - * 3: wol_disable - * 2: pkt_filter_disable - * 1: mcif_disable - * 0: rxmac_en - */ - -/* - * structure for Wake On Lan Control and CRC 0 reg in rxmac address map - * located at address 0x4004 - * 31-16: crc - * 15-12: reserved - * 11: ignore_pp - * 10: ignore_mp - * 9: clr_intr - * 8: ignore_link_chg - * 7: ignore_uni - * 6: ignore_multi - * 5: ignore_broad - * 4-0: valid_crc 4-0 - */ - -/* - * structure for CRC 1 and CRC 2 reg in rxmac address map - * located at address 0x4008 - * - * 31-16: crc2 - * 15-0: crc1 - */ - -/* - * structure for CRC 3 and CRC 4 reg in rxmac address map - * located at address 0x400C - * - * 31-16: crc4 - * 15-0: crc3 - */ - -/* - * structure for Wake On Lan Source Address Lo reg in rxmac address map - * located at address 0x4010 - * - * 31-24: sa3 - * 23-16: sa4 - * 15-8: sa5 - * 7-0: sa6 - */ - -#define ET_WOL_LO_SA3_SHIFT 24 -#define ET_WOL_LO_SA4_SHIFT 16 -#define ET_WOL_LO_SA5_SHIFT 8 - -/* - * structure for Wake On Lan Source Address Hi reg in rxmac address map - * located at address 0x4014 - * - * 31-16: reserved - * 15-8: sa1 - * 7-0: sa2 - */ - -#define ET_WOL_HI_SA1_SHIFT 8 - -/* - * structure for Wake On Lan mask reg in rxmac address map - * located at address 0x4018 - 0x4064 - * Defined earlier (u32) - */ - -/* - * structure for Unicast Paket Filter Address 1 reg in rxmac address map - * located at address 0x4068 - * - * 31-24: addr1_3 - * 23-16: addr1_4 - * 15-8: addr1_5 - * 7-0: addr1_6 - */ - -#define ET_UNI_PF_ADDR1_3_SHIFT 24 -#define ET_UNI_PF_ADDR1_4_SHIFT 16 -#define ET_UNI_PF_ADDR1_5_SHIFT 8 - -/* - * structure for Unicast Paket Filter Address 2 reg in rxmac address map - * located at address 0x406C - * - * 31-24: addr2_3 - * 23-16: addr2_4 - * 15-8: addr2_5 - * 7-0: addr2_6 - */ - -#define ET_UNI_PF_ADDR2_3_SHIFT 24 -#define ET_UNI_PF_ADDR2_4_SHIFT 16 -#define ET_UNI_PF_ADDR2_5_SHIFT 8 - -/* - * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map - * located at address 0x4070 - * - * 31-24: addr2_1 - * 23-16: addr2_2 - * 15-8: addr1_1 - * 7-0: addr1_2 - */ - -#define ET_UNI_PF_ADDR2_1_SHIFT 24 -#define ET_UNI_PF_ADDR2_2_SHIFT 16 -#define ET_UNI_PF_ADDR1_1_SHIFT 8 - - -/* - * structure for Multicast Hash reg in rxmac address map - * located at address 0x4074 - 0x4080 - * Defined earlier (u32) - */ - -/* - * structure for Packet Filter Control reg in rxmac address map - * located at address 0x4084 - * - * 31-23: unused - * 22-16: min_pkt_size - * 15-4: unused - * 3: filter_frag_en - * 2: filter_uni_en - * 1: filter_multi_en - * 0: filter_broad_en - */ - -/* - * structure for Memory Controller Interface Control Max Segment reg in rxmac - * address map. Located at address 0x4088 - * - * 31-10: reserved - * 9-2: max_size - * 1: fc_en - * 0: seg_en - */ - -/* - * structure for Memory Controller Interface Water Mark reg in rxmac address - * map. Located at address 0x408C - * - * 31-26: unused - * 25-16: mark_hi - * 15-10: unused - * 9-0: mark_lo - */ - -/* - * structure for Rx Queue Dialog reg in rxmac address map. - * located at address 0x4090 - * - * 31-26: reserved - * 25-16: rd_ptr - * 15-10: reserved - * 9-0: wr_ptr - */ - -/* - * structure for space available reg in rxmac address map. - * located at address 0x4094 - * - * 31-17: reserved - * 16: space_avail_en - * 15-10: reserved - * 9-0: space_avail - */ - -/* - * structure for management interface reg in rxmac address map. - * located at address 0x4098 - * - * 31-18: reserved - * 17: drop_pkt_en - * 16-0: drop_pkt_mask - */ - -/* - * structure for Error reg in rxmac address map. - * located at address 0x409C - * - * 31-4: unused - * 3: mif - * 2: async - * 1: pkt_filter - * 0: mcif - */ - -/* - * Rx MAC Module of JAGCore Address Mapping - */ -struct rxmac_regs { /* Location: */ - u32 ctrl; /* 0x4000 */ - u32 crc0; /* 0x4004 */ - u32 crc12; /* 0x4008 */ - u32 crc34; /* 0x400C */ - u32 sa_lo; /* 0x4010 */ - u32 sa_hi; /* 0x4014 */ - u32 mask0_word0; /* 0x4018 */ - u32 mask0_word1; /* 0x401C */ - u32 mask0_word2; /* 0x4020 */ - u32 mask0_word3; /* 0x4024 */ - u32 mask1_word0; /* 0x4028 */ - u32 mask1_word1; /* 0x402C */ - u32 mask1_word2; /* 0x4030 */ - u32 mask1_word3; /* 0x4034 */ - u32 mask2_word0; /* 0x4038 */ - u32 mask2_word1; /* 0x403C */ - u32 mask2_word2; /* 0x4040 */ - u32 mask2_word3; /* 0x4044 */ - u32 mask3_word0; /* 0x4048 */ - u32 mask3_word1; /* 0x404C */ - u32 mask3_word2; /* 0x4050 */ - u32 mask3_word3; /* 0x4054 */ - u32 mask4_word0; /* 0x4058 */ - u32 mask4_word1; /* 0x405C */ - u32 mask4_word2; /* 0x4060 */ - u32 mask4_word3; /* 0x4064 */ - u32 uni_pf_addr1; /* 0x4068 */ - u32 uni_pf_addr2; /* 0x406C */ - u32 uni_pf_addr3; /* 0x4070 */ - u32 multi_hash1; /* 0x4074 */ - u32 multi_hash2; /* 0x4078 */ - u32 multi_hash3; /* 0x407C */ - u32 multi_hash4; /* 0x4080 */ - u32 pf_ctrl; /* 0x4084 */ - u32 mcif_ctrl_max_seg; /* 0x4088 */ - u32 mcif_water_mark; /* 0x408C */ - u32 rxq_diag; /* 0x4090 */ - u32 space_avail; /* 0x4094 */ - - u32 mif_ctrl; /* 0x4098 */ - u32 err_reg; /* 0x409C */ -}; - -/* END OF RXMAC REGISTER ADDRESS MAP */ - - -/* START OF MAC REGISTER ADDRESS MAP */ - -/* - * structure for configuration #1 reg in mac address map. - * located at address 0x5000 - * - * 31: soft reset - * 30: sim reset - * 29-20: reserved - * 19: reset rx mc - * 18: reset tx mc - * 17: reset rx func - * 16: reset tx fnc - * 15-9: reserved - * 8: loopback - * 7-6: reserved - * 5: rx flow - * 4: tx flow - * 3: syncd rx en - * 2: rx enable - * 1: syncd tx en - * 0: tx enable - */ - -#define CFG1_LOOPBACK 0x00000100 -#define CFG1_RX_FLOW 0x00000020 -#define CFG1_TX_FLOW 0x00000010 -#define CFG1_RX_ENABLE 0x00000004 -#define CFG1_TX_ENABLE 0x00000001 -#define CFG1_WAIT 0x0000000A /* RX & TX syncd */ - -/* - * structure for configuration #2 reg in mac ad |