diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-05-02 09:28:03 -0700 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-05-02 09:28:03 -0700 |
commit | dfab34aa61a0f8c14a67d7b4c1dae28e57ba592d (patch) | |
tree | 581fd4d7394b838acb70c3c2e5d585b5b8a86b0d /drivers/pinctrl | |
parent | a7726350e06401929eac0aa0677a5467106565fc (diff) | |
parent | 88cf9c5e494795a53ec360d0b38f483a6d4e508f (diff) |
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device-tree updates from Olof Johansson:
"Part 1 of device-tree updates for 3.10. The bulk of the churn in this
branch is due to i.MX moving from C-defined pin control over to device
tree, which is a one-time conversion that will allow greater
flexibility down the road.
Besides that, there's PCI-e bindings for Marvell mvebu platforms and a
handful of cleanups to tegra due to the new include file functionality
of the device tree compiler"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (113 commits)
arm: mvebu: PCIe Device Tree informations for Armada XP GP
arm: mvebu: PCIe Device Tree informations for Armada 370 DB
arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
arm: mvebu: PCIe Device Tree informations for Armada XP DB
arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
arm: mvebu: add PCIe Device Tree informations for Armada XP
arm: mvebu: add PCIe Device Tree informations for Armada 370
ARM: sunxi: unify osc24M_fixed and osc24M
arm: vt8500: Add SDHC support to WM8505 DT
ARM: dts: Add a 64 bits version of the skeleton device tree
ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig
ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board
ARM: mvebu: Add support for NOR flash device on Armada XP-GP board
ARM: mvebu: Add Device Bus support for Armada 370/XP SoC
ARM: dts: imx6dl-wandboard: Add USB Host support
ARM: dts: imx51 cpu node
ARM: dts: Add missing imx27-phytec-phycore dtb target
ARM: dts: Add NFC support for i.MX27 Phytec PCM038 module
ARM: i.MX51: Add PATA support
ARM: dts: Add initial support for Wandboard Dual-Lite
...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r-- | drivers/pinctrl/Kconfig | 12 | ||||
-rw-r--r-- | drivers/pinctrl/Makefile | 1 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-imx.c | 126 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-imx.h | 29 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-imx35.c | 2088 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-imx51.c | 1532 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-imx53.c | 1597 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-imx6dl.c | 497 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-imx6q.c | 2301 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-imx6sl.c | 403 |
10 files changed, 2693 insertions, 5893 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f910962baaa7..51336b2aedc9 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -93,12 +93,20 @@ config PINCTRL_IMX53 Say Y here to enable the imx53 pinctrl driver config PINCTRL_IMX6Q - bool "IMX6Q pinctrl driver" + bool "IMX6Q/DL pinctrl driver" depends on OF depends on SOC_IMX6Q select PINCTRL_IMX help - Say Y here to enable the imx6q pinctrl driver + Say Y here to enable the imx6q/dl pinctrl driver + +config PINCTRL_IMX6SL + bool "IMX6SL pinctrl driver" + depends on OF + depends on SOC_IMX6SL + select PINCTRL_IMX + help + Say Y here to enable the imx6sl pinctrl driver config PINCTRL_LANTIQ bool diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 988279ae23cd..b9aaa61facd1 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o +obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c index 0ef190449eab..4fcfff9243be 100644 --- a/drivers/pinctrl/pinctrl-imx.c +++ b/drivers/pinctrl/pinctrl-imx.c @@ -54,32 +54,6 @@ struct imx_pinctrl { const struct imx_pinctrl_soc_info *info; }; -static const struct imx_pin_reg *imx_find_pin_reg( - const struct imx_pinctrl_soc_info *info, - unsigned pin, bool is_mux, unsigned mux) -{ - const struct imx_pin_reg *pin_reg = NULL; - int i; - - for (i = 0; i < info->npin_regs; i++) { - pin_reg = &info->pin_regs[i]; - if (pin_reg->pid != pin) - continue; - if (!is_mux) - break; - else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK)) - break; - } - - if (i == info->npin_regs) { - dev_err(info->dev, "Pin(%s): unable to find pin reg map\n", - info->pins[pin].name); - return NULL; - } - - return pin_reg; -} - static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( const struct imx_pinctrl_soc_info *info, const char *name) @@ -223,7 +197,8 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg; - const unsigned *pins, *mux; + const unsigned *pins, *mux, *input_val; + u16 *input_reg; unsigned int npins, pin_id; int i; @@ -234,18 +209,17 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, pins = info->groups[group].pins; npins = info->groups[group].npins; mux = info->groups[group].mux_mode; + input_val = info->groups[group].input_val; + input_reg = info->groups[group].input_reg; - WARN_ON(!pins || !npins || !mux); + WARN_ON(!pins || !npins || !mux || !input_val || !input_reg); dev_dbg(ipctl->dev, "enable function %s group %s\n", info->functions[selector].name, info->groups[group].name); for (i = 0; i < npins; i++) { pin_id = pins[i]; - - pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]); - if (!pin_reg) - return -EINVAL; + pin_reg = &info->pin_regs[pin_id]; if (!pin_reg->mux_reg) { dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", @@ -258,11 +232,11 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, pin_reg->mux_reg, mux[i]); /* some pins also need select input setting, set it if found */ - if (pin_reg->input_reg) { - writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg); + if (input_reg[i]) { + writel(input_val[i], ipctl->base + input_reg[i]); dev_dbg(ipctl->dev, "==>select_input: offset 0x%x val 0x%x\n", - pin_reg->input_reg, pin_reg->input_val); + input_reg[i], input_val[i]); } } @@ -311,11 +285,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); - if (!pin_reg) - return -EINVAL; + const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; if (!pin_reg->conf_reg) { dev_err(info->dev, "Pin(%s) does not support config function\n", @@ -333,11 +303,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); - if (!pin_reg) - return -EINVAL; + const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; if (!pin_reg->conf_reg) { dev_err(info->dev, "Pin(%s) does not support config function\n", @@ -360,10 +326,9 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; + const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; unsigned long config; - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); if (!pin_reg || !pin_reg->conf_reg) { seq_printf(s, "N/A"); return; @@ -411,29 +376,20 @@ static struct pinctrl_desc imx_pinctrl_desc = { .owner = THIS_MODULE, }; -/* decode pin id and mux from pin function id got from device tree*/ -static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info, - unsigned int pin_func_id, unsigned int *pin_id, - unsigned int *mux) -{ - if (pin_func_id > info->npin_regs) - return -EINVAL; - - *pin_id = info->pin_regs[pin_func_id].pid; - *mux = info->pin_regs[pin_func_id].mux_mode; - - return 0; -} +/* + * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and + * 1 u32 CONFIG, so 24 types in total for each pin. + */ +#define FSL_PIN_SIZE 24 static int imx_pinctrl_parse_groups(struct device_node *np, struct imx_pin_group *grp, struct imx_pinctrl_soc_info *info, u32 index) { - unsigned int pin_func_id; - int ret, size; + int size; const __be32 *list; - int i, j; + int i; u32 config; dev_dbg(info->dev, "group(%d): %s\n", index, np->name); @@ -447,32 +403,40 @@ static int imx_pinctrl_parse_groups(struct device_node *np, */ list = of_get_property(np, "fsl,pins", &size); /* we do not check return since it's safe node passed down */ - size /= sizeof(*list); - if (!size || size % 2) { - dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n"); + if (!size || size % FSL_PIN_SIZE) { + dev_err(info->dev, "Invalid fsl,pins property\n"); return -EINVAL; } - grp->npins = size / 2; + grp->npins = size / FSL_PIN_SIZE; grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), GFP_KERNEL); grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), GFP_KERNEL); + grp->input_reg = devm_kzalloc(info->dev, grp->npins * sizeof(u16), + GFP_KERNEL); + grp->input_val = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), + GFP_KERNEL); grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long), GFP_KERNEL); - for (i = 0, j = 0; i < size; i += 2, j++) { - pin_func_id = be32_to_cpu(*list++); - ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id, - &grp->pins[j], &grp->mux_mode[j]); - if (ret) { - dev_err(info->dev, "get invalid pin function id\n"); - return -EINVAL; - } + for (i = 0; i < grp->npins; i++) { + u32 mux_reg = be32_to_cpu(*list++); + u32 conf_reg = be32_to_cpu(*list++); + unsigned int pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; + struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; + + grp->pins[i] = pin_id; + pin_reg->mux_reg = mux_reg; + pin_reg->conf_reg = conf_reg; + grp->input_reg[i] = be32_to_cpu(*list++); + grp->mux_mode[i] = be32_to_cpu(*list++); + grp->input_val[i] = be32_to_cpu(*list++); + /* SION bit is in mux register */ config = be32_to_cpu(*list++); if (config & IMX_PAD_SION) - grp->mux_mode[j] |= IOMUXC_CONFIG_SION; - grp->configs[j] = config & ~IMX_PAD_SION; + grp->mux_mode[i] |= IOMUXC_CONFIG_SION; + grp->configs[i] = config & ~IMX_PAD_SION; } #ifdef DEBUG @@ -568,8 +532,7 @@ int imx_pinctrl_probe(struct platform_device *pdev, struct resource *res; int ret; - if (!info || !info->pins || !info->npins - || !info->pin_regs || !info->npin_regs) { + if (!info || !info->pins || !info->npins) { dev_err(&pdev->dev, "wrong pinctrl info\n"); return -EINVAL; } @@ -580,6 +543,11 @@ int imx_pinctrl_probe(struct platform_device *pdev, if (!ipctl) return -ENOMEM; + info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) * + info->npins, GFP_KERNEL); + if (!info->pin_regs) + return -ENOMEM; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENOENT; diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h index 9b65e7828f1d..607ef5497552 100644 --- a/drivers/pinctrl/pinctrl-imx.h +++ b/drivers/pinctrl/pinctrl-imx.h @@ -26,6 +26,10 @@ struct platform_device; * elements in .pins so we can iterate over that array * @mux_mode: the mux mode for each pin in this group. The size of this * array is the same as pins. + * @input_reg: select input register offset for this mux if any + * 0 if no select input setting needed. + * @input_val: the select input value for each pin in this group. The size of + * this array is the same as pins. * @configs: the config for each pin in this group. The size of this * array is the same as pins. */ @@ -34,6 +38,8 @@ struct imx_pin_group { unsigned int *pins; unsigned npins; unsigned int *mux_mode; + u16 *input_reg; + unsigned int *input_val; unsigned long *configs; }; @@ -51,30 +57,19 @@ struct imx_pmx_func { /** * struct imx_pin_reg - describe a pin reg map - * The last 3 members are used for select input setting - * @pid: pin id * @mux_reg: mux register offset * @conf_reg: config register offset - * @mux_mode: mux mode - * @input_reg: select input register offset for this mux if any - * 0 if no select input setting needed. - * @input_val: the value set to select input register */ struct imx_pin_reg { - u16 pid; u16 mux_reg; u16 conf_reg; - u8 mux_mode; - u16 input_reg; - u8 input_val; }; struct imx_pinctrl_soc_info { struct device *dev; const struct pinctrl_pin_desc *pins; unsigned int npins; - const struct imx_pin_reg *pin_regs; - unsigned int npin_regs; + struct imx_pin_reg *pin_regs; struct imx_pin_group *groups; unsigned int ngroups; struct imx_pmx_func *functions; @@ -84,16 +79,6 @@ struct imx_pinctrl_soc_info { #define NO_MUX 0x0 #define NO_PAD 0x0 -#define IMX_PIN_REG(id, conf, mux, mode, input, val) \ - { \ - .pid = id, \ - .conf_reg = conf, \ - .mux_reg = mux, \ - .mux_mode = mode, \ - .input_reg = input, \ - .input_val = val, \ - } - #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) #define PAD_CTL_MASK(len) ((1 << len) - 1) diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c index 6e214110e3d5..c4549829fc47 100644 --- a/drivers/pinctrl/pinctrl-imx35.c +++ b/drivers/pinctrl/pinctrl-imx35.c @@ -24,1249 +24,496 @@ #include "pinctrl-imx.h" enum imx35_pads { - MX35_PAD_CAPTURE = 0, - MX35_PAD_COMPARE = 1, - MX35_PAD_WDOG_RST = 2, - MX35_PAD_GPIO1_0 = 3, - MX35_PAD_GPIO1_1 = 4, - MX35_PAD_GPIO2_0 = 5, - MX35_PAD_GPIO3_0 = 6, - MX35_PAD_RESET_IN_B = 7, - MX35_PAD_POR_B = 8, - MX35_PAD_CLKO = 9, - MX35_PAD_BOOT_MODE0 = 10, - MX35_PAD_BOOT_MODE1 = 11, - MX35_PAD_CLK_MODE0 = 12, - MX35_PAD_CLK_MODE1 = 13, - MX35_PAD_POWER_FAIL = 14, - MX35_PAD_VSTBY = 15, - MX35_PAD_A0 = 16, - MX35_PAD_A1 = 17, - MX35_PAD_A2 = 18, - MX35_PAD_A3 = 19, - MX35_PAD_A4 = 20, - MX35_PAD_A5 = 21, - MX35_PAD_A6 = 22, - MX35_PAD_A7 = 23, - MX35_PAD_A8 = 24, - MX35_PAD_A9 = 25, - MX35_PAD_A10 = 26, - MX35_PAD_MA10 = 27, - MX35_PAD_A11 = 28, - MX35_PAD_A12 = 29, - MX35_PAD_A13 = 30, - MX35_PAD_A14 = 31, - MX35_PAD_A15 = 32, - MX35_PAD_A16 = 33, - MX35_PAD_A17 = 34, - MX35_PAD_A18 = 35, - MX35_PAD_A19 = 36, - MX35_PAD_A20 = 37, - MX35_PAD_A21 = 38, - MX35_PAD_A22 = 39, - MX35_PAD_A23 = 40, - MX35_PAD_A24 = 41, - MX35_PAD_A25 = 42, - MX35_PAD_SDBA1 = 43, - MX35_PAD_SDBA0 = 44, - MX35_PAD_SD0 = 45, - MX35_PAD_SD1 = 46, - MX35_PAD_SD2 = 47, - MX35_PAD_SD3 = 48, - MX35_PAD_SD4 = 49, - MX35_PAD_SD5 = 50, - MX35_PAD_SD6 = 51, - MX35_PAD_SD7 = 52, - MX35_PAD_SD8 = 53, - MX35_PAD_SD9 = 54, - MX35_PAD_SD10 = 55, - MX35_PAD_SD11 = 56, - MX35_PAD_SD12 = 57, - MX35_PAD_SD13 = 58, - MX35_PAD_SD14 = 59, - MX35_PAD_SD15 = 60, - MX35_PAD_SD16 = 61, - MX35_PAD_SD17 = 62, - MX35_PAD_SD18 = 63, - MX35_PAD_SD19 = 64, - MX35_PAD_SD20 = 65, - MX35_PAD_SD21 = 66, - MX35_PAD_SD22 = 67, - MX35_PAD_SD23 = 68, - MX35_PAD_SD24 = 69, - MX35_PAD_SD25 = 70, - MX35_PAD_SD26 = 71, - MX35_PAD_SD27 = 72, - MX35_PAD_SD28 = 73, - MX35_PAD_SD29 = 74, - MX35_PAD_SD30 = 75, - MX35_PAD_SD31 = 76, - MX35_PAD_DQM0 = 77, - MX35_PAD_DQM1 = 78, - MX35_PAD_DQM2 = 79, - MX35_PAD_DQM3 = 80, - MX35_PAD_EB0 = 81, - MX35_PAD_EB1 = 82, - MX35_PAD_OE = 83, - MX35_PAD_CS0 = 84, - MX35_PAD_CS1 = 85, - MX35_PAD_CS2 = 86, - MX35_PAD_CS3 = 87, - MX35_PAD_CS4 = 88, - MX35_PAD_CS5 = 89, - MX35_PAD_NF_CE0 = 90, - MX35_PAD_ECB = 91, - MX35_PAD_LBA = 92, - MX35_PAD_BCLK = 93, - MX35_PAD_RW = 94, - MX35_PAD_RAS = 95, - MX35_PAD_CAS = 96, - MX35_PAD_SDWE = 97, - MX35_PAD_SDCKE0 = 98, - MX35_PAD_SDCKE1 = 99, - MX35_PAD_SDCLK = 100, - MX35_PAD_SDQS0 = 101, - MX35_PAD_SDQS1 = 102, - MX35_PAD_SDQS2 = 103, - MX35_PAD_SDQS3 = 104, - MX35_PAD_NFWE_B = 105, - MX35_PAD_NFRE_B = 106, - MX35_PAD_NFALE = 107, - MX35_PAD_NFCLE = 108, - MX35_PAD_NFWP_B = 109, - MX35_PAD_NFRB = 110, - MX35_PAD_D15 = 111, - MX35_PAD_D14 = 112, - MX35_PAD_D13 = 113, - MX35_PAD_D12 = 114, - MX35_PAD_D11 = 115, - MX35_PAD_D10 = 116, - MX35_PAD_D9 = 117, - MX35_PAD_D8 = 118, - MX35_PAD_D7 = 119, - MX35_PAD_D6 = 120, - MX35_PAD_D5 = 121, - MX35_PAD_D4 = 122, - MX35_PAD_D3 = 123, - MX35_PAD_D2 = 124, - MX35_PAD_D1 = 125, - MX35_PAD_D0 = 126, - MX35_PAD_CSI_D8 = 127, - MX35_PAD_CSI_D9 = 128, - MX35_PAD_CSI_D10 = 129, - MX35_PAD_CSI_D11 = 130, - MX35_PAD_CSI_D12 = 131, - MX35_PAD_CSI_D13 = 132, - MX35_PAD_CSI_D14 = 133, - MX35_PAD_CSI_D15 = 134, - MX35_PAD_CSI_MCLK = 135, - MX35_PAD_CSI_VSYNC = 136, - MX35_PAD_CSI_HSYNC = 137, - MX35_PAD_CSI_PIXCLK = 138, - MX35_PAD_I2C1_CLK = 139, - MX35_PAD_I2C1_DAT = 140, - MX35_PAD_I2C2_CLK = 141, - MX35_PAD_I2C2_DAT = 142, - MX35_PAD_STXD4 = 143, - MX35_PAD_SRXD4 = 144, - MX35_PAD_SCK4 = 145, - MX35_PAD_STXFS4 = 146, - MX35_PAD_STXD5 = 147, - MX35_PAD_SRXD5 = 148, - MX35_PAD_SCK5 = 149, - MX35_PAD_STXFS5 = 150, - MX35_PAD_SCKR = 151, - MX35_PAD_FSR = 152, - MX35_PAD_HCKR = 153, - MX35_PAD_SCKT = 154, - MX35_PAD_FST = 155, - MX35_PAD_HCKT = 156, - MX35_PAD_TX5_RX0 = 157, - MX35_PAD_TX4_RX1 = 158, - MX35_PAD_TX3_RX2 = 159, - MX35_PAD_TX2_RX3 = 160, - MX35_PAD_TX1 = 161, - MX35_PAD_TX0 = 162, - MX35_PAD_CSPI1_MOSI = 163, - MX35_PAD_CSPI1_MISO = 164, - MX35_PAD_CSPI1_SS0 = 165, - MX35_PAD_CSPI1_SS1 = 166, - MX35_PAD_CSPI1_SCLK = 167, - MX35_PAD_CSPI1_SPI_RDY = 168, - MX35_PAD_RXD1 = 169, - MX35_PAD_TXD1 = 170, - MX35_PAD_RTS1 = 171, - MX35_PAD_CTS1 = 172, - MX35_PAD_RXD2 = 173, - MX35_PAD_TXD2 = 174, - MX35_PAD_RTS2 = 175, - MX35_PAD_CTS2 = 176, - MX35_PAD_RTCK = 177, - MX35_PAD_TCK = 178, - MX35_PAD_TMS = 179, - MX35_PAD_TDI = 180, - MX35_PAD_TDO = 181, - MX35_PAD_TRSTB = 182, - MX35_PAD_DE_B = 183, - MX35_PAD_SJC_MOD = 184, - MX35_PAD_USBOTG_PWR = 185, - MX35_PAD_USBOTG_OC = 186, - MX35_PAD_LD0 = 187, - MX35_PAD_LD1 = 188, - MX35_PAD_LD2 = 189, - MX35_PAD_LD3 = 190, - MX35_PAD_LD4 = 191, - MX35_PAD_LD5 = 192, - MX35_PAD_LD6 = 193, - MX35_PAD_LD7 = 194, - MX35_PAD_LD8 = 195, - MX35_PAD_LD9 = 196, - MX35_PAD_LD10 = 197, - MX35_PAD_LD11 = 198, - MX35_PAD_LD12 = 199, - MX35_PAD_LD13 = 200, - MX35_PAD_LD14 = 201, - MX35_PAD_LD15 = 202, - MX35_PAD_LD16 = 203, - MX35_PAD_LD17 = 204, - MX35_PAD_LD18 = 205, - MX35_PAD_LD19 = 206, - MX35_PAD_LD20 = 207, - MX35_PAD_LD21 = 208, - MX35_PAD_LD22 = 209, - MX35_PAD_LD23 = 210, - MX35_PAD_D3_HSYNC = 211, - MX35_PAD_D3_FPSHIFT = 212, - MX35_PAD_D3_DRDY = 213, - MX35_PAD_CONTRAST = 214, - MX35_PAD_D3_VSYNC = 215, - MX35_PAD_D3_REV = 216, - MX35_PAD_D3_CLS = 217, - MX35_PAD_D3_SPL = 218, - MX35_PAD_SD1_CMD = 219, - MX35_PAD_SD1_CLK = 220, - MX35_PAD_SD1_DATA0 = 221, - MX35_PAD_SD1_DATA1 = 222, - MX35_PAD_SD1_DATA2 = 223, - MX35_PAD_SD1_DATA3 = 224, - MX35_PAD_SD2_CMD = 225, - MX35_PAD_SD2_CLK = 226, - MX35_PAD_SD2_DATA0 = 227, - MX35_PAD_SD2_DATA1 = 228, - MX35_PAD_SD2_DATA2 = 229, - MX35_PAD_SD2_DATA3 = 230, - MX35_PAD_ATA_CS0 = 231, - MX35_PAD_ATA_CS1 = 232, - MX35_PAD_ATA_DIOR = 233, - MX35_PAD_ATA_DIOW = 234, - MX35_PAD_ATA_DMACK = 235, - MX35_PAD_ATA_RESET_B = 236, - MX35_PAD_ATA_IORDY = 237, - MX35_PAD_ATA_DATA0 = 238, - MX35_PAD_ATA_DATA1 = 239, - MX35_PAD_ATA_DATA2 = 240, - MX35_PAD_ATA_DATA3 = 241, - MX35_PAD_ATA_DATA4 = 242, - MX35_PAD_ATA_DATA5 = 243, - MX35_PAD_ATA_DATA6 = 244, - MX35_PAD_ATA_DATA7 = 245, - MX35_PAD_ATA_DATA8 = 246, - MX35_PAD_ATA_DATA9 = 247, - MX35_PAD_ATA_DATA10 = 248, - MX35_PAD_ATA_DATA11 = 249, - MX35_PAD_ATA_DATA12 = 250, - MX35_PAD_ATA_DATA13 = 251, - MX35_PAD_ATA_DATA14 = 252, - MX35_PAD_ATA_DATA15 = 253, - MX35_PAD_ATA_INTRQ = 254, - MX35_PAD_ATA_BUFF_EN = 255, - MX35_PAD_ATA_DMARQ = 256, - MX35_PAD_ATA_DA0 = 257, - MX35_PAD_ATA_DA1 = 258, - MX35_PAD_ATA_DA2 = 259, - MX35_PAD_MLB_CLK = 260, - MX35_PAD_MLB_DAT = 261, - MX35_PAD_MLB_SIG = 262, - MX35_PAD_FEC_TX_CLK = 263, - MX35_PAD_FEC_RX_CLK = 264, - MX35_PAD_FEC_RX_DV = 265, - MX35_PAD_FEC_COL = 266, - MX35_PAD_FEC_RDATA0 = 267, - MX35_PAD_FEC_TDATA0 = 268, - MX35_PAD_FEC_TX_EN = 269, - MX35_PAD_FEC_MDC = 270, - MX35_PAD_FEC_MDIO = 271, - MX35_PAD_FEC_TX_ERR = 272, - MX35_PAD_FEC_RX_ERR = 273, - MX35_PAD_FEC_CRS = 274, - MX35_PAD_FEC_RDATA1 = 275, - MX35_PAD_FEC_TDATA1 = 276, - MX35_PAD_FEC_RDATA2 = 277, - MX35_PAD_FEC_TDATA2 = 278, - MX35_PAD_FEC_RDATA3 = 279, - MX35_PAD_FEC_TDATA3 = 280, - MX35_PAD_EXT_ARMCLK = 281, - MX35_PAD_TEST_MODE = 282, -}; - -/* imx35 register maps */ -static struct imx_pin_reg imx35_pin_regs[] = { - [0] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 0, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CAPIN1 */ - [1] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 1, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CMPOUT2 */ - [2] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 2, 0x7f4, 0), /* MX35_PAD_CAPTURE__CSPI2_SS1 */ - [3] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 3, 0x0, 0), /* MX35_PAD_CAPTURE__EPIT1_EPITO */ - [4] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 4, 0x7d0, 0), /* MX35_PAD_CAPTURE__CCM_CLK32K */ - [5] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 5, 0x850, 0), /* MX35_PAD_CAPTURE__GPIO1_4 */ - [6] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 0, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT1 */ - [7] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 1, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CAPIN2 */ - [8] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 2, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT3 */ - [9] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 3, 0x0, 0), /* MX35_PAD_COMPARE__EPIT2_EPITO */ - [10] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 5, 0x854, 0), /* MX35_PAD_COMPARE__GPIO1_5 */ - [11] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 7, 0x0, 0), /* MX35_PAD_COMPARE__SDMA_EXTDMA_2 */ - [12] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 0, 0x0, 0), /* MX35_PAD_WDOG_RST__WDOG_WDOG_B */ - [13] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 3, 0x0, 0), /* MX35_PAD_WDOG_RST__IPU_FLASH_STROBE */ - [14] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 5, 0x858, 0), /* MX35_PAD_WDOG_RST__GPIO1_6 */ - [15] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 0, 0x82c, 0), /* MX35_PAD_GPIO1_0__GPIO1_0 */ - [16] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 1, 0x7d4, 0), /* MX35_PAD_GPIO1_0__CCM_PMIC_RDY */ - [17] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 2, 0x990, 0), /* MX35_PAD_GPIO1_0__OWIRE_LINE */ - [18] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 7, 0x0, 0), /* MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 */ - [19] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 0, 0x838, 0), /* MX35_PAD_GPIO1_1__GPIO1_1 */ - [20] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 2, 0x0, 0), /* MX35_PAD_GPIO1_1__PWM_PWMO */ - [21] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 3, 0x7d8, 0), /* MX35_PAD_GPIO1_1__CSPI1_SS2 */ - [22] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 6, 0x0, 0), /* MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT */ - [23] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 7, 0x0, 0), /* MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 */ - [24] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 0, 0x868, 0), /* MX35_PAD_GPIO2_0__GPIO2_0 */ - [25] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 1, 0x0, 0), /* MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK */ - [26] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 0, 0x8e8, 0), /* MX35_PAD_GPIO3_0__GPIO3_0 */ - [27] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 1, 0x0, 0), /* MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK */ - [28] = IMX_PIN_REG(MX35_PAD_RESET_IN_B, 0x344, 0x0, 0, 0x0, 0), /* MX35_PAD_RESET_IN_B__CCM_RESET_IN_B */ - [29] = IMX_PIN_REG(MX35_PAD_POR_B, 0x348, 0x0, 0, 0x0, 0), /* MX35_PAD_POR_B__CCM_POR_B */ - [30] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 0, 0x0, 0), /* MX35_PAD_CLKO__CCM_CLKO */ - [31] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 5, 0x860, 0), /* MX35_PAD_CLKO__GPIO1_8 */ - [32] = IMX_PIN_REG(MX35_PAD_BOOT_MODE0, 0x350, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 */ - [33] = IMX_PIN_REG(MX35_PAD_BOOT_MODE1, 0x354, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 */ - [34] = IMX_PIN_REG(MX35_PAD_CLK_MODE0, 0x358, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 */ - [35] = IMX_PIN_REG(MX35_PAD_CLK_MODE1, 0x35c, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 */ - [36] = IMX_PIN_REG(MX35_PAD_POWER_FAIL, 0x360, 0x0, 0, 0x0, 0), /* MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 */ - [37] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 0, 0x0, 0), /* MX35_PAD_VSTBY__CCM_VSTBY */ - [38] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 5, 0x85c, 0), /* MX35_PAD_VSTBY__GPIO1_7 */ - [39] = IMX_PIN_REG(MX35_PAD_A0, 0x368, 0x028, 0, 0x0, 0), /* MX35_PAD_A0__EMI_EIM_DA_L_0 */ - [40] = IMX_PIN_REG(MX35_PAD_A1, 0x36c, 0x02c, 0, 0x0, 0), /* MX35_PAD_A1__EMI_EIM_DA_L_1 */ - [41] = IMX_PIN_REG(MX35_PAD_A2, 0x370, 0x030, 0, 0x0, 0), /* MX35_PAD_A2__EMI_EIM_DA_L_2 */ - [42] = IMX_PIN_REG(MX35_PAD_A3, 0x374, 0x034, 0, 0x0, 0), /* MX35_PAD_A3__EMI_EIM_DA_L_3 */ - [43] = IMX_PIN_REG(MX35_PAD_A4, 0x378, 0x038, 0, 0x0, 0), /* MX35_PAD_A4__EMI_EIM_DA_L_4 */ - [44] = IMX_PIN_REG(MX35_PAD_A5, 0x37c, 0x03c, 0, 0x0, 0), /* MX35_PAD_A5__EMI_EIM_DA_L_5 */ - [45] = IMX_PIN_REG(MX35_PAD_A6, 0x380, 0x040, 0, 0x0, 0), /* MX35_PAD_A6__EMI_EIM_DA_L_6 */ - [46] = IMX_PIN_REG(MX35_PAD_A7, 0x384, 0x044, 0, 0x0, 0), /* MX35_PAD_A7__EMI_EIM_DA_L_7 */ - [47] = IMX_PIN_REG(MX35_PAD_A8, 0x388, 0x048, 0, 0x0, 0), /* MX35_PAD_A8__EMI_EIM_DA_H_8 */ - [48] = IMX_PIN_REG(MX35_PAD_A9, 0x38c, 0x04c, 0, 0x0, 0), /* MX35_PAD_A9__EMI_EIM_DA_H_9 */ - [49] = IMX_PIN_REG(MX35_PAD_A10, 0x390, 0x050, 0, 0x0, 0), /* MX35_PAD_A10__EMI_EIM_DA_H_10 */ - [50] = IMX_PIN_REG(MX35_PAD_MA10, 0x394, 0x054, 0, 0x0, 0), /* MX35_PAD_MA10__EMI_MA10 */ - [51] = IMX_PIN_REG(MX35_PAD_A11, 0x398, 0x058, 0, 0x0, 0), /* MX35_PAD_A11__EMI_EIM_DA_H_11 */ - [52] = IMX_PIN_REG(MX35_PAD_A12, 0x39c, 0x05c, 0, 0x0, 0), /* MX35_PAD_A12__EMI_EIM_DA_H_12 */ - [53] = IMX_PIN_REG(MX35_PAD_A13, 0x3a0, 0x060, 0, 0x0, 0), /* MX35_PAD_A13__EMI_EIM_DA_H_13 */ - [54] = IMX_PIN_REG(MX35_PAD_A14, 0x3a4, 0x064, 0, 0x0, 0), /* MX35_PAD_A14__EMI_EIM_DA_H2_14 */ - [55] = IMX_PIN_REG(MX35_PAD_A15, 0x3a8, 0x068, 0, 0x0, 0), /* MX35_PAD_A15__EMI_EIM_DA_H2_15 */ - [56] = IMX_PIN_REG(MX35_PAD_A16, 0x3ac, 0x06c, 0, 0x0, 0), /* MX35_PAD_A16__EMI_EIM_A_16 */ - [57] = IMX_PIN_REG(MX35_PAD_A17, 0x3b0, 0x070, 0, 0x0, 0), /* MX35_PAD_A17__EMI_EIM_A_17 */ - [58] = IMX_PIN_REG(MX35_PAD_A18, 0x3b4, 0x074, 0, 0x0, 0), /* MX35_PAD_A18__EMI_EIM_A_18 */ - [59] = IMX_PIN_REG(MX35_PAD_A19, 0x3b8, 0x078, 0, 0x0, 0), /* MX35_PAD_A19__EMI_EIM_A_19 */ - [60] = IMX_PIN_REG(MX35_PAD_A20, 0x3bc, 0x07c, 0, 0x0, 0), /* MX35_PAD_A20__EMI_EIM_A_20 */ - [61] = IMX_PIN_REG(MX35_PAD_A21, 0x3c0, 0x080, 0, 0x0, 0), /* MX35_PAD_A21__EMI_EIM_A_21 */ - [62] = IMX_PIN_REG(MX35_PAD_A22, 0x3c4, 0x084, 0, 0x0, 0), /* MX35_PAD_A22__EMI_EIM_A_22 */ - [63] = IMX_PIN_REG(MX35_PAD_A23, 0x3c8, 0x088, 0, 0x0, 0), /* MX35_PAD_A23__EMI_EIM_A_23 */ - [64] = IMX_PIN_REG(MX35_PAD_A24, 0x3cc, 0x08c, 0, 0x0, 0), /* MX35_PAD_A24__EMI_EIM_A_24 */ - [65] = IMX_PIN_REG(MX35_PAD_A25, 0x3d0, 0x090, 0, 0x0, 0), /* MX35_PAD_A25__EMI_EIM_A_25 */ - [66] = IMX_PIN_REG(MX35_PAD_SDBA1, 0x3d4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA1__EMI_EIM_SDBA1 */ - [67] = IMX_PIN_REG(MX35_PAD_SDBA0, 0x3d8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA0__EMI_EIM_SDBA0 */ - [68] = IMX_PIN_REG(MX35_PAD_SD0, 0x3dc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD0__EMI_DRAM_D_0 */ - [69] = IMX_PIN_REG(MX35_PAD_SD1, 0x3e0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD1__EMI_DRAM_D_1 */ - [70] = IMX_PIN_REG(MX35_PAD_SD2, 0x3e4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD2__EMI_DRAM_D_2 */ - [71] = IMX_PIN_REG(MX35_PAD_SD3, 0x3e8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD3__EMI_DRAM_D_3 */ - [72] = IMX_PIN_REG(MX35_PAD_SD4, 0x3ec, 0x0, 0, 0x0, 0), /* MX35_PAD_SD4__EMI_DRAM_D_4 */ - [73] = IMX_PIN_REG(MX35_PAD_SD5, 0x3f0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD5__EMI_DRAM_D_5 */ - [74] = IMX_PIN_REG(MX35_PAD_SD6, 0x3f4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD6__EMI_DRAM_D_6 */ - [75] = IMX_PIN_REG(MX35_PAD_SD7, 0x3f8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD7__EMI_DRAM_D_7 */ - [76] = IMX_PIN_REG(MX35_PAD_SD8, 0x3fc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD8__EMI_DRAM_D_8 */ - [77] = IMX_PIN_REG(MX35_PAD_SD9, 0x400, 0x0, 0, 0x0, 0), /* MX35_PAD_SD9__EMI_DRAM_D_9 */ - [78] = IMX_PIN_REG(MX35_PAD_SD10, 0x404, 0x0, 0, 0x0, 0), /* MX35_PAD_SD10__EMI_DRAM_D_10 */ - [79] = IMX_PIN_REG(MX35_PAD_SD11, 0x408, 0x0, 0, 0x0, 0), /* MX35_PAD_SD11__EMI_DRAM_D_11 */ - [80] = IMX_PIN_REG(MX35_PAD_SD12, 0x40c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD12__EMI_DRAM_D_12 */ - [81] = IMX_PIN_REG(MX35_PAD_SD13, 0x410, 0x0, 0, 0x0, 0), /* MX35_PAD_SD13__EMI_DRAM_D_13 */ - [82] = IMX_PIN_REG(MX35_PAD_SD14, 0x414, 0x0, 0, 0x0, 0), /* MX35_PAD_SD14__EMI_DRAM_D_14 */ - [83] = IMX_PIN_REG(MX35_PAD_SD15, 0x418, 0x0, 0, 0x0, 0), /* MX35_PAD_SD15__EMI_DRAM_D_15 */ - [84] = IMX_PIN_REG(MX35_PAD_SD16, 0x41c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD16__EMI_DRAM_D_16 */ - [85] = IMX_PIN_REG(MX35_PAD_SD17, 0x420, 0x0, 0, 0x0, 0), /* MX35_PAD_SD17__EMI_DRAM_D_17 */ - [86] = IMX_PIN_REG(MX35_PAD_SD18, 0x424, 0x0, 0, 0x0, 0), /* MX35_PAD_SD18__EMI_DRAM_D_18 */ - [87] = IMX_PIN_REG(MX35_PAD_SD19, 0x428, 0x0, 0, 0x0, 0), /* MX35_PAD_SD19__EMI_DRAM_D_19 */ - [88] = IMX_PIN_REG(MX35_PAD_SD20, 0x42c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD20__EMI_DRAM_D_20 */ - [89] = IMX_PIN_REG(MX35_PAD_SD21, 0x430, 0x0, 0, 0x0, 0), /* MX35_PAD_SD21__EMI_DRAM_D_21 */ - [90] = IMX_PIN_REG(MX35_PAD_SD22, 0x434, 0x0, 0, 0x0, 0), /* MX35_PAD_SD22__EMI_DRAM_D_22 */ - [91] = IMX_PIN_REG(MX35_PAD_SD23, 0x438, 0x0, 0, 0x0, 0), /* MX35_PAD_SD23__EMI_DRAM_D_23 */ - [92] = IMX_PIN_REG(MX35_PAD_SD24, 0x43c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD24__EMI_DRAM_D_24 */ - [93] = IMX_PIN_REG(MX35_PAD_SD25, 0x440, 0x0, 0, 0x0, 0), /* MX35_PAD_SD25__EMI_DRAM_D_25 */ - [94] = IMX_PIN_REG(MX35_PAD_SD26, 0x444, 0x0, 0, 0x0, 0), /* MX35_PAD_SD26__EMI_DRAM_D_26 */ - [95] = IMX_PIN_REG(MX35_PAD_SD27, 0x448, 0x0, 0, 0x0, 0), /* MX35_PAD_SD27__EMI_DRAM_D_27 */ - [96] = IMX_PIN_REG(MX35_PAD_SD28, 0x44c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD28__EMI_DRAM_D_28 */ - [97] = IMX_PIN_REG(MX35_PAD_SD29, 0x450, 0x0, 0, 0x0, 0), /* MX35_PAD_SD29__EMI_DRAM_D_29 */ - [98] = IMX_PIN_REG(MX35_PAD_SD30, 0x454, 0x0, 0, 0x0, 0), /* MX35_PAD_SD30__EMI_DRAM_D_30 */ - [99] = IMX_PIN_REG(MX35_PAD_SD31, 0x458, 0x0, 0, 0x0, 0), /* MX35_PAD_SD31__EMI_DRAM_D_31 */ - [100] = IMX_PIN_REG(MX35_PAD_DQM0, 0x45c, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM0__EMI_DRAM_DQM_0 */ - [101] = IMX_PIN_REG(MX35_PAD_DQM1, 0x460, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM1__EMI_DRAM_DQM_1 */ - [102] = IMX_PIN_REG(MX35_PAD_DQM2, 0x464, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM2__EMI_DRAM_DQM_2 */ - [103] = IMX_PIN_REG(MX35_PAD_DQM3, 0x468, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM3__EMI_DRAM_DQM_3 */ - [104] = IMX_PIN_REG(MX35_PAD_EB0, 0x46c, 0x094, 0, 0x0, 0), /* MX35_PAD_EB0__EMI_EIM_EB0_B */ - [105] = IMX_PIN_REG(MX35_PAD_EB1, 0x470, 0x098, 0, 0x0, 0), /* MX35_PAD_EB1__EMI_EIM_EB1_B */ - [106] = IMX_PIN_REG(MX35_PAD_OE, 0x474, 0x09c, 0, 0x0, 0), /* MX35_PAD_OE__EMI_EIM_OE */ - [107] = IMX_PIN_REG(MX35_PAD_CS0, 0x478, 0x0a0, 0, 0x0, 0), /* MX35_PAD_CS0__EMI_EIM_CS0 */ - [108] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 0, 0x0, 0), /* MX35_PAD_CS1__EMI_EIM_CS1 */ - [109] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 3, 0x0, 0), /* MX35_PAD_CS1__EMI_NANDF_CE3 */ - [110] = IMX_PIN_REG(MX35_PAD_CS2, 0x480, 0x0a8, 0, 0x0, 0), /* MX35_PAD_CS2__EMI_EIM_CS2 */ - [111] = IMX_PIN_REG(MX35_PAD_CS3, 0x484, 0x0ac, 0, 0x0, 0), /* MX35_PAD_CS3__EMI_EIM_CS3 */ - [112] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 0, 0x0, 0), /* MX35_PAD_CS4__EMI_EIM_CS4 */ - [113] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 1, 0x800, 0), /* MX35_PAD_CS4__EMI_DTACK_B */ - [114] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 3, 0x0, 0), /* MX35_PAD_CS4__EMI_NANDF_CE1 */ - [115] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 5, 0x83c, 0), /* MX35_PAD_CS4__GPIO1_20 */ - [116] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 0, 0x0, 0), /* MX35_PAD_CS5__EMI_EIM_CS5 */ - [117] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 1, 0x7f8, 0), /* MX35_PAD_CS5__CSPI2_SS2 */ - [118] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 2, 0x7d8, 1), /* MX35_PAD_CS5__CSPI1_SS2 */ - [119] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 3, 0x0, 0), /* MX35_PAD_CS5__EMI_NANDF_CE2 */ - [120] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 5, 0x840, 0), /* MX35_PAD_CS5__GPIO1_21 */ - [121] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 0, 0x0, 0), /* MX35_PAD_NF_CE0__EMI_NANDF_CE0 */ - [122] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 5, 0x844, 0), /* MX35_PAD_NF_CE0__GPIO1_22 */ - [123] = IMX_PIN_REG(MX35_PAD_ECB, 0x494, 0x0, 0, 0x0, 0), /* MX35_PAD_ECB__EMI_EIM_ECB */ - [124] = IMX_PIN_REG(MX35_PAD_LBA, 0x498, 0x0bc, 0, 0x0, 0), /* MX35_PAD_LBA__EMI_EIM_LBA */ - [125] = IMX_PIN_REG(MX35_PAD_BCLK, 0x49c, 0x0c0, 0, 0x0, 0), /* MX35_PAD_BCLK__EMI_EIM_BCLK */ - [126] = IMX_PIN_REG(MX35_PAD_RW, 0x4a0, 0x0c4, 0, 0x0, 0), /* MX35_PAD_RW__EMI_EIM_RW */ - [127] = IMX_PIN_REG(MX35_PAD_RAS, 0x4a4, 0x0, 0, 0x0, 0), /* MX35_PAD_RAS__EMI_DRAM_RAS */ - [128] = IMX_PIN_REG(MX35_PAD_CAS, 0x4a8, 0x0, 0, 0x0, 0), /* MX35_PAD_CAS__EMI_DRAM_CAS */ - [129] = IMX_PIN_REG(MX35_PAD_SDWE, 0x4ac, 0x0, 0, 0x0, 0), /* MX35_PAD_SDWE__EMI_DRAM_SDWE */ - [130] = IMX_PIN_REG(MX35_PAD_SDCKE0, 0x4b0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 */ - [131] = IMX_PIN_REG(MX35_PAD_SDCKE1, 0x4b4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 */ - [132] = IMX_PIN_REG(MX35_PAD_SDCLK, 0x4b8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCLK__EMI_DRAM_SDCLK */ - [133] = IMX_PIN_REG(MX35_PAD_SDQS0, 0x4bc, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 */ - [134] = IMX_PIN_REG(MX35_PAD_SDQS1, 0x4c0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 */ - [135] = IMX_PIN_REG(MX35_PAD_SDQS2, 0x4c4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 */ - [136] = IMX_PIN_REG(MX35_PAD_SDQS3, 0x4c8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 */ - [137] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 0, 0x0, 0), /* MX35_PAD_NFWE_B__EMI_NANDF_WE_B */ - [138] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 1, 0x9d8, 0), /* MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 */ - [139] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 2, 0x924, 0), /* MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC */ - [140] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 5, 0x88c, 0), /* MX35_PAD_NFWE_B__GPIO2_18 */ - [141] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 7, 0x0, 0), /* MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 */ - [142] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 0, 0x0, 0), /* MX35_PAD_NFRE_B__EMI_NANDF_RE_B */ - [143] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 1, 0x9ec, 0), /* MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR */ - [144] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 2, 0x0, 0), /* MX35_PAD_NFRE_B__IPU_DISPB_BCLK */ - [145] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 5, 0x890, 0), /* MX35_PAD_NFRE_B__GPIO2_19 */ - [146] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 7, 0x0, 0), /* MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 */ - [147] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 0, 0x0, 0), /* MX35_PAD_NFALE__EMI_NANDF_ALE */ - [148] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 1, 0x0, 0), /* MX35_PAD_NFALE__USB_TOP_USBH2_STP */ - [149] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 2, 0x0, 0), /* MX35_PAD_NFALE__IPU_DISPB_CS0 */ - [150] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 5, 0x898, 0), /* MX35_PAD_NFALE__GPIO2_20 */ - [151] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 7, 0x0, 0), /* MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 */ - [152] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 0, 0x0, 0), /* MX35_PAD_NFCLE__EMI_NANDF_CLE */ - [153] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 1, 0x9f0, 0), /* MX35_PAD_NFCLE__USB_TOP_USBH2_NXT */ - [154] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 2, 0x0, 0), /* MX35_PAD_NFCLE__IPU_DISPB_PAR_RS */ - [155] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 5, 0x89c, 0), /* MX35_PAD_NFCLE__GPIO2_21 */ - [156] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 7, 0x0, 0), /* MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 */ - [157] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 0, 0x0, 0), /* MX35_PAD_NFWP_B__EMI_NANDF_WP_B */ - [158] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 1, 0x9e8, 0), /* MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 */ - [159] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 2, 0x0, 0), /* MX35_PAD_NFWP_B__IPU_DISPB_WR */ - [160] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 5, 0x8a0, 0), /* MX35_PAD_NFWP_B__GPIO2_22 */ - [161] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 7, 0x0, 0), /* MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL */ - [162] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 0, 0x0, 0), /* MX35_PAD_NFRB__EMI_NANDF_RB */ - [163] = |