diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2016-11-16 20:50:49 +0100 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2016-11-16 20:50:49 +0100 |
commit | d278dae88428d61623590269e5d782264f2ac2f8 (patch) | |
tree | 4bfe02da68c4f93246fac775da3d3d91940590fd /drivers/pinctrl | |
parent | 688daf234fa3b61019efa2beea544a3e173a251d (diff) | |
parent | 1fa1522f61f1fa53b2518c82bb3c667161836e10 (diff) |
Merge tag 'sh-pfc-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.10 (take two)
- DU and EtherAVB pin groups for R-Car M3-W,
- Bias handling cleanups and bug fixes,
- Drive-strength for non-GPIO pins for R-Car H3,
- EtherAVB MDIO & MII, and QSPI pin groups for R-Car H3.
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r-- | drivers/pinctrl/sh-pfc/core.c | 15 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/core.h | 4 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 342 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 616 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 188 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/pinctrl.c | 3 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/sh_pfc.h | 14 |
7 files changed, 816 insertions, 366 deletions
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index f3a8897d4e8f..cf80ce1dd7ce 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -389,6 +389,21 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) return 0; } +const struct sh_pfc_bias_info * +sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, + unsigned int num, unsigned int pin) +{ + unsigned int i; + + for (i = 0; i < num; i++) + if (info[i].pin == pin) + return &info[i]; + + WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); + + return NULL; +} + static int sh_pfc_init_ranges(struct sh_pfc *pfc) { struct sh_pfc_pin_range *range; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 0bbdea5849f4..6d598dd63720 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -33,4 +33,8 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); +const struct sh_pfc_bias_info * +sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, + unsigned int num, unsigned int pin); + #endif /* __SH_PFC_CORE_H__ */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index 18ef7042b3d1..c3af9ebee4af 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -24,6 +24,7 @@ #include <linux/kernel.h> #include <linux/pinctrl/pinconf-generic.h> +#include "core.h" #include "sh_pfc.h" #define PORT_GP_PUP_1(bank, pin, fn, sfx) \ @@ -2918,183 +2919,182 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define PUPR4 0x110 #define PUPR5 0x114 -static const struct { - u16 reg : 11; - u16 bit : 5; -} pullups[] = { - [RCAR_GP_PIN(0, 6)] = { PUPR0, 0 }, /* A0 */ - [RCAR_GP_PIN(0, 7)] = { PUPR0, 1 }, /* A1 */ - [RCAR_GP_PIN(0, 8)] = { PUPR0, 2 }, /* A2 */ - [RCAR_GP_PIN(0, 9)] = { PUPR0, 3 }, /* A3 */ - [RCAR_GP_PIN(0, 10)] = { PUPR0, 4 }, /* A4 */ - [RCAR_GP_PIN(0, 11)] = { PUPR0, 5 }, /* A5 */ - [RCAR_GP_PIN(0, 12)] = { PUPR0, 6 }, /* A6 */ - [RCAR_GP_PIN(0, 13)] = { PUPR0, 7 }, /* A7 */ - [RCAR_GP_PIN(0, 14)] = { PUPR0, 8 }, /* A8 */ - [RCAR_GP_PIN(0, 15)] = { PUPR0, 9 }, /* A9 */ - [RCAR_GP_PIN(0, 16)] = { PUPR0, 10 }, /* A10 */ - [RCAR_GP_PIN(0, 17)] = { PUPR0, 11 }, /* A11 */ - [RCAR_GP_PIN(0, 18)] = { PUPR0, 12 }, /* A12 */ - [RCAR_GP_PIN(0, 19)] = { PUPR0, 13 }, /* A13 */ - [RCAR_GP_PIN(0, 20)] = { PUPR0, 14 }, /* A14 */ - [RCAR_GP_PIN(0, 21)] = { PUPR0, 15 }, /* A15 */ - [RCAR_GP_PIN(0, 22)] = { PUPR0, 16 }, /* A16 */ - [RCAR_GP_PIN(0, 23)] = { PUPR0, 17 }, /* A17 */ - [RCAR_GP_PIN(0, 24)] = { PUPR0, 18 }, /* A18 */ - [RCAR_GP_PIN(0, 25)] = { PUPR0, 19 }, /* A19 */ - [RCAR_GP_PIN(0, 26)] = { PUPR0, 20 }, /* A20 */ - [RCAR_GP_PIN(0, 27)] = { PUPR0, 21 }, /* A21 */ - [RCAR_GP_PIN(0, 28)] = { PUPR0, 22 }, /* A22 */ - [RCAR_GP_PIN(0, 29)] = { PUPR0, 23 }, /* A23 */ - [RCAR_GP_PIN(0, 30)] = { PUPR0, 24 }, /* A24 */ - [RCAR_GP_PIN(0, 31)] = { PUPR0, 25 }, /* A25 */ - [RCAR_GP_PIN(1, 3)] = { PUPR0, 26 }, /* /EX_CS0 */ - [RCAR_GP_PIN(1, 4)] = { PUPR0, 27 }, /* /EX_CS1 */ - [RCAR_GP_PIN(1, 5)] = { PUPR0, 28 }, /* /EX_CS2 */ - [RCAR_GP_PIN(1, 6)] = { PUPR0, 29 }, /* /EX_CS3 */ - [RCAR_GP_PIN(1, 7)] = { PUPR0, 30 }, /* /EX_CS4 */ - [RCAR_GP_PIN(1, 8)] = { PUPR0, 31 }, /* /EX_CS5 */ - - [RCAR_GP_PIN(0, 0)] = { PUPR1, 0 }, /* /PRESETOUT */ - [RCAR_GP_PIN(0, 5)] = { PUPR1, 1 }, /* /BS */ - [RCAR_GP_PIN(1, 0)] = { PUPR1, 2 }, /* RD//WR */ - [RCAR_GP_PIN(1, 1)] = { PUPR1, 3 }, /* /WE0 */ - [RCAR_GP_PIN(1, 2)] = { PUPR1, 4 }, /* /WE1 */ - [RCAR_GP_PIN(1, 11)] = { PUPR1, 5 }, /* EX_WAIT0 */ - [RCAR_GP_PIN(1, 9)] = { PUPR1, 6 }, /* DREQ0 */ - [RCAR_GP_PIN(1, 10)] = { PUPR1, 7 }, /* DACK0 */ - [RCAR_GP_PIN(1, 12)] = { PUPR1, 8 }, /* IRQ0 */ - [RCAR_GP_PIN(1, 13)] = { PUPR1, 9 }, /* IRQ1 */ - - [RCAR_GP_PIN(1, 22)] = { PUPR2, 0 }, /* DU0_DR0 */ - [RCAR_GP_PIN(1, 23)] = { PUPR2, 1 }, /* DU0_DR1 */ - [RCAR_GP_PIN(1, 24)] = { PUPR2, 2 }, /* DU0_DR2 */ - [RCAR_GP_PIN(1, 25)] = { PUPR2, 3 }, /* DU0_DR3 */ - [RCAR_GP_PIN(1, 26)] = { PUPR2, 4 }, /* DU0_DR4 */ - [RCAR_GP_PIN(1, 27)] = { PUPR2, 5 }, /* DU0_DR5 */ - [RCAR_GP_PIN(1, 28)] = { PUPR2, 6 }, /* DU0_DR6 */ - [RCAR_GP_PIN(1, 29)] = { PUPR2, 7 }, /* DU0_DR7 */ - [RCAR_GP_PIN(1, 30)] = { PUPR2, 8 }, /* DU0_DG0 */ - [RCAR_GP_PIN(1, 31)] = { PUPR2, 9 }, /* DU0_DG1 */ - [RCAR_GP_PIN(2, 0)] = { PUPR2, 10 }, /* DU0_DG2 */ - [RCAR_GP_PIN(2, 1)] = { PUPR2, 11 }, /* DU0_DG3 */ - [RCAR_GP_PIN(2, 2)] = { PUPR2, 12 }, /* DU0_DG4 */ - [RCAR_GP_PIN(2, 3)] = { PUPR2, 13 }, /* DU0_DG5 */ - [RCAR_GP_PIN(2, 4)] = { PUPR2, 14 }, /* DU0_DG6 */ - [RCAR_GP_PIN(2, 5)] = { PUPR2, 15 }, /* DU0_DG7 */ - [RCAR_GP_PIN(2, 6)] = { PUPR2, 16 }, /* DU0_DB0 */ - [RCAR_GP_PIN(2, 7)] = { PUPR2, 17 }, /* DU0_DB1 */ - [RCAR_GP_PIN(2, 8)] = { PUPR2, 18 }, /* DU0_DB2 */ - [RCAR_GP_PIN(2, 9)] = { PUPR2, 19 }, /* DU0_DB3 */ - [RCAR_GP_PIN(2, 10)] = { PUPR2, 20 }, /* DU0_DB4 */ - [RCAR_GP_PIN(2, 11)] = { PUPR2, 21 }, /* DU0_DB5 */ - [RCAR_GP_PIN(2, 12)] = { PUPR2, 22 }, /* DU0_DB6 */ - [RCAR_GP_PIN(2, 13)] = { PUPR2, 23 }, /* DU0_DB7 */ - [RCAR_GP_PIN(2, 14)] = { PUPR2, 24 }, /* DU0_DOTCLKIN */ - [RCAR_GP_PIN(2, 15)] = { PUPR2, 25 }, /* DU0_DOTCLKOUT0 */ - [RCAR_GP_PIN(2, 17)] = { PUPR2, 26 }, /* DU0_HSYNC */ - [RCAR_GP_PIN(2, 18)] = { PUPR2, 27 }, /* DU0_VSYNC */ - [RCAR_GP_PIN(2, 19)] = { PUPR2, 28 }, /* DU0_EXODDF */ - [RCAR_GP_PIN(2, 20)] = { PUPR2, 29 }, /* DU0_DISP */ - [RCAR_GP_PIN(2, 21)] = { PUPR2, 30 }, /* DU0_CDE */ - [RCAR_GP_PIN(2, 16)] = { PUPR2, 31 }, /* DU0_DOTCLKOUT1 */ - - [RCAR_GP_PIN(3, 24)] = { PUPR3, 0 }, /* VI0_CLK */ - [RCAR_GP_PIN(3, 25)] = { PUPR3, 1 }, /* VI0_CLKENB */ - [RCAR_GP_PIN(3, 26)] = { PUPR3, 2 }, /* VI0_FIELD */ - [RCAR_GP_PIN(3, 27)] = { PUPR3, 3 }, /* /VI0_HSYNC */ - [RCAR_GP_PIN(3, 28)] = { PUPR3, 4 }, /* /VI0_VSYNC */ - [RCAR_GP_PIN(3, 29)] = { PUPR3, 5 }, /* VI0_DATA0 */ - [RCAR_GP_PIN(3, 30)] = { PUPR3, 6 }, /* VI0_DATA1 */ - [RCAR_GP_PIN(3, 31)] = { PUPR3, 7 }, /* VI0_DATA2 */ - [RCAR_GP_PIN(4, 0)] = { PUPR3, 8 }, /* VI0_DATA3 */ - [RCAR_GP_PIN(4, 1)] = { PUPR3, 9 }, /* VI0_DATA4 */ - [RCAR_GP_PIN(4, 2)] = { PUPR3, 10 }, /* VI0_DATA5 */ - [RCAR_GP_PIN(4, 3)] = { PUPR3, 11 }, /* VI0_DATA6 */ - [RCAR_GP_PIN(4, 4)] = { PUPR3, 12 }, /* VI0_DATA7 */ - [RCAR_GP_PIN(4, 5)] = { PUPR3, 13 }, /* VI0_G2 */ - [RCAR_GP_PIN(4, 6)] = { PUPR3, 14 }, /* VI0_G3 */ - [RCAR_GP_PIN(4, 7)] = { PUPR3, 15 }, /* VI0_G4 */ - [RCAR_GP_PIN(4, 8)] = { PUPR3, 16 }, /* VI0_G5 */ - [RCAR_GP_PIN(4, 21)] = { PUPR3, 17 }, /* VI1_DATA12 */ - [RCAR_GP_PIN(4, 22)] = { PUPR3, 18 }, /* VI1_DATA13 */ - [RCAR_GP_PIN(4, 23)] = { PUPR3, 19 }, /* VI1_DATA14 */ - [RCAR_GP_PIN(4, 24)] = { PUPR3, 20 }, /* VI1_DATA15 */ - [RCAR_GP_PIN(4, 9)] = { PUPR3, 21 }, /* ETH_REF_CLK */ - [RCAR_GP_PIN(4, 10)] = { PUPR3, 22 }, /* ETH_TXD0 */ - [RCAR_GP_PIN(4, 11)] = { PUPR3, 23 }, /* ETH_TXD1 */ - [RCAR_GP_PIN(4, 12)] = { PUPR3, 24 }, /* ETH_CRS_DV */ - [RCAR_GP_PIN(4, 13)] = { PUPR3, 25 }, /* ETH_TX_EN */ - [RCAR_GP_PIN(4, 14)] = { PUPR3, 26 }, /* ETH_RX_ER */ - [RCAR_GP_PIN(4, 15)] = { PUPR3, 27 }, /* ETH_RXD0 */ - [RCAR_GP_PIN(4, 16)] = { PUPR3, 28 }, /* ETH_RXD1 */ - [RCAR_GP_PIN(4, 17)] = { PUPR3, 29 }, /* ETH_MDC */ - [RCAR_GP_PIN(4, 18)] = { PUPR3, 30 }, /* ETH_MDIO */ - [RCAR_GP_PIN(4, 19)] = { PUPR3, 31 }, /* ETH_LINK */ - - [RCAR_GP_PIN(3, 6)] = { PUPR4, 0 }, /* SSI_SCK012 */ - [RCAR_GP_PIN(3, 7)] = { PUPR4, 1 }, /* SSI_WS012 */ - [RCAR_GP_PIN(3, 10)] = { PUPR4, 2 }, /* SSI_SDATA0 */ - [RCAR_GP_PIN(3, 9)] = { PUPR4, 3 }, /* SSI_SDATA1 */ - [RCAR_GP_PIN(3, 8)] = { PUPR4, 4 }, /* SSI_SDATA2 */ - [RCAR_GP_PIN(3, 2)] = { PUPR4, 5 }, /* SSI_SCK34 */ - [RCAR_GP_PIN(3, 3)] = { PUPR4, 6 }, /* SSI_WS34 */ - [RCAR_GP_PIN(3, 5)] = { PUPR4, 7 }, /* SSI_SDATA3 */ - [RCAR_GP_PIN(3, 4)] = { PUPR4, 8 }, /* SSI_SDATA4 */ - [RCAR_GP_PIN(2, 31)] = { PUPR4, 9 }, /* SSI_SCK5 */ - [RCAR_GP_PIN(3, 0)] = { PUPR4, 10 }, /* SSI_WS5 */ - [RCAR_GP_PIN(3, 1)] = { PUPR4, 11 }, /* SSI_SDATA5 */ - [RCAR_GP_PIN(2, 28)] = { PUPR4, 12 }, /* SSI_SCK6 */ - [RCAR_GP_PIN(2, 29)] = { PUPR4, 13 }, /* SSI_WS6 */ - [RCAR_GP_PIN(2, 30)] = { PUPR4, 14 }, /* SSI_SDATA6 */ - [RCAR_GP_PIN(2, 24)] = { PUPR4, 15 }, /* SSI_SCK78 */ - [RCAR_GP_PIN(2, 25)] = { PUPR4, 16 }, /* SSI_WS78 */ - [RCAR_GP_PIN(2, 27)] = { PUPR4, 17 }, /* SSI_SDATA7 */ - [RCAR_GP_PIN(2, 26)] = { PUPR4, 18 }, /* SSI_SDATA8 */ - [RCAR_GP_PIN(3, 23)] = { PUPR4, 19 }, /* TCLK0 */ - [RCAR_GP_PIN(3, 11)] = { PUPR4, 20 }, /* SD0_CLK */ - [RCAR_GP_PIN(3, 12)] = { PUPR4, 21 }, /* SD0_CMD */ - [RCAR_GP_PIN(3, 13)] = { PUPR4, 22 }, /* SD0_DAT0 */ - [RCAR_GP_PIN(3, 14)] = { PUPR4, 23 }, /* SD0_DAT1 */ - [RCAR_GP_PIN(3, 15)] = { PUPR4, 24 }, /* SD0_DAT2 */ - [RCAR_GP_PIN(3, 16)] = { PUPR4, 25 }, /* SD0_DAT3 */ - [RCAR_GP_PIN(3, 17)] = { PUPR4, 26 }, /* SD0_CD */ - [RCAR_GP_PIN(3, 18)] = { PUPR4, 27 }, /* SD0_WP */ - [RCAR_GP_PIN(2, 22)] = { PUPR4, 28 }, /* AUDIO_CLKA */ - [RCAR_GP_PIN(2, 23)] = { PUPR4, 29 }, /* AUDIO_CLKB */ - [RCAR_GP_PIN(1, 14)] = { PUPR4, 30 }, /* IRQ2 */ - [RCAR_GP_PIN(1, 15)] = { PUPR4, 31 }, /* IRQ3 */ - - [RCAR_GP_PIN(0, 1)] = { PUPR5, 0 }, /* PENC0 */ - [RCAR_GP_PIN(0, 2)] = { PUPR5, 1 }, /* PENC1 */ - [RCAR_GP_PIN(0, 3)] = { PUPR5, 2 }, /* USB_OVC0 */ - [RCAR_GP_PIN(0, 4)] = { PUPR5, 3 }, /* USB_OVC1 */ - [RCAR_GP_PIN(1, 16)] = { PUPR5, 4 }, /* SCIF_CLK */ - [RCAR_GP_PIN(1, 17)] = { PUPR5, 5 }, /* TX0 */ - [RCAR_GP_PIN(1, 18)] = { PUPR5, 6 }, /* RX0 */ - [RCAR_GP_PIN(1, 19)] = { PUPR5, 7 }, /* SCK0 */ - [RCAR_GP_PIN(1, 20)] = { PUPR5, 8 }, /* /CTS0 */ - [RCAR_GP_PIN(1, 21)] = { PUPR5, 9 }, /* /RTS0 */ - [RCAR_GP_PIN(3, 19)] = { PUPR5, 10 }, /* HSPI_CLK0 */ - [RCAR_GP_PIN(3, 20)] = { PUPR5, 11 }, /* /HSPI_CS0 */ - [RCAR_GP_PIN(3, 21)] = { PUPR5, 12 }, /* HSPI_RX0 */ - [RCAR_GP_PIN(3, 22)] = { PUPR5, 13 }, /* HSPI_TX0 */ - [RCAR_GP_PIN(4, 20)] = { PUPR5, 14 }, /* ETH_MAGIC */ - [RCAR_GP_PIN(4, 25)] = { PUPR5, 15 }, /* AVS1 */ - [RCAR_GP_PIN(4, 26)] = { PUPR5, 16 }, /* AVS2 */ +static const struct sh_pfc_bias_info bias_info[] = { + { RCAR_GP_PIN(0, 6), PUPR0, 0 }, /* A0 */ + { RCAR_GP_PIN(0, 7), PUPR0, 1 }, /* A1 */ + { RCAR_GP_PIN(0, 8), PUPR0, 2 }, /* A2 */ + { RCAR_GP_PIN(0, 9), PUPR0, 3 }, /* A3 */ + { RCAR_GP_PIN(0, 10), PUPR0, 4 }, /* A4 */ + { RCAR_GP_PIN(0, 11), PUPR0, 5 }, /* A5 */ + { RCAR_GP_PIN(0, 12), PUPR0, 6 }, /* A6 */ + { RCAR_GP_PIN(0, 13), PUPR0, 7 }, /* A7 */ + { RCAR_GP_PIN(0, 14), PUPR0, 8 }, /* A8 */ + { RCAR_GP_PIN(0, 15), PUPR0, 9 }, /* A9 */ + { RCAR_GP_PIN(0, 16), PUPR0, 10 }, /* A10 */ + { RCAR_GP_PIN(0, 17), PUPR0, 11 }, /* A11 */ + { RCAR_GP_PIN(0, 18), PUPR0, 12 }, /* A12 */ + { RCAR_GP_PIN(0, 19), PUPR0, 13 }, /* A13 */ + { RCAR_GP_PIN(0, 20), PUPR0, 14 }, /* A14 */ + { RCAR_GP_PIN(0, 21), PUPR0, 15 }, /* A15 */ + { RCAR_GP_PIN(0, 22), PUPR0, 16 }, /* A16 */ + { RCAR_GP_PIN(0, 23), PUPR0, 17 }, /* A17 */ + { RCAR_GP_PIN(0, 24), PUPR0, 18 }, /* A18 */ + { RCAR_GP_PIN(0, 25), PUPR0, 19 }, /* A19 */ + { RCAR_GP_PIN(0, 26), PUPR0, 20 }, /* A20 */ + { RCAR_GP_PIN(0, 27), PUPR0, 21 }, /* A21 */ + { RCAR_GP_PIN(0, 28), PUPR0, 22 }, /* A22 */ + { RCAR_GP_PIN(0, 29), PUPR0, 23 }, /* A23 */ + { RCAR_GP_PIN(0, 30), PUPR0, 24 }, /* A24 */ + { RCAR_GP_PIN(0, 31), PUPR0, 25 }, /* A25 */ + { RCAR_GP_PIN(1, 3), PUPR0, 26 }, /* /EX_CS0 */ + { RCAR_GP_PIN(1, 4), PUPR0, 27 }, /* /EX_CS1 */ + { RCAR_GP_PIN(1, 5), PUPR0, 28 }, /* /EX_CS2 */ + { RCAR_GP_PIN(1, 6), PUPR0, 29 }, /* /EX_CS3 */ + { RCAR_GP_PIN(1, 7), PUPR0, 30 }, /* /EX_CS4 */ + { RCAR_GP_PIN(1, 8), PUPR0, 31 }, /* /EX_CS5 */ + + { RCAR_GP_PIN(0, 0), PUPR1, 0 }, /* /PRESETOUT */ + { RCAR_GP_PIN(0, 5), PUPR1, 1 }, /* /BS */ + { RCAR_GP_PIN(1, 0), PUPR1, 2 }, /* RD//WR */ + { RCAR_GP_PIN(1, 1), PUPR1, 3 }, /* /WE0 */ + { RCAR_GP_PIN(1, 2), PUPR1, 4 }, /* /WE1 */ + { RCAR_GP_PIN(1, 11), PUPR1, 5 }, /* EX_WAIT0 */ + { RCAR_GP_PIN(1, 9), PUPR1, 6 }, /* DREQ0 */ + { RCAR_GP_PIN(1, 10), PUPR1, 7 }, /* DACK0 */ + { RCAR_GP_PIN(1, 12), PUPR1, 8 }, /* IRQ0 */ + { RCAR_GP_PIN(1, 13), PUPR1, 9 }, /* IRQ1 */ + + { RCAR_GP_PIN(1, 22), PUPR2, 0 }, /* DU0_DR0 */ + { RCAR_GP_PIN(1, 23), PUPR2, 1 }, /* DU0_DR1 */ + { RCAR_GP_PIN(1, 24), PUPR2, 2 }, /* DU0_DR2 */ + { RCAR_GP_PIN(1, 25), PUPR2, 3 }, /* DU0_DR3 */ + { RCAR_GP_PIN(1, 26), PUPR2, 4 }, /* DU0_DR4 */ + { RCAR_GP_PIN(1, 27), PUPR2, 5 }, /* DU0_DR5 */ + { RCAR_GP_PIN(1, 28), PUPR2, 6 }, /* DU0_DR6 */ + { RCAR_GP_PIN(1, 29), PUPR2, 7 }, /* DU0_DR7 */ + { RCAR_GP_PIN(1, 30), PUPR2, 8 }, /* DU0_DG0 */ + { RCAR_GP_PIN(1, 31), PUPR2, 9 }, /* DU0_DG1 */ + { RCAR_GP_PIN(2, 0), PUPR2, 10 }, /* DU0_DG2 */ + { RCAR_GP_PIN(2, 1), PUPR2, 11 }, /* DU0_DG3 */ + { RCAR_GP_PIN(2, 2), PUPR2, 12 }, /* DU0_DG4 */ + { RCAR_GP_PIN(2, 3), PUPR2, 13 }, /* DU0_DG5 */ + { RCAR_GP_PIN(2, 4), PUPR2, 14 }, /* DU0_DG6 */ + { RCAR_GP_PIN(2, 5), PUPR2, 15 }, /* DU0_DG7 */ + { RCAR_GP_PIN(2, 6), PUPR2, 16 }, /* DU0_DB0 */ + { RCAR_GP_PIN(2, 7), PUPR2, 17 }, /* DU0_DB1 */ + { RCAR_GP_PIN(2, 8), PUPR2, 18 }, /* DU0_DB2 */ + { RCAR_GP_PIN(2, 9), PUPR2, 19 }, /* DU0_DB3 */ + { RCAR_GP_PIN(2, 10), PUPR2, 20 }, /* DU0_DB4 */ + { RCAR_GP_PIN(2, 11), PUPR2, 21 }, /* DU0_DB5 */ + { RCAR_GP_PIN(2, 12), PUPR2, 22 }, /* DU0_DB6 */ + { RCAR_GP_PIN(2, 13), PUPR2, 23 }, /* DU0_DB7 */ + { RCAR_GP_PIN(2, 14), PUPR2, 24 }, /* DU0_DOTCLKIN */ + { RCAR_GP_PIN(2, 15), PUPR2, 25 }, /* DU0_DOTCLKOUT0 */ + { RCAR_GP_PIN(2, 17), PUPR2, 26 }, /* DU0_HSYNC */ + { RCAR_GP_PIN(2, 18), PUPR2, 27 }, /* DU0_VSYNC */ + { RCAR_GP_PIN(2, 19), PUPR2, 28 }, /* DU0_EXODDF */ + { RCAR_GP_PIN(2, 20), PUPR2, 29 }, /* DU0_DISP */ + { RCAR_GP_PIN(2, 21), PUPR2, 30 }, /* DU0_CDE */ + { RCAR_GP_PIN(2, 16), PUPR2, 31 }, /* DU0_DOTCLKOUT1 */ + + { RCAR_GP_PIN(3, 24), PUPR3, 0 }, /* VI0_CLK */ + { RCAR_GP_PIN(3, 25), PUPR3, 1 }, /* VI0_CLKENB */ + { RCAR_GP_PIN(3, 26), PUPR3, 2 }, /* VI0_FIELD */ + { RCAR_GP_PIN(3, 27), PUPR3, 3 }, /* /VI0_HSYNC */ + { RCAR_GP_PIN(3, 28), PUPR3, 4 }, /* /VI0_VSYNC */ + { RCAR_GP_PIN(3, 29), PUPR3, 5 }, /* VI0_DATA0 */ + { RCAR_GP_PIN(3, 30), PUPR3, 6 }, /* VI0_DATA1 */ + { RCAR_GP_PIN(3, 31), PUPR3, 7 }, /* VI0_DATA2 */ + { RCAR_GP_PIN(4, 0), PUPR3, 8 }, /* VI0_DATA3 */ + { RCAR_GP_PIN(4, 1), PUPR3, 9 }, /* VI0_DATA4 */ + { RCAR_GP_PIN(4, 2), PUPR3, 10 }, /* VI0_DATA5 */ + { RCAR_GP_PIN(4, 3), PUPR3, 11 }, /* VI0_DATA6 */ + { RCAR_GP_PIN(4, 4), PUPR3, 12 }, /* VI0_DATA7 */ + { RCAR_GP_PIN(4, 5), PUPR3, 13 }, /* VI0_G2 */ + { RCAR_GP_PIN(4, 6), PUPR3, 14 }, /* VI0_G3 */ + { RCAR_GP_PIN(4, 7), PUPR3, 15 }, /* VI0_G4 */ + { RCAR_GP_PIN(4, 8), PUPR3, 16 }, /* VI0_G5 */ + { RCAR_GP_PIN(4, 21), PUPR3, 17 }, /* VI1_DATA12 */ + { RCAR_GP_PIN(4, 22), PUPR3, 18 }, /* VI1_DATA13 */ + { RCAR_GP_PIN(4, 23), PUPR3, 19 }, /* VI1_DATA14 */ + { RCAR_GP_PIN(4, 24), PUPR3, 20 }, /* VI1_DATA15 */ + { RCAR_GP_PIN(4, 9), PUPR3, 21 }, /* ETH_REF_CLK */ + { RCAR_GP_PIN(4, 10), PUPR3, 22 }, /* ETH_TXD0 */ + { RCAR_GP_PIN(4, 11), PUPR3, 23 }, /* ETH_TXD1 */ + { RCAR_GP_PIN(4, 12), PUPR3, 24 }, /* ETH_CRS_DV */ + { RCAR_GP_PIN(4, 13), PUPR3, 25 }, /* ETH_TX_EN */ + { RCAR_GP_PIN(4, 14), PUPR3, 26 }, /* ETH_RX_ER */ + { RCAR_GP_PIN(4, 15), PUPR3, 27 }, /* ETH_RXD0 */ + { RCAR_GP_PIN(4, 16), PUPR3, 28 }, /* ETH_RXD1 */ + { RCAR_GP_PIN(4, 17), PUPR3, 29 }, /* ETH_MDC */ + { RCAR_GP_PIN(4, 18), PUPR3, 30 }, /* ETH_MDIO */ + { RCAR_GP_PIN(4, 19), PUPR3, 31 }, /* ETH_LINK */ + + { RCAR_GP_PIN(3, 6), PUPR4, 0 }, /* SSI_SCK012 */ + { RCAR_GP_PIN(3, 7), PUPR4, 1 }, /* SSI_WS012 */ + { RCAR_GP_PIN(3, 10), PUPR4, 2 }, /* SSI_SDATA0 */ + { RCAR_GP_PIN(3, 9), PUPR4, 3 }, /* SSI_SDATA1 */ + { RCAR_GP_PIN(3, 8), PUPR4, 4 }, /* SSI_SDATA2 */ + { RCAR_GP_PIN(3, 2), PUPR4, 5 }, /* SSI_SCK34 */ + { RCAR_GP_PIN(3, 3), PUPR4, 6 }, /* SSI_WS34 */ + { RCAR_GP_PIN(3, 5), PUPR4, 7 }, /* SSI_SDATA3 */ + { RCAR_GP_PIN(3, 4), PUPR4, 8 }, /* SSI_SDATA4 */ + { RCAR_GP_PIN(2, 31), PUPR4, 9 }, /* SSI_SCK5 */ + { RCAR_GP_PIN(3, 0), PUPR4, 10 }, /* SSI_WS5 */ + { RCAR_GP_PIN(3, 1), PUPR4, 11 }, /* SSI_SDATA5 */ + { RCAR_GP_PIN(2, 28), PUPR4, 12 }, /* SSI_SCK6 */ + { RCAR_GP_PIN(2, 29), PUPR4, 13 }, /* SSI_WS6 */ + { RCAR_GP_PIN(2, 30), PUPR4, 14 }, /* SSI_SDATA6 */ + { RCAR_GP_PIN(2, 24), PUPR4, 15 }, /* SSI_SCK78 */ + { RCAR_GP_PIN(2, 25), PUPR4, 16 }, /* SSI_WS78 */ + { RCAR_GP_PIN(2, 27), PUPR4, 17 }, /* SSI_SDATA7 */ + { RCAR_GP_PIN(2, 26), PUPR4, 18 }, /* SSI_SDATA8 */ + { RCAR_GP_PIN(3, 23), PUPR4, 19 }, /* TCLK0 */ + { RCAR_GP_PIN(3, 11), PUPR4, 20 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 12), PUPR4, 21 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 13), PUPR4, 22 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 14), PUPR4, 23 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 15), PUPR4, 24 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 16), PUPR4, 25 }, /* SD0_DAT3 */ + { RCAR_GP_PIN(3, 17), PUPR4, 26 }, /* SD0_CD */ + { RCAR_GP_PIN(3, 18), PUPR4, 27 }, /* SD0_WP */ + { RCAR_GP_PIN(2, 22), PUPR4, 28 }, /* AUDIO_CLKA */ + { RCAR_GP_PIN(2, 23), PUPR4, 29 }, /* AUDIO_CLKB */ + { RCAR_GP_PIN(1, 14), PUPR4, 30 }, /* IRQ2 */ + { RCAR_GP_PIN(1, 15), PUPR4, 31 }, /* IRQ3 */ + + { RCAR_GP_PIN(0, 1), PUPR5, 0 }, /* PENC0 */ + { RCAR_GP_PIN(0, 2), PUPR5, 1 }, /* PENC1 */ + { RCAR_GP_PIN(0, 3), PUPR5, 2 }, /* USB_OVC0 */ + { RCAR_GP_PIN(0, 4), PUPR5, 3 }, /* USB_OVC1 */ + { RCAR_GP_PIN(1, 16), PUPR5, 4 }, /* SCIF_CLK */ + { RCAR_GP_PIN(1, 17), PUPR5, 5 }, /* TX0 */ + { RCAR_GP_PIN(1, 18), PUPR5, 6 }, /* RX0 */ + { RCAR_GP_PIN(1, 19), PUPR5, 7 }, /* SCK0 */ + { RCAR_GP_PIN(1, 20), PUPR5, 8 }, /* /CTS0 */ + { RCAR_GP_PIN(1, 21), PUPR5, 9 }, /* /RTS0 */ + { RCAR_GP_PIN(3, 19), PUPR5, 10 }, /* HSPI_CLK0 */ + { RCAR_GP_PIN(3, 20), PUPR5, 11 }, /* /HSPI_CS0 */ + { RCAR_GP_PIN(3, 21), PUPR5, 12 }, /* HSPI_RX0 */ + { RCAR_GP_PIN(3, 22), PUPR5, 13 }, /* HSPI_TX0 */ + { RCAR_GP_PIN(4, 20), PUPR5, 14 }, /* ETH_MAGIC */ + { RCAR_GP_PIN(4, 25), PUPR5, 15 }, /* AVS1 */ + { RCAR_GP_PIN(4, 26), PUPR5, 16 }, /* AVS2 */ }; static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { + const struct sh_pfc_bias_info *info; void __iomem *addr; - if (WARN_ON_ONCE(!pullups[pin].reg)) + info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); + if (!info) return PIN_CONFIG_BIAS_DISABLE; - addr = pfc->windows->virt + pullups[pin].reg; + addr = pfc->windows->virt + info->reg; - if (ioread32(addr) & BIT(pullups[pin].bit)) + if (ioread32(addr) & BIT(info->bit)) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_DISABLE; @@ -3103,15 +3103,17 @@ static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { + const struct sh_pfc_bias_info *info; void __iomem *addr; u32 value; u32 bit; - if (WARN_ON_ONCE(!pullups[pin].reg)) + info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); + if (!info) return; - addr = pfc->windows->virt + pullups[pin].reg; - bit = BIT(pullups[pin].bit); + addr = pfc->windows->virt + info->reg; + bit = BIT(info->bit); value = ioread32(addr) & ~bit; if (bias == PIN_CONFIG_BIAS_PULL_UP) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 2e8cc2adbed7..135ed5cbeb44 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -523,6 +523,22 @@ MOD_SEL0_2_1 MOD_SEL1_2 \ MOD_SEL1_1 \ MOD_SEL1_0 MOD_SEL2_0 +/* + * These pins are not able to be muxed but have other properties + * that can be set, such as drive-strength or pull-up/pull-down enable. + */ +#define PINMUX_STATIC \ + FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ + FM(QSPI0_IO2) FM(QSPI0_IO3) \ + FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ + FM(QSPI1_IO2) FM(QSPI1_IO3) \ + FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ + FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ + FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ + FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ + FM(CLKOUT) FM(PRESETOUT) \ + FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ + FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) enum { PINMUX_RESERVED = 0, @@ -548,6 +564,7 @@ enum { PINMUX_GPSR PINMUX_IPSR PINMUX_MOD_SELS + PINMUX_STATIC PINMUX_MARK_END, #undef F_ #undef FM @@ -1412,10 +1429,78 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1), PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3), + +/* + * Static pins can not be muxed between different functions but + * still needs a mark entry in the pinmux list. Add each static + * pin to the list without an associated function. The sh-pfc + * core will do the right thing and skip trying to mux then pin + * while still applying configuration to it + */ +#define FM(x) PINMUX_DATA(x##_MARK, 0), + PINMUX_STATIC +#undef FM }; +/* + * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs. + * Physical layout rows: A - AW, cols: 1 - 39. + */ +#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) +#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) +#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + + /* + * Pins not associated with a GPIO port. + * + * The pin positions are different between different r8a7795 + * packages, all that is needed for the pfc driver is a unique + * number for each pin. To this end use the pin layout from + * R-Car H3SiP to calculate a unique number for each pin. + */ + SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), }; /* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1563,11 +1648,33 @@ static const unsigned int avb_phy_int_mux[] = { AVB_PHY_INT_MARK, }; static const unsigned int avb_mdc_pins[] = { - /* AVB_MDC */ - RCAR_GP_PIN(2, 9), + /* AVB_MDC, AVB_MDIO */ + RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), }; static const unsigned int avb_mdc_mux[] = { - AVB_MDC_MARK, + AVB_MDC_MARK, AVB_MDIO_MARK, +}; +static const unsigned int avb_mii_pins[] = { + /* + * AVB_TX_CTL, AVB_TXC, AVB_TD0, + * AVB_TD1, AVB_TD2, AVB_TD3, + * AVB_RX_CTL, AVB_RXC, AVB_RD0, + * AVB_RD1, AVB_RD2, AVB_RD3, + * AVB_TXCREFCLK + */ + PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), + PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), + PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), + PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), + PIN_NUMBER('A', 12), + +}; +static const unsigned int avb_mii_mux[] = { + AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, + AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, + AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, + AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, + AVB_TXCREFCLK_MARK, }; static const unsigned int avb_avtp_pps_pins[] = { /* AVB_AVTP_PPS */ @@ -3613,6 +3720,55 @@ static const unsigned int usb2_mux[] = { USB2_PWEN_MARK, USB2_OVC_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */ + PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), + PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + PIN_NUMBER('V', 3), PIN_NUMBER('V', 5), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */ + PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), + PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), @@ -3635,6 +3791,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), SH_PFC_PIN_GROUP(avb_mdc), + SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_avtp_match_a), SH_PFC_PIN_GROUP(avb_avtp_capture_a), @@ -3912,6 +4069,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), }; static const char * const audio_clk_groups[] = { @@ -3939,6 +4102,7 @@ static const char * const avb_groups[] = { "avb_magic", "avb_phy_int", "avb_mdc", + "avb_mii", "avb_avtp_pps", "avb_avtp_match_a", "avb_avtp_capture_a", @@ -4356,6 +4520,18 @@ static const char * const usb2_groups[] = { "usb2", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), @@ -4405,6 +4581,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -4962,10 +5140,45 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { }; static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { + { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ + { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ + { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ + { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ + { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ + { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { + { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ + { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ + { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ + { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ + { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ + { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ + { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { + { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ + { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ + { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ + { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ + { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ + { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ + { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ + { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ + { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ + { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ + { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ @@ -5008,6 +5221,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ } }, { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { + { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */ { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ @@ -5018,6 +5232,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ + { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ @@ -5036,20 +5251,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */ + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */ + { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { + { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */ + { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */ + { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */ + { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ + { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ @@ -5118,6 +5343,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ + { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { @@ -5188,206 +5414,206 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc #define PU5 0x14 #define PU6 0x18 -static const struct { - u16 reg : 11; - u16 bit : 5; -} pullups[] = { - [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */ - [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */ - [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */ - - [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */ - [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */ - [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */ - [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */ - [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */ - [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */ - [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */ - [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */ - [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */ - [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */ - [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */ - [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */ - [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */ - [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */ - [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */ - [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */ - [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */ - [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */ - [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */ - [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */ - [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */ - [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */ - [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */ - [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, |