diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2019-04-04 22:20:59 +0700 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2019-04-04 22:20:59 +0700 |
commit | 3846e6a06160053d7631594fa60fd55dff286b54 (patch) | |
tree | 4522a9d1293434b4b7765de33f26c3050a8d807e /drivers/pinctrl | |
parent | d1ff8d07166b7388901137c551a4118054ca4760 (diff) | |
parent | 0a042b355e60269ad30725b5b5ca68fc5371a8df (diff) |
Merge tag 'sh-pfc-for-v5.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v5.2
- Add HSCIF (serial) pin groups on R-Car H1,
- Add I2C[035] pin groups on R-Car M3-N,
- Add CANFD pin groups on RZ/G2M and RZ/G2E,
- Retain SDHI/MMC clock return path delay configuration across
suspend/resume on R-Car Gen3,
- More validation of pinmux tables at build and runtime, including
compile-test coverage of all drivers,
- Small fixes, improvements, and cleanups.
Diffstat (limited to 'drivers/pinctrl')
37 files changed, 2854 insertions, 2419 deletions
diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index 9cfe9d0520ac..021e37b7689e 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -620,14 +620,7 @@ static void rza1_pin_reset(struct rza1_port *port, unsigned int pin) static inline int rza1_pin_get_direction(struct rza1_port *port, unsigned int pin) { - unsigned long irqflags; - int input; - - spin_lock_irqsave(&port->lock, irqflags); - input = rza1_get_bit(port, RZA1_PM_REG, pin); - spin_unlock_irqrestore(&port->lock, irqflags); - - return !!input; + return !!rza1_get_bit(port, RZA1_PM_REG, pin); } /** @@ -671,14 +664,7 @@ static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin, static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin) { - unsigned long irqflags; - int val; - - spin_lock_irqsave(&port->lock, irqflags); - val = rza1_get_bit(port, RZA1_PPR_REG, pin); - spin_unlock_irqrestore(&port->lock, irqflags); - - return val; + return rza1_get_bit(port, RZA1_PPR_REG, pin); } /** diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index e941ba60d4b7..2dd716b016a3 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -3,201 +3,183 @@ # Renesas SH and SH Mobile PINCTRL drivers # -if ARCH_RENESAS || SUPERH - config PINCTRL_SH_PFC + bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH) + default y if ARCH_RENESAS || SUPERH select PINMUX select PINCONF select GENERIC_PINCONF - def_bool y + select PINCTRL_PFC_EMEV2 if ARCH_EMEV2 + select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4 + select PINCTRL_PFC_R8A7740 if ARCH_R8A7740 + select PINCTRL_PFC_R8A7743 if ARCH_R8A7743 + select PINCTRL_PFC_R8A7744 if ARCH_R8A7744 + select PINCTRL_PFC_R8A7745 if ARCH_R8A7745 + select PINCTRL_PFC_R8A77470 if ARCH_R8A77470 + select PINCTRL_PFC_R8A774A1 if ARCH_R8A774A1 + select PINCTRL_PFC_R8A774C0 if ARCH_R8A774C0 + select PINCTRL_PFC_R8A7778 if ARCH_R8A7778 + select PINCTRL_PFC_R8A7779 if ARCH_R8A7779 + select PINCTRL_PFC_R8A7790 if ARCH_R8A7790 + select PINCTRL_PFC_R8A7791 if ARCH_R8A7791 + select PINCTRL_PFC_R8A7792 if ARCH_R8A7792 + select PINCTRL_PFC_R8A7793 if ARCH_R8A7793 + select PINCTRL_PFC_R8A7794 if ARCH_R8A7794 + select PINCTRL_PFC_R8A7795 if ARCH_R8A7795 + select PINCTRL_PFC_R8A7796 if ARCH_R8A7796 + select PINCTRL_PFC_R8A77965 if ARCH_R8A77965 + select PINCTRL_PFC_R8A77970 if ARCH_R8A77970 + select PINCTRL_PFC_R8A77980 if ARCH_R8A77980 + select PINCTRL_PFC_R8A77990 if ARCH_R8A77990 + select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 + select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 + select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 + select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 + select PINCTRL_PFC_SH73A0 if ARCH_SH73A0 + select PINCTRL_PFC_SH7720 if CPU_SUBTYPE_SH7720 + select PINCTRL_PFC_SH7722 if CPU_SUBTYPE_SH7722 + select PINCTRL_PFC_SH7723 if CPU_SUBTYPE_SH7723 + select PINCTRL_PFC_SH7724 if CPU_SUBTYPE_SH7724 + select PINCTRL_PFC_SH7734 if CPU_SUBTYPE_SH7734 + select PINCTRL_PFC_SH7757 if CPU_SUBTYPE_SH7757 + select PINCTRL_PFC_SH7785 if CPU_SUBTYPE_SH7785 + select PINCTRL_PFC_SH7786 if CPU_SUBTYPE_SH7786 + select PINCTRL_PFC_SHX3 if CPU_SUBTYPE_SHX3 help - This enables pin control drivers for SH and SH Mobile platforms + This enables pin control drivers for Renesas SuperH and ARM platforms config PINCTRL_SH_PFC_GPIO select GPIOLIB - select PINCTRL_SH_PFC bool help This enables pin control and GPIO drivers for SH/SH Mobile platforms +config PINCTRL_SH_FUNC_GPIO + select PINCTRL_SH_PFC_GPIO + bool + help + This enables legacy function GPIOs for SH platforms + config PINCTRL_PFC_EMEV2 - def_bool y - depends on ARCH_EMEV2 - select PINCTRL_SH_PFC + bool "Emma Mobile AV2 pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A73A4 - def_bool y - depends on ARCH_R8A73A4 + bool "R-Mobile APE6 pin control support" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_R8A7740 - def_bool y - depends on ARCH_R8A7740 + bool "R-Mobile A1 pin control support" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_R8A7743 - def_bool y - depends on ARCH_R8A7743 - select PINCTRL_SH_PFC + bool "RZ/G1M pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7744 - def_bool y - depends on ARCH_R8A7744 - select PINCTRL_SH_PFC + bool "RZ/G1N pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7745 - def_bool y - depends on ARCH_R8A7745 - select PINCTRL_SH_PFC + bool "RZ/G1E pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A77470 - def_bool y - depends on ARCH_R8A77470 - select PINCTRL_SH_PFC + bool "RZ/G1C pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A774A1 - def_bool y - depends on ARCH_R8A774A1 - select PINCTRL_SH_PFC + bool "RZ/G2M pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A774C0 - def_bool y - depends on ARCH_R8A774C0 - select PINCTRL_SH_PFC + bool "RZ/G2E pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7778 - def_bool y - depends on ARCH_R8A7778 - select PINCTRL_SH_PFC + bool "R-Car M1A pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7779 - def_bool y - depends on ARCH_R8A7779 - select PINCTRL_SH_PFC + bool "R-Car H1 pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7790 - def_bool y - depends on ARCH_R8A7790 - select PINCTRL_SH_PFC + bool "R-Car H2 pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7791 - def_bool y - depends on ARCH_R8A7791 - select PINCTRL_SH_PFC + bool "R-Car M2-W pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7792 - def_bool y - depends on ARCH_R8A7792 - select PINCTRL_SH_PFC + bool "R-Car V2H pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7793 - def_bool y - depends on ARCH_R8A7793 - select PINCTRL_SH_PFC + bool "R-Car M2-N pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7794 - def_bool y - depends on ARCH_R8A7794 - select PINCTRL_SH_PFC + bool "R-Car E2 pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7795 - def_bool y - depends on ARCH_R8A7795 - select PINCTRL_SH_PFC + bool "R-Car H3 pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A7796 - def_bool y - depends on ARCH_R8A7796 - select PINCTRL_SH_PFC + bool "R-Car M3-W pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A77965 - def_bool y - depends on ARCH_R8A77965 - select PINCTRL_SH_PFC + bool "R-Car M3-N pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A77970 - def_bool y - depends on ARCH_R8A77970 - select PINCTRL_SH_PFC + bool "R-Car V3M pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A77980 - def_bool y - depends on ARCH_R8A77980 - select PINCTRL_SH_PFC + bool "R-Car V3H pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A77990 - def_bool y - depends on ARCH_R8A77990 - select PINCTRL_SH_PFC + bool "R-Car E3 pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A77995 - def_bool y - depends on ARCH_R8A77995 - select PINCTRL_SH_PFC + bool "R-Car D3 pin control support" if COMPILE_TEST config PINCTRL_PFC_SH7203 - def_bool y - depends on CPU_SUBTYPE_SH7203 - select PINCTRL_SH_PFC_GPIO + bool "SH7203 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7264 - def_bool y - depends on CPU_SUBTYPE_SH7264 - select PINCTRL_SH_PFC_GPIO + bool "SH7264 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7269 - def_bool y - depends on CPU_SUBTYPE_SH7269 - select PINCTRL_SH_PFC_GPIO + bool "SH7269 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH73A0 - def_bool y - depends on ARCH_SH73A0 + bool "SH-Mobile AG5 pin control support" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO select REGULATOR config PINCTRL_PFC_SH7720 - def_bool y - depends on CPU_SUBTYPE_SH7720 - select PINCTRL_SH_PFC_GPIO + bool "SH7720 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7722 - def_bool y - depends on CPU_SUBTYPE_SH7722 - select PINCTRL_SH_PFC_GPIO + bool "SH7722 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7723 - def_bool y - depends on CPU_SUBTYPE_SH7723 - select PINCTRL_SH_PFC_GPIO + bool "SH-Mobile R2 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7724 - def_bool y - depends on CPU_SUBTYPE_SH7724 - select PINCTRL_SH_PFC_GPIO + bool "SH-Mobile R2R pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7734 - def_bool y - depends on CPU_SUBTYPE_SH7734 - select PINCTRL_SH_PFC_GPIO + bool "SH7734 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7757 - def_bool y - depends on CPU_SUBTYPE_SH7757 - select PINCTRL_SH_PFC_GPIO + bool "SH7757 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7785 - def_bool y - depends on CPU_SUBTYPE_SH7785 - select PINCTRL_SH_PFC_GPIO + bool "SH7785 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7786 - def_bool y - depends on CPU_SUBTYPE_SH7786 - select PINCTRL_SH_PFC_GPIO + bool "SH7786 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SHX3 - def_bool y - depends on CPU_SUBTYPE_SHX3 - select PINCTRL_SH_PFC_GPIO -endif + bool "SH-X3 pin control support" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 82ebb2a91ee0..8c95abcfcc00 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -38,3 +38,18 @@ obj-$(CONFIG_PINCTRL_PFC_SH7757) += pfc-sh7757.o obj-$(CONFIG_PINCTRL_PFC_SH7785) += pfc-sh7785.o obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o + +ifeq ($(CONFIG_COMPILE_TEST),y) +CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a +CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a +CFLAGS_pfc-sh7269.o += -I$(srctree)/arch/sh/include/cpu-sh2a +CFLAGS_pfc-sh7720.o += -I$(srctree)/arch/sh/include/cpu-sh3 +CFLAGS_pfc-sh7722.o += -I$(srctree)/arch/sh/include/cpu-sh4 +CFLAGS_pfc-sh7723.o += -I$(srctree)/arch/sh/include/cpu-sh4 +CFLAGS_pfc-sh7724.o += -I$(srctree)/arch/sh/include/cpu-sh4 +CFLAGS_pfc-sh7734.o += -I$(srctree)/arch/sh/include/cpu-sh4 +CFLAGS_pfc-sh7757.o += -I$(srctree)/arch/sh/include/cpu-sh4 +CFLAGS_pfc-sh7785.o += -I$(srctree)/arch/sh/include/cpu-sh4 +CFLAGS_pfc-sh7786.o += -I$(srctree)/arch/sh/include/cpu-sh4 +CFLAGS_pfc-shx3.o += -I$(srctree)/arch/sh/include/cpu-sh4 +endif diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index f1cfcc8c6544..3f989f5cb021 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -571,6 +571,13 @@ static const struct of_device_id sh_pfc_of_table[] = { .compatible = "renesas,pfc-r8a7795", .data = &r8a7795_pinmux_info, }, +#ifdef DEBUG + { + /* For sanity checks only (nothing matches against this) */ + .compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */ + .data = &r8a7795es1_pinmux_info, + }, +#endif /* DEBUG */ #endif #ifdef CONFIG_PINCTRL_PFC_R8A7796 { @@ -709,6 +716,128 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } #define DEV_PM_OPS NULL #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ +#ifdef DEBUG +static bool is0s(const u16 *enum_ids, unsigned int n) +{ + unsigned int i; + + for (i = 0; i < n; i++) + if (enum_ids[i]) + return false; + + return true; +} + +static unsigned int sh_pfc_errors; +static unsigned int sh_pfc_warnings; + +static void sh_pfc_check_cfg_reg(const char *drvname, + const struct pinmux_cfg_reg *cfg_reg) +{ + unsigned int i, n, rw, fw; + + if (cfg_reg->field_width) { + /* Checked at build time */ + return; + } + + for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) { + if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) { + pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n", + drvname, cfg_reg->reg, rw, rw + fw - 1); + sh_pfc_warnings++; + } + n += 1 << fw; + rw += fw; + } + + if (rw != cfg_reg->reg_width) { + pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n", + drvname, cfg_reg->reg, rw, cfg_reg->reg_width); + sh_pfc_errors++; + } + + if (n != cfg_reg->nr_enum_ids) { + pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n", + drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n); + sh_pfc_errors++; + } +} + +static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) +{ + const struct sh_pfc_function *func; + const char *drvname = info->name; + unsigned int *refcnts; + unsigned int i, j, k; + + pr_info("Checking %s\n", drvname); + + /* Check groups and functions */ + refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL); + if (!refcnts) + return; + + for (i = 0; i < info->nr_functions; i++) { + func = &info->functions[i]; + for (j = 0; j < func->nr_groups; j++) { + for (k = 0; k < info->nr_groups; k++) { + if (!strcmp(func->groups[j], + info->groups[k].name)) { + refcnts[k]++; + break; + } + } + + if (k == info->nr_groups) { + pr_err("%s: function %s: group %s not found\n", + drvname, func->name, func->groups[j]); + sh_pfc_errors++; + } + } + } + + for (i = 0; i < info->nr_groups; i++) { + if (!refcnts[i]) { + pr_err("%s: orphan group %s\n", drvname, + info->groups[i].name); + sh_pfc_errors++; + } else if (refcnts[i] > 1) { + pr_err("%s: group %s referred by %u functions\n", + drvname, info->groups[i].name, refcnts[i]); + sh_pfc_warnings++; + } + } + + kfree(refcnts); + + /* Check config register descriptions */ + for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++) + sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]); +} + +static void sh_pfc_check_driver(const struct platform_driver *pdrv) +{ + unsigned int i; + + pr_warn("Checking builtin pinmux tables\n"); + + for (i = 0; pdrv->id_table[i].name[0]; i++) + sh_pfc_check_info((void *)pdrv->id_table[i].driver_data); + +#ifdef CONFIG_OF + for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++) + sh_pfc_check_info(pdrv->driver.of_match_table[i].data); +#endif + + pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors, + sh_pfc_warnings); +} + +#else /* !DEBUG */ +static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {} +#endif /* !DEBUG */ + static int sh_pfc_probe(struct platform_device *pdev) { #ifdef CONFIG_OF @@ -840,6 +969,7 @@ static struct platform_driver sh_pfc_driver = { static int __init sh_pfc_init(void) { + sh_pfc_check_driver(&sh_pfc_driver); return platform_driver_register(&sh_pfc_driver); } postcore_initcall(sh_pfc_init); diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 4f3a34ee1cd4..97c1332c1045 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -252,7 +252,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip) * Function GPIOs */ -#ifdef CONFIG_SUPERH +#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO static int gpio_function_request(struct gpio_chip *gc, unsigned offset) { static bool __print_once; @@ -292,7 +292,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip) return 0; } -#endif +#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */ /* ----------------------------------------------------------------------------- * Register/unregister @@ -369,7 +369,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node) return 0; -#ifdef CONFIG_SUPERH +#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO /* * Register the GPIO to pin mappings. As pins with GPIO ports * must come first in the ranges, skip the pins without GPIO @@ -397,7 +397,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL); if (IS_ERR(chip)) return PTR_ERR(chip); -#endif /* CONFIG_SUPERH */ +#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */ return 0; } diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c index 310c6f3ee7cc..0af1ef82a1a8 100644 --- a/drivers/pinctrl/sh-pfc/pfc-emev2.c +++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c @@ -1433,7 +1433,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP( 0, PORT31_FN, /* PIN: J18 */ 0, PORT30_FN, /* PIN: H18 */ 0, PORT29_FN, /* PIN: G18 */ @@ -1466,9 +1466,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_JT_SEL, PORT2_FN, /* PIN: V9 */ 0, PORT1_FN, /* PIN: U10 */ 0, PORT0_FN, /* PIN: V10 */ - } + )) }, - { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP( FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */ FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */ FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */ @@ -1501,9 +1501,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_LCD3_R2, PORT34_FN, /* PIN: A19 */ FN_LCD3_R1, PORT33_FN, /* PIN: B20 */ FN_LCD3_R0, PORT32_FN, /* PIN: A20 */ - } + )) }, - { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP( FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */ FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */ FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */ @@ -1536,9 +1536,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */ FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */ FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */ - } + )) }, - { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP( FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */ FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */ FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */ @@ -1571,9 +1571,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */ FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */ FN_AB_A20, PORT96_FN, /* PIN: M21 */ - } + )) }, - { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP( 0, 0, FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */ FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */ @@ -1606,11 +1606,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */ FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */ FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */ - } + )) }, { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 2, 2, 2, 2, 2, 2) { + GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, + 2, 2), + GROUP( /* 31 - 12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1624,11 +1626,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 1 - 0 */ FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0, - } + )) }, { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) { + GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 2), + GROUP( /* 31 - 2 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1636,11 +1640,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 1 - 0 */ FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0, - } + )) }, { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) { + GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 2), + GROUP( /* 31 - 2 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1648,11 +1654,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 1 - 0 */ FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0, - } + )) }, { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 2, 2, 2, 2, 2, 2, 2, 2) { + GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2), + GROUP( /* 31 - 14 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1673,11 +1680,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11, /* 1 - 0 */ FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0, - } + )) }, { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2) { + GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 2, 2, 2), + GROUP( /* 31 - 10 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1692,11 +1701,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0, /* 1 - 0 */ FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0, - } + )) }, { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) { + GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 2), + GROUP( /* 31 - 2 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1704,7 +1715,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 1 - 0 */ FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0, - } + )) }, { }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 5acbacb3727f..bf12849defdb 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2284,7 +2284,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(328, 0xe6053148), PORTCR(329, 0xe6053149), - { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { + { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP( MSEL1CR_31_0, MSEL1CR_31_1, 0, 0, 0, 0, @@ -2317,9 +2317,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MSEL1CR_02_0, MSEL1CR_02_1, MSEL1CR_01_0, MSEL1CR_01_1, MSEL1CR_00_0, MSEL1CR_00_1, - } + )) }, - { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { + { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP( MSEL3CR_31_0, MSEL3CR_31_1, 0, 0, 0, 0, @@ -2352,9 +2352,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, MSEL3CR_01_0, MSEL3CR_01_1, MSEL3CR_00_0, MSEL3CR_00_1, - } + )) }, - { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { + { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP( 0, 0, MSEL4CR_30_0, MSEL4CR_30_1, MSEL4CR_29_0, MSEL4CR_29_1, @@ -2387,9 +2387,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, MSEL4CR_01_0, MSEL4CR_01_1, 0, 0, - } + )) }, - { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) { + { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP( MSEL5CR_31_0, MSEL5CR_31_1, MSEL5CR_30_0, MSEL5CR_30_1, MSEL5CR_29_0, MSEL5CR_29_1, @@ -2422,9 +2422,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, - } + )) < |