diff options
| author | Yixun Lan <yixun.lan@amlogic.com> | 2018-08-07 10:06:34 +0800 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2018-08-29 10:34:53 +0200 |
| commit | 29ae0952e85f3ef2ac87eb39f9cc867e2458a0ad (patch) | |
| tree | 71869940040a91e9dc2e13f5fc6e8af92cdc93bf /drivers/pinctrl/meson/Kconfig | |
| parent | 3cd3c83f675259aaf6bebdafb37622be2139fb8f (diff) | |
pinctrl: meson-g12a: add pinctrl driver support
Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC, both use same pinmux ops (register layout).
A new driver is needed here due to the differences in the pins.
Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register bits for
the pin mux definition. The new design greatly simplify the software model.
For the detail example, one 32bit register can be divided into 8 parts,
each has 4 bits whose value start from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.
Please note, the GPIOE is actually located at AO (always on) bank.
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/meson/Kconfig')
| -rw-r--r-- | drivers/pinctrl/meson/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index c80951d6caff..9ab537eb78a3 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG config PINCTRL_MESON_AXG_PMX bool +config PINCTRL_MESON_G12A + bool "Meson g12a Soc pinctrl driver" + depends on ARM64 + select PINCTRL_MESON_AXG_PMX + default y + endif |